SPRS565D April 2009 – June 2014 TMS320C6743
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
NO. | MIN | MAX | UNIT | |||
---|---|---|---|---|---|---|
25 | td(SCSL_SPC)S | Required delay from SPI0_SCS asserted at slave to first SPI0_CLK edge at slave. | 2P | ns | ||
26 | td(SPC_SCSH)S | Required delay from final SPI0_CLK edge before SPI0_SCS is deasserted. | Polarity = 0, Phase = 0,
from SPI0_CLK falling |
0.5tc(SPC)M + P + 5 | ns | |
Polarity = 0, Phase = 1,
from SPI0_CLK falling |
P + 5 | |||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
0.5tc(SPC)M + P + 5 | |||||
Polarity = 1, Phase = 1,
from SPI0_CLK rising |
P + 5 | |||||
27 | tena(SCSL_SOMI)S | Delay from master asserting SPI0_SCS to slave driving SPI0_SOMI valid | P + 18.5 | |||
28 | tdis(SCSH_SOMI)S | Delay from master deasserting SPI0_SCS to slave 3-stating SPI0_SOMI | P + 18.5 |