SPRS565D
April 2009 – June 2014
TMS320C6743
PRODUCTION DATA.
1
TMS320C6743 Fixed- and Floating-Point Digital Signal Processor
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Overview
3.1
Device Characteristics
3.2
Device Compatibility
3.3
DSP Subsystem
3.3.1
C674x DSP CPU Description
3.3.2
DSP Memory Mapping
3.3.2.1
External Memories
3.3.2.2
DSP Internal Memories
3.3.2.3
C674x CPU
3.4
Memory Map Summary
3.4.1
C6743 Top Level Memory Map
3.5
Pin Assignments
3.5.1
Pin Map (Bottom View)
3.6
Terminal Functions
3.6.1
Device Reset and JTAG
3.6.2
High-Frequency Oscillator and PLL
3.6.3
External Memory Interface A (ASYNC)
3.6.4
External Memory Interface B (SDRAM only)
3.6.5
Serial Peripheral Interface Modules (SPI0)
3.6.6
Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
3.6.7
Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
3.6.8
Enhanced Quadrature Encoder Pulse Module (eQEP)
3.6.9
Boot
3.6.10
Universal Asynchronous Receiver/Transmitters (UART0, UART2)
3.6.11
Inter-Integrated Circuit Modules (I2C0, I2C1)
3.6.12
Timers
3.6.13
Multichannel Audio Serial Ports (McASP0, McASP1)
3.6.14
Ethernet Media Access Controller (EMAC)
3.6.15
Multimedia Card/Secure Digital (MMC/SD)
3.6.16
General-Purpose IO Only Terminal Functions
3.6.17
Reserved and No Connect Terminal Functions
3.6.18
Supply and Ground Terminal Functions
4
Device Configuration
4.1
Boot Modes
4.2
SYSCFG Module
4.3
Pullup/Pulldown Resistors
5
Device Operating Conditions
5.1
Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
5.2
Handling Ratings
5.3
Recommended Operating Conditions
5.4
Notes on Recommended Power-On Hours (POH)
5.5
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
6
Peripheral Information and Electrical Specifications
6.1
Parameter Information
6.1.1
Parameter Information Device-Specific Information
6.1.1.1
Signal Transition Levels
6.2
Recommended Clock and Control Signal Transition Behavior
6.3
Power Supplies
6.3.1
Power-On Sequence
6.3.2
Power-Off Sequence
6.4
Reset
6.4.1
Power-On Reset (POR)
6.4.2
Warm Reset
6.4.3
Reset Electrical Data Timings
6.5
Crystal Oscillator or External Clock Input
6.6
Clock PLLs
6.6.1
PLL Device-Specific Information
6.6.2
Device Clock Generation
6.6.3
PLL Controller 0 Registers
6.7
DSP Interrupts
6.8
General-Purpose Input/Output (GPIO)
6.8.1
GPIO Register Description(s)
6.8.2
GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-10
Timing Requirements for GPIO Inputs (see )
Table 6-11
Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
6.8.3
GPIO Peripheral External Interrupts Electrical Data/Timing
Table 6-12
Timing Requirements for External Interrupts (see )
6.9
EDMA
6.10
External Memory Interface A (EMIFA)
6.10.1
EMIFA Asynchronous Memory Support
6.10.2
EMIFA Connection Examples
6.10.3
External Memory Interface (EMIF) Registers
6.10.4
EMIFA Electrical Data/Timing
Table 6-19
EMIFA Asynchronous Memory Timing Requirements
Table 6-20
EMIFA Asynchronous Memory Switching Characteristics
6.11
External Memory Interface B (EMIFB)
6.11.1
EMIFB SDRAM Loading Limitations
6.11.2
Interfacing to SDRAM
6.11.3
EMIFB Electrical Data/Timing
Table 6-24
EMIFB SDRAM Interface Timing Requirements
Table 6-25
EMIFB SDRAM Interface Switching Characteristics
6.12
Memory Protection Units
6.13
MMC / SD / SDIO (MMCSD)
6.13.1
MMCSD Peripheral Register Description(s)
6.13.2
MMC/SD Electrical Data/Timing
Table 6-29
Timing Requirements for MMC/SD Module (see and )
Table 6-30
Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module (see through )
6.14
Ethernet Media Access Controller (EMAC)
6.14.1
EMAC Peripheral Register Description(s)
6.14.2
EMAC Electrical Data/Timing
6.15
Management Data Input/Output (MDIO)
6.15.1
MDIO Peripheral Register Description(s)
6.15.2
Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-38
Timing Requirements for MDIO Input (see and )
Table 6-39
Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
6.16
Multichannel Audio Serial Ports (McASP0, McASP1)
6.16.1
McASP Peripheral Registers Description(s)
6.16.2
McASP Electrical Data/Timing
6.16.2.1
Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-44
McASP0 Timing Requirements
Table 6-45
McASP0 Switching Characteristics
6.16.2.2
Multichannel Audio Serial Port 1 (McASP1) Timing
Table 6-46
McASP1 Timing Requirements
Table 6-47
McASP1 Switching Characteristics
6.17
Serial Peripheral Interface Ports (SPI0)
6.17.1
SPI Peripheral Registers Description(s)
6.17.2
SPI Electrical Data/Timing
6.17.2.1
Serial Peripheral Interface (SPI) Timing
Table 6-49
General Timing Requirements for SPI0 Master Modes
Table 6-50
General Timing Requirements for SPI0 Slave Modes
Table 6-51
Additional SPI0 Master Timings, 4-Pin Enable Option
Table 6-52
Additional SPI0 Master Timings, 4-Pin Chip Select Option
Table 6-53
Additional SPI0 Master Timings, 5-Pin Option
Table 6-54
Additional SPI0 Slave Timings, 4-Pin Enable Option
Table 6-55
Additional SPI0 Slave Timings, 4-Pin Chip Select Option
Table 6-56
Additional SPI0 Slave Timings, 5-Pin Option
6.18
Enhanced Capture (eCAP) Peripheral
Table 6-58
Enhanced Capture (eCAP) Timing Requirement
Table 6-59
eCAP Switching Characteristics
6.19
Enhanced Quadrature Encoder (eQEP) Peripheral
Table 6-61
Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
Table 6-62
eQEP Switching Characteristics
6.20
Enhanced Pulse Width Modulator (eHRPWM) Modules
6.20.1
Enhanced Pulse Width Modulator (eHRPWM) Timing
Table 6-64
eHRPWM Timing Requirements
Table 6-65
eHRPWM Switching Characteristics
6.20.2
Trip-Zone Input Timing
6.21
Timers
6.21.1
Timer Electrical Data/Timing
Table 6-69
Timing Requirements for Timer Input (see )
Table 6-70
Switching Characteristics Over Recommended Operating Conditions for Timer Output
6.22
Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
6.22.1
I2C Device-Specific Information
6.22.2
I2C Peripheral Registers Description(s)
6.22.3
I2C Electrical Data/Timing
6.22.3.1
Inter-Integrated Circuit (I2C) Timing
Table 6-72
I2C Input Timing Requirements
Table 6-73
I2C Switching Characteristics
6.23
Universal Asynchronous Receiver/Transmitter (UART)
6.23.1
UART Peripheral Registers Description(s)
6.23.2
UART Electrical Data/Timing
Table 6-75
Timing Requirements for UARTx Receive (see )
Table 6-76
Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
6.24
Power and Sleep Controller (PSC)
6.24.1
PSC Peripheral Registers Description(s)
6.24.2
Power Domain and Module Topology
6.24.2.1
Power Domain States
6.24.2.2
Module States
6.25
Programmable Real-Time Unit Subsystem (PRUSS)
6.25.1
PRUSS Register Descriptions
6.26
Emulation Logic
6.26.1
JTAG Port Description
6.26.2
Scan Chain Configuration Parameters
6.26.3
JTAG 1149.1 Boundary Scan Considerations
6.27
IEEE 1149.1 JTAG
6.27.1
JTAG Peripheral Register Description(s) – JTAG ID Register
6.27.2
JTAG Test-Port Electrical Data/Timing
Table 6-91
Timing Requirements for JTAG Test Port (see )
Table 6-92
Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
7
Device and Documentation Support
7.1
Device Support
7.1.1
Development Support
7.1.2
Device and Development-Support Tool Nomenclature
7.2
Documentation Support
7.3
Support Resources
7.4
Trademarks
7.5
Electrostatic Discharge Caution
7.6
Glossary
8
Mechanical Packaging and Orderable Information
8.1
Thermal Data for ZKB
8.2
Thermal Data for PTP
8.3
Supplementary Information About the 176-pin PTP PowerPAD™ Package
8.3.1
Standoff Height
8.3.2
PowerPAD™ PCB Footprint
8.4
Mechanical Drawings
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
ZKB|256
PTP|176
サーマルパッド・メカニカル・データ
PTP|176
PPTD141B
発注情報
sprs565d_oa
sprs565d_pm
7.1
Device Support