SPRS565D April   2009  – June 2014 TMS320C6743

PRODUCTION DATA.  

  1. 1TMS320C6743 Fixed- and Floating-Point Digital Signal Processor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. 3.4.1 C6743 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  External Memory Interface A (ASYNC)
      4. 3.6.4  External Memory Interface B (SDRAM only)
      5. 3.6.5  Serial Peripheral Interface Modules (SPI0)
      6. 3.6.6  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      7. 3.6.7  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      8. 3.6.8  Enhanced Quadrature Encoder Pulse Module (eQEP)
      9. 3.6.9  Boot
      10. 3.6.10 Universal Asynchronous Receiver/Transmitters (UART0, UART2)
      11. 3.6.11 Inter-Integrated Circuit Modules (I2C0, I2C1)
      12. 3.6.12 Timers
      13. 3.6.13 Multichannel Audio Serial Ports (McASP0, McASP1)
      14. 3.6.14 Ethernet Media Access Controller (EMAC)
      15. 3.6.15 Multimedia Card/Secure Digital (MMC/SD)
      16. 3.6.16 General-Purpose IO Only Terminal Functions
      17. 3.6.17 Reserved and No Connect Terminal Functions
      18. 3.6.18 Supply and Ground Terminal Functions
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 PLL Controller 0 Registers
    7. 6.7  DSP Interrupts
    8. 6.8  General-Purpose Input/Output (GPIO)
      1. 6.8.1 GPIO Register Description(s)
      2. 6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-10 Timing Requirements for GPIO Inputs (see )
        2. Table 6-11 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-12 Timing Requirements for External Interrupts (see )
    9. 6.9  EDMA
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Connection Examples
      3. 6.10.3 External Memory Interface (EMIF) Registers
      4. 6.10.4 EMIFA Electrical Data/Timing
        1. Table 6-19 EMIFA Asynchronous Memory Timing Requirements
        2. Table 6-20 EMIFA Asynchronous Memory Switching Characteristics
    11. 6.11 External Memory Interface B (EMIFB)
      1. 6.11.1 EMIFB SDRAM Loading Limitations
      2. 6.11.2 Interfacing to SDRAM
      3. 6.11.3 EMIFB Electrical Data/Timing
        1. Table 6-24 EMIFB SDRAM Interface Timing Requirements
        2. Table 6-25 EMIFB SDRAM Interface Switching Characteristics
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD)
      1. 6.13.1 MMCSD Peripheral Register Description(s)
      2. 6.13.2 MMC/SD Electrical Data/Timing
        1. Table 6-29 Timing Requirements for MMC/SD Module (see and )
        2. Table 6-30 Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module (see through )
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Peripheral Register Description(s)
      2. 6.14.2 EMAC Electrical Data/Timing
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Peripheral Register Description(s)
      2. 6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-38 Timing Requirements for MDIO Input (see and )
        2. Table 6-39 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    16. 6.16 Multichannel Audio Serial Ports (McASP0, McASP1)
      1. 6.16.1 McASP Peripheral Registers Description(s)
      2. 6.16.2 McASP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-44 McASP0 Timing Requirements
          2. Table 6-45 McASP0 Switching Characteristics
        2. 6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
          1. Table 6-46 McASP1 Timing Requirements
          2. Table 6-47 McASP1 Switching Characteristics
    17. 6.17 Serial Peripheral Interface Ports (SPI0)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-49 General Timing Requirements for SPI0 Master Modes
          2. Table 6-50 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-51 Additional SPI0 Master Timings, 4-Pin Enable Option
          4. Table 6-52 Additional SPI0 Master Timings, 4-Pin Chip Select Option
          5. Table 6-53 Additional SPI0 Master Timings, 5-Pin Option
          6. Table 6-54 Additional SPI0 Slave Timings, 4-Pin Enable Option
          7. Table 6-55 Additional SPI0 Slave Timings, 4-Pin Chip Select Option
          8. Table 6-56 Additional SPI0 Slave Timings, 5-Pin Option
    18. 6.18 Enhanced Capture (eCAP) Peripheral
      1. Table 6-58 Enhanced Capture (eCAP) Timing Requirement
      2. Table 6-59 eCAP Switching Characteristics
    19. 6.19 Enhanced Quadrature Encoder (eQEP) Peripheral
      1. Table 6-61 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
      2. Table 6-62 eQEP Switching Characteristics
    20. 6.20 Enhanced Pulse Width Modulator (eHRPWM) Modules
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-64 eHRPWM Timing Requirements
        2. Table 6-65 eHRPWM Switching Characteristics
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 Timers
      1. 6.21.1 Timer Electrical Data/Timing
        1. Table 6-69 Timing Requirements for Timer Input (see )
        2. Table 6-70 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    22. 6.22 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 6.22.1 I2C Device-Specific Information
      2. 6.22.2 I2C Peripheral Registers Description(s)
      3. 6.22.3 I2C Electrical Data/Timing
        1. 6.22.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-72 I2C Input Timing Requirements
          2. Table 6-73 I2C Switching Characteristics
    23. 6.23 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.23.1 UART Peripheral Registers Description(s)
      2. 6.23.2 UART Electrical Data/Timing
        1. Table 6-75 Timing Requirements for UARTx Receive (see )
        2. Table 6-76 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    24. 6.24 Power and Sleep Controller (PSC)
      1. 6.24.1 PSC Peripheral Registers Description(s)
      2. 6.24.2 Power Domain and Module Topology
        1. 6.24.2.1 Power Domain States
        2. 6.24.2.2 Module States
    25. 6.25 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.25.1 PRUSS Register Descriptions
    26. 6.26 Emulation Logic
      1. 6.26.1 JTAG Port Description
      2. 6.26.2 Scan Chain Configuration Parameters
      3. 6.26.3 JTAG 1149.1 Boundary Scan Considerations
    27. 6.27 IEEE 1149.1 JTAG
      1. 6.27.1 JTAG Peripheral Register Description(s) – JTAG ID Register
      2. 6.27.2 JTAG Test-Port Electrical Data/Timing
        1. Table 6-91 Timing Requirements for JTAG Test Port (see )
        2. Table 6-92 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZKB
    2. 8.2 Thermal Data for PTP
    3. 8.3 Supplementary Information About the 176-pin PTP PowerPAD™ Package
      1. 8.3.1 Standoff Height
      2. 8.3.2 PowerPAD™ PCB Footprint
    4. 8.4 Mechanical Drawings

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZKB|256
  • PTP|176
サーマルパッド・メカニカル・データ
発注情報

6.7 DSP Interrupts

The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable and is listed in Table 6-7. Also, the interrupt controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 6-8 summarizes the C674x interrupt controller registers and memory locations.

Table 6-7 C6743 DSP Interrupts

EVT# INTERRUPT NAME SOURCE
0 EVT0 C674x Int Ctl 0
1 EVT1 C674x Int Ctl 1
2 EVT2 C674x Int Ctl 2
3 EVT3 C674x Int Ctl 3
4 T64P0_TINT12 Timer64P0 - TINT12
5 SYSCFG_CHIPINT2 SYSCFG_CHIPSIG Register
6 PRU_EVTOUT0 PRU Interrupt
7 EHRPWM0 HiResTimer/PWM0 Interrupt
8 EDMA3_CC0_INT1 EDMA3 CC0 Region 1 interrupt
9 EMU-DTDMA C674x-ECM
10 EHRPWM0TZ HiResTimer/PWM0 Trip Zone Interrupt
11 EMU-RTDXRX C674x-RTDX
12 EMU-RTDXTX C674x-RTDX
13 IDMAINT0 C674x-EMC
14 IDMAINT1 C674x-EMC
15 MMCSD_INT0 MMCSD MMC/SD Interrupt
16 MMCSD_INT1 MMCSD SDIO Interrupt
17 PRU_EVTOUT1 PRU Interrupt
18 EHRPWM1 HiResTimer/PWM1 Interrupt
19-21 - Reserved
22 PRU_EVTOUT2 PRU Interrupt
23 EHRPWM1TZ HiResTimer/PWM1 Trip Zone Interrupt
24 EHRPWM2 HiResTimer/PWM2 Interrupt
25 EHRPWM2TZ HiResTimer/PWM2 Trip Zone Interrupt
26 EMAC_C0RXTHRESH EMAC - Core 0 Receive Threshold Interrupt
27 EMAC_C0RX EMAC - Core 0 Receive Interrupt
28 EMAC_C0TX EMAC - Core 0 Transmit Interrupt
29 EMAC_C0MISC EMAC - Core 0 Miscellaneous Interrupt
30 EMAC_C1RXTHRESH EMAC - Core 1 Receive Threshold Interrupt
31 EMAC_C1RX EMAC - Core 1 Receive Interrupt
32 EMAC_C1TX EMAC - Core 1 Transmit Interrupt
33 EMAC_C1MISC EMAC - Core 1 Miscellaneous Interrupt
34 - Reserved
35 PRU_EVTOUT3 PRU Interrupt
36 IIC0_INT I2C0
37 SP0_INT SPI0
38 UART0_INT UART0
39 PRU_EVTOUT5 PRU Interrupt
40 T64P1_TINT12 Timer64P1 Interrupt 12
41 GPIO_B1INT GPIO Bank 1 Interrupt
42 IIC1_INT I2C1
43 - Reserved
44 PRU_EVTOUT6 PRU Interrupt
45 ECAP0 ECAP0
46 - Reserved
47 ECAP1 ECAP1
48 T64P1_TINT34 Timer64P1 Interrupt 34
49 GPIO_B2INT GPIO Bank 2 Interrupt
50 PRU_EVTOUT7 PRU Interrupt
51 ECAP2 ECAP2
52 GPIO_B3INT GPIO Bank 3 Interrupt
53 EQEP1 EQEP1
54 GPIO_B4INT GPIO Bank 4 Interrupt
55 EMIFA_INT EMIFA
56 EDMA3_CC0_ERRINT EDMA3 Channel Controller 0
57 EDMA3_TC0_ERRINT EDMA3 Transfer Controller 0
58 EDMA3_TC1_ERRINT EDMA3 Transfer Controller 1
59 GPIO_B5INT GPIO Bank 5 Interrupt
60 EMIFB_INT EMIFB Memory Error Interrupt
61 MCASP_INT McASP0,1 Combined RX/TX Interrupts
62 GPIO_B6INT GPIO Bank 6 Interrupt
63 - Reserved
64 T64P0_TINT34 Timer64P0 Interrupt 34
65 GPIO_B0INT GPIO Bank 0 Interrupt
66 PRU_EVTOUT4 PRU Interrupt
67 SYSCFG_CHIPINT3 SYSCFG_CHIPSIG Register
68 EQEP0 EQEP0
69 UART2_INT UART2
70 PSC0_ALLINT PSC0
71 PSC1_ALLINT PSC1
72 GPIO_B7INT GPIO Bank 7 Interrupt
73 - Reserved
74 MPU_BOOTCFG_ERR Shared MPU and SYSCFG Address/Protection Error Interrupt
75-77 - Reserved
78  T64P0_CMPINT0  Timer64P0 - Compare 0
79  T64P0_CMPINT1  Timer64P0 - Compare 1
80  T64P0_CMPINT2  Timer64P0 - Compare 2
81  T64P0_CMPINT3  Timer64P0 - Compare 3
82  T64P0_CMPINT4  Timer64P0 - Compare 4
83  T64P0_CMPINT5  Timer64P0 - Compare 5
84  T64P0_CMPINT6  Timer64P0 - Compare 6
85  T64P0_CMPINT7  Timer64P0 - Compare 7
86  T64P1_CMPINT0  Timer64P1 - Compare 0
87  T64P1_CMPINT1  Timer64P1 - Compare 1
88  T64P1_CMPINT2  Timer64P1 - Compare 2
89  T64P1_CMPINT3  Timer64P1 - Compare 3
90  T64P1_CMPINT4  Timer64P1 - Compare 4
91  T64P1_CMPINT5  Timer64P1 - Compare 5
92  T64P1_CMPINT6  Timer64P1 - Compare 6
93  T64P1_CMPINT7  Timer64P1 - Compare 7
94-95 - Reserved
96 INTERR C674x-Int Ctl
97 EMC_IDMAERR C674x-EMC
98-112 - Reserved
113 PMC_ED C674x-PMC
114-115 - Reserved
116 UMC_ED1 C674x-UMC
117 UMC_ED2 C674x-UMC
118 PDC_INT C674x-PDC
119 SYS_CMPA C674x-SYS
120 PMC_CMPA C674x-PMC
121 PMC_CMPA C674x-PMC
122 DMC_CMPA C674x-DMC
123 DMC_CMPA C674x-DMC
124 UMC_CMPA C674x-UMC
125 UMC_CMPA C674x-UMC
126 EMC_CMPA C674x-EMC
127 EMC_BUSERR C674x-EMC

Table 6-8 C674x DSP Interrupt Controller Registers

BYTE ADDRESS REGISTER NAME REGISTER DESCRIPTION
0x0180 0000 EVTFLAG0 Event flag register 0
0x0180 0004 EVTFLAG1 Event flag register 1
0x0180 0008 EVTFLAG2 Event flag register 2
0x0180 000C EVTFLAG3 Event flag register 3
0x0180 0020 EVTSET0 Event set register 0
0x0180 0024 EVTSET1 Event set register 1
0x0180 0028 EVTSET2 Event set register 2
0x0180 002C EVTSET3 Event set register 3
0x0180 0040 EVTCLR0 Event clear register 0
0x0180 0044 EVTCLR1 Event clear register 1
0x0180 0048 EVTCLR2 Event clear register 2
0x0180 004C EVTCLR3 Event clear register 3
0x0180 0080 EVTMASK0 Event mask register 0
0x0180 0084 EVTMASK1 Event mask register 1
0x0180 0088 EVTMASK2 Event mask register 2
0x0180 008C EVTMASK3 Event mask register 3
0x0180 00A0 MEVTFLAG0 Masked event flag register 0
0x0180 00A4 MEVTFLAG1 Masked event flag register 1
0x0180 00A8 MEVTFLAG2 Masked event flag register 2
0x0180 00AC MEVTFLAG3 Masked event flag register 3
0x0180 00C0 EXPMASK0 Exception mask register 0
0x0180 00C4 EXPMASK1 Exception mask register 1
0x0180 00C8 EXPMASK2 Exception mask register 2
0x0180 00CC EXPMASK3 Exception mask register 3
0x0180 00E0 MEXPFLAG0 Masked exception flag register 0
0x0180 00E4 MEXPFLAG1 Masked exception flag register 1
0x0180 00E8 MEXPFLAG2 Masked exception flag register 2
0x0180 00EC MEXPFLAG3 Masked exception flag register 3