SPRS565D April   2009  – June 2014 TMS320C6743

PRODUCTION DATA.  

  1. 1TMS320C6743 Fixed- and Floating-Point Digital Signal Processor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. 3.4.1 C6743 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  External Memory Interface A (ASYNC)
      4. 3.6.4  External Memory Interface B (SDRAM only)
      5. 3.6.5  Serial Peripheral Interface Modules (SPI0)
      6. 3.6.6  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      7. 3.6.7  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      8. 3.6.8  Enhanced Quadrature Encoder Pulse Module (eQEP)
      9. 3.6.9  Boot
      10. 3.6.10 Universal Asynchronous Receiver/Transmitters (UART0, UART2)
      11. 3.6.11 Inter-Integrated Circuit Modules (I2C0, I2C1)
      12. 3.6.12 Timers
      13. 3.6.13 Multichannel Audio Serial Ports (McASP0, McASP1)
      14. 3.6.14 Ethernet Media Access Controller (EMAC)
      15. 3.6.15 Multimedia Card/Secure Digital (MMC/SD)
      16. 3.6.16 General-Purpose IO Only Terminal Functions
      17. 3.6.17 Reserved and No Connect Terminal Functions
      18. 3.6.18 Supply and Ground Terminal Functions
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 PLL Controller 0 Registers
    7. 6.7  DSP Interrupts
    8. 6.8  General-Purpose Input/Output (GPIO)
      1. 6.8.1 GPIO Register Description(s)
      2. 6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-10 Timing Requirements for GPIO Inputs (see )
        2. Table 6-11 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-12 Timing Requirements for External Interrupts (see )
    9. 6.9  EDMA
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Connection Examples
      3. 6.10.3 External Memory Interface (EMIF) Registers
      4. 6.10.4 EMIFA Electrical Data/Timing
        1. Table 6-19 EMIFA Asynchronous Memory Timing Requirements
        2. Table 6-20 EMIFA Asynchronous Memory Switching Characteristics
    11. 6.11 External Memory Interface B (EMIFB)
      1. 6.11.1 EMIFB SDRAM Loading Limitations
      2. 6.11.2 Interfacing to SDRAM
      3. 6.11.3 EMIFB Electrical Data/Timing
        1. Table 6-24 EMIFB SDRAM Interface Timing Requirements
        2. Table 6-25 EMIFB SDRAM Interface Switching Characteristics
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD)
      1. 6.13.1 MMCSD Peripheral Register Description(s)
      2. 6.13.2 MMC/SD Electrical Data/Timing
        1. Table 6-29 Timing Requirements for MMC/SD Module (see and )
        2. Table 6-30 Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module (see through )
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Peripheral Register Description(s)
      2. 6.14.2 EMAC Electrical Data/Timing
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Peripheral Register Description(s)
      2. 6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-38 Timing Requirements for MDIO Input (see and )
        2. Table 6-39 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    16. 6.16 Multichannel Audio Serial Ports (McASP0, McASP1)
      1. 6.16.1 McASP Peripheral Registers Description(s)
      2. 6.16.2 McASP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-44 McASP0 Timing Requirements
          2. Table 6-45 McASP0 Switching Characteristics
        2. 6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
          1. Table 6-46 McASP1 Timing Requirements
          2. Table 6-47 McASP1 Switching Characteristics
    17. 6.17 Serial Peripheral Interface Ports (SPI0)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-49 General Timing Requirements for SPI0 Master Modes
          2. Table 6-50 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-51 Additional SPI0 Master Timings, 4-Pin Enable Option
          4. Table 6-52 Additional SPI0 Master Timings, 4-Pin Chip Select Option
          5. Table 6-53 Additional SPI0 Master Timings, 5-Pin Option
          6. Table 6-54 Additional SPI0 Slave Timings, 4-Pin Enable Option
          7. Table 6-55 Additional SPI0 Slave Timings, 4-Pin Chip Select Option
          8. Table 6-56 Additional SPI0 Slave Timings, 5-Pin Option
    18. 6.18 Enhanced Capture (eCAP) Peripheral
      1. Table 6-58 Enhanced Capture (eCAP) Timing Requirement
      2. Table 6-59 eCAP Switching Characteristics
    19. 6.19 Enhanced Quadrature Encoder (eQEP) Peripheral
      1. Table 6-61 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
      2. Table 6-62 eQEP Switching Characteristics
    20. 6.20 Enhanced Pulse Width Modulator (eHRPWM) Modules
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-64 eHRPWM Timing Requirements
        2. Table 6-65 eHRPWM Switching Characteristics
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 Timers
      1. 6.21.1 Timer Electrical Data/Timing
        1. Table 6-69 Timing Requirements for Timer Input (see )
        2. Table 6-70 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    22. 6.22 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 6.22.1 I2C Device-Specific Information
      2. 6.22.2 I2C Peripheral Registers Description(s)
      3. 6.22.3 I2C Electrical Data/Timing
        1. 6.22.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-72 I2C Input Timing Requirements
          2. Table 6-73 I2C Switching Characteristics
    23. 6.23 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.23.1 UART Peripheral Registers Description(s)
      2. 6.23.2 UART Electrical Data/Timing
        1. Table 6-75 Timing Requirements for UARTx Receive (see )
        2. Table 6-76 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    24. 6.24 Power and Sleep Controller (PSC)
      1. 6.24.1 PSC Peripheral Registers Description(s)
      2. 6.24.2 Power Domain and Module Topology
        1. 6.24.2.1 Power Domain States
        2. 6.24.2.2 Module States
    25. 6.25 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.25.1 PRUSS Register Descriptions
    26. 6.26 Emulation Logic
      1. 6.26.1 JTAG Port Description
      2. 6.26.2 Scan Chain Configuration Parameters
      3. 6.26.3 JTAG 1149.1 Boundary Scan Considerations
    27. 6.27 IEEE 1149.1 JTAG
      1. 6.27.1 JTAG Peripheral Register Description(s) – JTAG ID Register
      2. 6.27.2 JTAG Test-Port Electrical Data/Timing
        1. Table 6-91 Timing Requirements for JTAG Test Port (see )
        2. Table 6-92 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZKB
    2. 8.2 Thermal Data for PTP
    3. 8.3 Supplementary Information About the 176-pin PTP PowerPAD™ Package
      1. 8.3.1 Standoff Height
      2. 8.3.2 PowerPAD™ PCB Footprint
    4. 8.4 Mechanical Drawings

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZKB|256
  • PTP|176
サーマルパッド・メカニカル・データ
発注情報

6.9 EDMA

Table 6-13 is the list of EDMA3 Channel Contoller Registers and Table 6-14 is the list of EDMA3 Transfer Controller registers. See the TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9) for more details.

Table 6-13 EDMA3 Channel Controller (EDMA3CC) Registers

BYTE ADDRESS REGISTER NAME REGISTER DESCRIPTION
0x01C0 0000 PID Peripheral Identification Register
0x01C0 0004 CCCFG EDMA3CC Configuration Register
Global Registers
0x01C0 0200 QCHMAP0 QDMA Channel 0 Mapping Register
0x01C0 0204 QCHMAP1 QDMA Channel 1 Mapping Register
0x01C0 0208 QCHMAP2 QDMA Channel 2 Mapping Register
0x01C0 020C QCHMAP3 QDMA Channel 3 Mapping Register
0x01C0 0210 QCHMAP4 QDMA Channel 4 Mapping Register
0x01C0 0214 QCHMAP5 QDMA Channel 5 Mapping Register
0x01C0 0218 QCHMAP6 QDMA Channel 6 Mapping Register
0x01C0 021C QCHMAP7 QDMA Channel 7 Mapping Register
0x01C0 0240 DMAQNUM0 DMA Channel Queue Number Register 0
0x01C0 0244 DMAQNUM1 DMA Channel Queue Number Register 1
0x01C0 0248 DMAQNUM2 DMA Channel Queue Number Register 2
0x01C0 024C DMAQNUM3 DMA Channel Queue Number Register 3
0x01C0 0260 QDMAQNUM QDMA Channel Queue Number Register
0x01C0 0284 QUEPRI Queue Priority Register(1)
0x01C0 0300 EMR Event Missed Register
0x01C0 0308 EMCR Event Missed Clear Register
0x01C0 0310 QEMR QDMA Event Missed Register
0x01C0 0314 QEMCR QDMA Event Missed Clear Register
0x01C0 0318 CCERR EDMA3CC Error Register
0x01C0 031C CCERRCLR EDMA3CC Error Clear Register
0x01C0 0320 EEVAL Error Evaluate Register
0x01C0 0340 DRAE0 DMA Region Access Enable Register for Region 0
0x01C0 0348 DRAE1 DMA Region Access Enable Register for Region 1
0x01C0 0350 DRAE2 DMA Region Access Enable Register for Region 2
0x01C0 0358 DRAE3 DMA Region Access Enable Register for Region 3
0x01C0 0380 QRAE0 QDMA Region Access Enable Register for Region 0
0x01C0 0384 QRAE1 QDMA Region Access Enable Register for Region 1
0x01C0 0388 QRAE2 QDMA Region Access Enable Register for Region 2
0x01C0 038C QRAE3 QDMA Region Access Enable Register for Region 3
0x01C0 0400 - 0x01C0 043C Q0E0-Q0E15 Event Queue Entry Registers Q0E0-Q0E15
0x01C0 0440 - 0x01C0 047C Q1E0-Q1E15 Event Queue Entry Registers Q1E0-Q1E15
0x01C0 0600 QSTAT0 Queue 0 Status Register
0x01C0 0604 QSTAT1 Queue 1 Status Register
0x01C0 0620 QWMTHRA Queue Watermark Threshold A Register
0x01C0 0640 CCSTAT EDMA3CC Status Register
Global Channel Registers
0x01C0 1000 ER Event Register
0x01C0 1008 ECR Event Clear Register
0x01C0 1010 ESR Event Set Register
0x01C0 1018 CER Chained Event Register
0x01C0 1020 EER Event Enable Register
0x01C0 1028 EECR Event Enable Clear Register
0x01C0 1030 EESR Event Enable Set Register
0x01C0 1038 SER Secondary Event Register
0x01C0 1040 SECR Secondary Event Clear Register
0x01C0 1050 IER Interrupt Enable Register
0x01C0 1058 IECR Interrupt Enable Clear Register
0x01C0 1060 IESR Interrupt Enable Set Register
0x01C0 1068 IPR Interrupt Pending Register
0x01C0 1070 ICR Interrupt Clear Register
0x01C0 1078 IEVAL Interrupt Evaluate Register
0x01C0 1080 QER QDMA Event Register
0x01C0 1084 QEER QDMA Event Enable Register
0x01C0 1088 QEECR QDMA Event Enable Clear Register
0x01C0 108C QEESR QDMA Event Enable Set Register
0x01C0 1090 QSER QDMA Secondary Event Register
0x01C0 1094 QSECR QDMA Secondary Event Clear Register
Shadow Region 0 Channel Registers
0x01C0 2000 ER Event Register
0x01C0 2008 ECR Event Clear Register
0x01C0 2010 ESR Event Set Register
0x01C0 2018 CER Chained Event Register
0x01C0 2020 EER Event Enable Register
0x01C0 2028 EECR Event Enable Clear Register
0x01C0 2030 EESR Event Enable Set Register
0x01C0 2038 SER Secondary Event Register
0x01C0 2040 SECR Secondary Event Clear Register
0x01C0 2050 IER Interrupt Enable Register
0x01C0 2058 IECR Interrupt Enable Clear Register
0x01C0 2060 IESR Interrupt Enable Set Register
0x01C0 2068 IPR Interrupt Pending Register
0x01C0 2070 ICR Interrupt Clear Register
0x01C0 2078 IEVAL Interrupt Evaluate Register
0x01C0 2080 QER QDMA Event Register
0x01C0 2084 QEER QDMA Event Enable Register
0x01C0 2088 QEECR QDMA Event Enable Clear Register
0x01C0 208C QEESR QDMA Event Enable Set Register
0x01C0 2090 QSER QDMA Secondary Event Register
0x01C0 2094 QSECR QDMA Secondary Event Clear Register
Shadow Region 1 Channel Registers
0x01C0 2200 ER Event Register
0x01C0 2208 ECR Event Clear Register
0x01C0 2210 ESR Event Set Register
0x01C0 2218 CER Chained Event Register
0x01C0 2220 EER Event Enable Register
0x01C0 2228 EECR Event Enable Clear Register
0x01C0 2230 EESR Event Enable Set Register
0x01C0 2238 SER Secondary Event Register
0x01C0 2240 SECR Secondary Event Clear Register
0x01C0 2250 IER Interrupt Enable Register
0x01C0 2258 IECR Interrupt Enable Clear Register
0x01C0 2260 IESR Interrupt Enable Set Register
0x01C0 2268 IPR Interrupt Pending Register
0x01C0 2270 ICR Interrupt Clear Register
0x01C0 2278 IEVAL Interrupt Evaluate Register
0x01C0 2280 QER QDMA Event Register
0x01C0 2284 QEER QDMA Event Enable Register
0x01C0 2288 QEECR QDMA Event Enable Clear Register
0x01C0 228C QEESR QDMA Event Enable Set Register
0x01C0 2290 QSER QDMA Secondary Event Register
0x01C0 2294 QSECR QDMA Secondary Event Clear Register
0x01C0 4000 - 0x01C0 4FFF — Parameter RAM (PaRAM)
(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.

Table 6-14 EDMA3 Transfer Controller (EDMA3TC) Registers

TRANSFER CONTROLLER 0
BYTE ADDRESS		 TRANSFER CONTROLLER 1
BYTE ADDRESS		 REGISTER NAME REGISTER DESCRIPTION
0x01C0 8000 0x01C0 8400 PID Peripheral Identification Register
0x01C0 8004 0x01C0 8404 TCCFG EDMA3TC Configuration Register
0x01C0 8100 0x01C0 8500 TCSTAT EDMA3TC Channel Status Register
0x01C0 8120 0x01C0 8520 ERRSTAT Error Status Register
0x01C0 8124 0x01C0 8524 ERREN Error Enable Register
0x01C0 8128 0x01C0 8528 ERRCLR Error Clear Register
0x01C0 812C 0x01C0 852C ERRDET Error Details Register
0x01C0 8130 0x01C0 8530 ERRCMD Error Interrupt Command Register
0x01C0 8140 0x01C0 8540 RDRATE Read Command Rate Register
0x01C0 8240 0x01C0 8640 SAOPT Source Active Options Register
0x01C0 8244 0x01C0 8644 SASRC Source Active Source Address Register
0x01C0 8248 0x01C0 8648 SACNT Source Active Count Register
0x01C0 824C 0x01C0 864C SADST Source Active Destination Address Register
0x01C0 8250 0x01C0 8650 SABIDX Source Active B-Index Register
0x01C0 8254 0x01C0 8654 SAMPPRXY Source Active Memory Protection Proxy Register
0x01C0 8258 0x01C0 8658 SACNTRLD Source Active Count Reload Register
0x01C0 825C 0x01C0 865C SASRCBREF Source Active Source Address B-Reference Register
0x01C0 8260 0x01C0 8660 SADSTBREF Source Active Destination Address B-Reference Register
0x01C0 8280 0x01C0 8680 DFCNTRLD Destination FIFO Set Count Reload Register
0x01C0 8284 0x01C0 8684 DFSRCBREF Destination FIFO Set Source Address B-Reference Register
0x01C0 8288 0x01C0 8688 DFDSTBREF Destination FIFO Set Destination Address B-Reference Register
0x01C0 8300 0x01C0 8700 DFOPT0 Destination FIFO Options Register 0
0x01C0 8304 0x01C0 8704 DFSRC0 Destination FIFO Source Address Register 0
0x01C0 8308 0x01C0 8708 DFCNT0 Destination FIFO Count Register 0
0x01C0 830C 0x01C0 870C DFDST0 Destination FIFO Destination Address Register 0
0x01C0 8310 0x01C0 8710 DFBIDX0 Destination FIFO B-Index Register 0
0x01C0 8314 0x01C0 8714 DFMPPRXY0 Destination FIFO Memory Protection Proxy Register 0
0x01C0 8340 0x01C0 8740 DFOPT1 Destination FIFO Options Register 1
0x01C0 8344 0x01C0 8744 DFSRC1 Destination FIFO Source Address Register 1
0x01C0 8348 0x01C0 8748 DFCNT1 Destination FIFO Count Register 1
0x01C0 834C 0x01C0 874C DFDST1 Destination FIFO Destination Address Register 1
0x01C0 8350 0x01C0 8750 DFBIDX1 Destination FIFO B-Index Register 1
0x01C0 8354 0x01C0 8754 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1
0x01C0 8380 0x01C0 8780 DFOPT2 Destination FIFO Options Register 2
0x01C0 8384 0x01C0 8784 DFSRC2 Destination FIFO Source Address Register 2
0x01C0 8388 0x01C0 8788 DFCNT2 Destination FIFO Count Register 2
0x01C0 838C 0x01C0 878C DFDST2 Destination FIFO Destination Address Register 2
0x01C0 8390 0x01C0 8790 DFBIDX2 Destination FIFO B-Index Register 2
0x01C0 8394 0x01C0 8794 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2
0x01C0 83C0 0x01C0 87C0 DFOPT3 Destination FIFO Options Register 3
0x01C0 83C4 0x01C0 87C4 DFSRC3 Destination FIFO Source Address Register 3
0x01C0 83C8 0x01C0 87C8 DFCNT3 Destination FIFO Count Register 3
0x01C0 83CC 0x01C0 87CC DFDST3 Destination FIFO Destination Address Register 3
0x01C0 83D0 0x01C0 87D0 DFBIDX3 Destination FIFO B-Index Register 3
0x01C0 83D4 0x01C0 87D4 DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3

Table 6-15 shows an abbreviation of the set of registers which make up the parameter set for each of 128 EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-16 shows the parameter set entry registers with relative memory address locations within each of the parameter sets.

Table 6-15 EDMA Parameter Set RAM

HEX ADDRESS RANGE DESCRIPTION
0x01C0 4000 - 0x01C0 401F Parameters Set 0 (8 32-bit words)
0x01C0 4020 - 0x01C0 403F Parameters Set 1 (8 32-bit words)
0x01C0 4040 - 0x01cC0 405F Parameters Set 2 (8 32-bit words)
0x01C0 4060 - 0x01C0 407F Parameters Set 3 (8 32-bit words)
0x01C0 4080 - 0x01C0 409F Parameters Set 4 (8 32-bit words)
0x01C0 40A0 - 0x01C0 40BF Parameters Set 5 (8 32-bit words)
... ...
0x01C0 4FC0 - 0x01C0 4FDF Parameters Set 126 (8 32-bit words)
0x01C0 4FE0 - 0x01C0 4FFF Parameters Set 127 (8 32-bit words)

Table 6-16 Parameter Set Entries

HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET		 ACRONYM PARAMETER ENTRY
0x0000 OPT Option
0x0004 SRC Source Address
0x0008 A_B_CNT A Count, B Count
0x000C DST Destination Address
0x0010 SRC_DST_BIDX Source B Index, Destination B Index
0x0014 LINK_BCNTRLD Link Address, B Count Reload
0x0018 SRC_DST_CIDX Source C Index, Destination C Index
0x001C CCNT C Count

Table 6-17 EDMA Events

EVENT EVENT NAME / SOURCE EVENT EVENT NAME / SOURCE
0 McASP0 Receive 16 MMCSD Receive
1 McASP0 Transmit 17 MMCSD Transmit
2 McASP1 Receive 18 -
3 McASP1 Transmit 19 -
4 - 20 PRU_EVTOUT6
5 - 21 PRU_EVTOUT7
6 GPIO Bank 0 Interrupt 22 GPIO Bank 2 Interrupt
7 GPIO Bank 1 Interrupt 23 GPIO Bank 3 Interrupt
8 UART0 Receive 24 I2C0 Receive
9 UART0 Transmit 25 I2C0 Transmit
10 Timer64P0 Event Out 12 26 I2C1 Receive
11 Timer64P0 Event Out 34 27 I2C1 Transmit
12 - 28 GPIO Bank 4 Interrupt
13 - 29 GPIO Bank 5 Interrupt
14 SPI0 Receive 30 UART2 Receive
15 SPI0 Transmit 31 UART2 Transmit