SPRS565D April 2009 – June 2014 TMS320C6743
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
Figure 6-17, EMIFB Functional Block Diagram illustrates a high-level view of the EMIFB and its connections within the device. Multiple requesters have access to EMIFB through a switched central resource (indicated as crossbar in the figure). The EMIFB implements a split transaction internal bus, allowing concurrence between reads and writes from the various requesters. See the TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (SPRUFK9) for more details.
EMIFB supports a 3.3V LVCMOS Interface.