SPRS565D April 2009 – June 2014 TMS320C6743
PRODUCTION DATA.
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Registers for the McASP are summarized in Table 6-41. The registers are accessed through the peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can also be accessed through the DMA port, as listed in Table 6-42
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-43. Note that the AFIFO Write FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control registers are accessed through the peripheral configuration port.
McASP0
BYTE ADDRESS |
McASP1
BYTE ADDRESS |
REGISTER NAME | REGISTER DESCRIPTION |
---|---|---|---|
0x01D0 0000 | 0x01D0 4000 | REV | Revision identification register |
0x01D0 0010 | 0x01D0 4010 | PFUNC | Pin function register |
0x01D0 0014 | 0x01D0 4014 | PDIR | Pin direction register |
0x01D0 0018 | 0x01D0 4018 | PDOUT | Pin data output register |
0x01D0 001C | 0x01D0 401C | PDIN | Read returns: Pin data input register |
0x01D0 001C | 0x01D0 401C | PDSET | Writes affect: Pin data set register (alternate write address: PDOUT) |
0x01D0 0020 | 0x01D0 4020 | PDCLR | Pin data clear register (alternate write address: PDOUT) |
0x01D0 0044 | 0x01D0 4044 | GBLCTL | Global control register |
0x01D0 0048 | 0x01D0 4048 | AMUTE | Audio mute control register |
0x01D0 004C | 0x01D0 404C | DLBCTL | Digital loopback control register |
0x01D0 0050 | 0x01D0 4050 | DITCTL | DIT mode control register |
0x01D0 0060 | 0x01D0 4060 | RGBLCTL | Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows receiver to be reset independently from transmitter |
0x01D0 0064 | 0x01D0 4064 | RMASK | Receive format unit bit mask register |
0x01D0 0068 | 0x01D0 4068 | RFMT | Receive bit stream format register |
0x01D0 006C | 0x01D0 406C | AFSRCTL | Receive frame sync control register |
0x01D0 0070 | 0x01D0 4070 | ACLKRCTL | Receive clock control register |
0x01D0 0074 | 0x01D0 4074 | AHCLKRCTL | Receive high-frequency clock control register |
0x01D0 0078 | 0x01D0 4078 | RTDM | Receive TDM time slot 0-31 register |
0x01D0 007C | 0x01D0 407C | RINTCTL | Receiver interrupt control register |
0x01D0 0080 | 0x01D0 4080 | RSTAT | Receiver status register |
0x01D0 0084 | 0x01D0 4084 | RSLOT | Current receive TDM time slot register |
0x01D0 0088 | 0x01D0 4088 | RCLKCHK | Receive clock check control register |
0x01D0 008C | 0x01D0 408C | REVTCTL | Receiver DMA event control register |
0x01D0 00A0 | 0x01D0 40A0 | XGBLCTL | Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows transmitter to be reset independently from receiver |
0x01D0 00A4 | 0x01D0 40A4 | XMASK | Transmit format unit bit mask register |
0x01D0 00A8 | 0x01D0 40A8 | XFMT | Transmit bit stream format register |
0x01D0 00AC | 0x01D0 40AC | AFSXCTL | Transmit frame sync control register |
0x01D0 00B0 | 0x01D0 40B0 | ACLKXCTL | Transmit clock control register |
0x01D0 00B4 | 0x01D0 40B4 | AHCLKXCTL | Transmit high-frequency clock control register |
0x01D0 00B8 | 0x01D0 40B8 | XTDM | Transmit TDM time slot 0-31 register |
0x01D0 00BC | 0x01D0 40BC | XINTCTL | Transmitter interrupt control register |
0x01D0 00C0 | 0x01D0 40C0 | XSTAT | Transmitter status register |
0x01D0 00C4 | 0x01D0 40C4 | XSLOT | Current transmit TDM time slot register |
0x01D0 00C8 | 0x01D0 40C8 | XCLKCHK | Transmit clock check control register |
0x01D0 00CC | 0x01D0 40CC | XEVTCTL | Transmitter DMA event control register |
0x01D0 0100 | 0x01D0 4100 | DITCSRA0 | Left (even TDM time slot) channel status register (DIT mode) 0 |
0x01D0 0104 | 0x01D0 4104 | DITCSRA1 | Left (even TDM time slot) channel status register (DIT mode) 1 |
0x01D0 0108 | 0x01D0 4108 | DITCSRA2 | Left (even TDM time slot) channel status register (DIT mode) 2 |
0x01D0 010C | 0x01D0 410C | DITCSRA3 | Left (even TDM time slot) channel status register (DIT mode) 3 |
0x01D0 0110 | 0x01D0 4110 | DITCSRA4 | Left (even TDM time slot) channel status register (DIT mode) 4 |
0x01D0 0114 | 0x01D0 4114 | DITCSRA5 | Left (even TDM time slot) channel status register (DIT mode) 5 |
0x01D0 0118 | 0x01D0 4118 | DITCSRB0 | Right (odd TDM time slot) channel status register (DIT mode) 0 |
0x01D0 011C | 0x01D0 411C | DITCSRB1 | Right (odd TDM time slot) channel status register (DIT mode) 1 |
0x01D0 0120 | 0x01D0 4120 | DITCSRB2 | Right (odd TDM time slot) channel status register (DIT mode) 2 |
0x01D0 0124 | 0x01D0 4124 | DITCSRB3 | Right (odd TDM time slot) channel status register (DIT mode) 3 |
0x01D0 0128 | 0x01D0 4128 | DITCSRB4 | Right (odd TDM time slot) channel status register (DIT mode) 4 |
0x01D0 012C | 0x01D0 412C | DITCSRB5 | Right (odd TDM time slot) channel status register (DIT mode) 5 |
0x01D0 0130 | 0x01D0 4130 | DITUDRA0 | Left (even TDM time slot) channel user data register (DIT mode) 0 |
0x01D0 0134 | 0x01D0 4134 | DITUDRA1 | Left (even TDM time slot) channel user data register (DIT mode) 1 |
0x01D0 0138 | 0x01D0 4138 | DITUDRA2 | Left (even TDM time slot) channel user data register (DIT mode) 2 |
0x01D0 013C | 0x01D0 413C | DITUDRA3 | Left (even TDM time slot) channel user data register (DIT mode) 3 |
0x01D0 0140 | 0x01D0 4140 | DITUDRA4 | Left (even TDM time slot) channel user data register (DIT mode) 4 |
0x01D0 0144 | 0x01D0 4144 | DITUDRA5 | Left (even TDM time slot) channel user data register (DIT mode) 5 |
0x01D0 0148 | 0x01D0 4148 | DITUDRB0 | Right (odd TDM time slot) channel user data register (DIT mode) 0 |
0x01D0 014C | 0x01D0 414C | DITUDRB1 | Right (odd TDM time slot) channel user data register (DIT mode) 1 |
0x01D0 0150 | 0x01D0 4150 | DITUDRB2 | Right (odd TDM time slot) channel user data register (DIT mode) 2 |
0x01D0 0154 | 0x01D0 4154 | DITUDRB3 | Right (odd TDM time slot) channel user data register (DIT mode) 3 |
0x01D0 0158 | 0x01D0 4158 | DITUDRB4 | Right (odd TDM time slot) channel user data register (DIT mode) 4 |
0x01D0 015C | 0x01D0 415C | DITUDRB5 | Right (odd TDM time slot) channel user data register (DIT mode) 5 |
0x01D0 0180 | 0x01D0 4180 | SRCTL0 | Serializer control register 0 |
0x01D0 0184 | 0x01D0 4184 | SRCTL1 | Serializer control register 1 |
0x01D0 0188 | 0x01D0 4188 | SRCTL2 | Serializer control register 2 |
0x01D0 018C | 0x01D0 418C | SRCTL3 | Serializer control register 3 |
0x01D0 0190 | 0x01D0 4190 | SRCTL4 | Serializer control register 4 |
0x01D0 0194 | 0x01D0 4194 | SRCTL5 | Serializer control register 5 |
0x01D0 0198 | 0x01D0 4198 | SRCTL6 | Serializer control register 6 |
0x01D0 019C | 0x01D0 419C | SRCTL7 | Serializer control register 7 |
0x01D0 01A0 | 0x01D0 41A0 | SRCTL8 | Serializer control register 8 |
0x01D0 01A4 | 0x01D0 41A4 | SRCTL9 | Serializer control register 9 |
0x01D0 01A8 | 0x01D0 41A8 | SRCTL10 | Serializer control register 10 |
0x01D0 01AC | 0x01D0 41AC | SRCTL11 | Serializer control register 11 |
0x01D0 01B0 | 0x01D0 41B0 | SRCTL12 | Serializer control register 12 |
0x01D0 01B4 | 0x01D0 41B4 | SRCTL13 | Serializer control register 13 |
0x01D0 01B8 | 0x01D0 41B8 | SRCTL14 | Serializer control register 14 |
0x01D0 01BC | 0x01D0 41BC | SRCTL15 | Serializer control register 15 |
0x01D0 0200 | 0x01D0 4200 | XBUF0(1) | Transmit buffer register for serializer 0 |
0x01D0 0204 | 0x01D0 4204 | XBUF1(1) | Transmit buffer register for serializer 1 |
0x01D0 0208 | 0x01D0 4208 | XBUF2(1) | Transmit buffer register for serializer 2 |
0x01D0 020C | 0x01D0 420C | XBUF3(1) | Transmit buffer register for serializer 3 |
0x01D0 0210 | 0x01D0 4210 | XBUF4(1) | Transmit buffer register for serializer 4 |
0x01D0 0214 | 0x01D0 4214 | XBUF5(1) | Transmit buffer register for serializer 5 |
0x01D0 0218 | 0x01D0 4218 | XBUF6(1) | Transmit buffer register for serializer 6 |
0x01D0 021C | 0x01D0 421C | XBUF7(1) | Transmit buffer register for serializer 7 |
0x01D0 0220 | 0x01D0 4220 | XBUF8(1) | Transmit buffer register for serializer 8 |
0x01D0 0224 | 0x01D0 4224 | XBUF9(1) | Transmit buffer register for serializer 9 |
0x01D0 0228 | 0x01D0 4228 | XBUF10(1) | Transmit buffer register for serializer 10 |
0x01D0 022C | 0x01D0 422C | XBUF11(1) | Transmit buffer register for serializer 11 |
0x01D0 0230 | 0x01D0 4230 | XBUF12(1) | Transmit buffer register for serializer 12 |
0x01D0 0234 | 0x01D0 4234 | XBUF13(1) | Transmit buffer register for serializer 13 |
0x01D0 0238 | 0x01D0 4238 | XBUF14(1) | Transmit buffer register for serializer 14 |
0x01D0 023C | 0x01D0 423C | XBUF15(1) | Transmit buffer register for serializer 15 |
0x01D0 0280 | 0x01D0 4280 | RBUF0(2) | Receive buffer register for serializer 0 |
0x01D0 0284 | 0x01D0 4284 | RBUF1(2) | Receive buffer register for serializer 1 |
0x01D0 0288 | 0x01D0 4288 | RBUF2(2) | Receive buffer register for serializer 2 |
0x01D0 028C | 0x01D0 428C | RBUF3(2) | Receive buffer register for serializer 3 |
0x01D0 0290 | 0x01D0 4290 | RBUF4(2) | Receive buffer register for serializer 4 |
0x01D0 0294 | 0x01D0 4294 | RBUF5(2) | Receive buffer register for serializer 5 |
0x01D0 0298 | 0x01D0 4298 | RBUF6(2) | Receive buffer register for serializer 6 |
0x01D0 029C | 0x01D0 429C | RBUF7(2) | Receive buffer register for serializer 7 |
0x01D0 02A0 | 0x01D0 42A0 | RBUF8(2) | Receive buffer register for serializer 8 |
0x01D0 02A4 | 0x01D0 42A4 | RBUF9(2) | Receive buffer register for serializer 9 |
0x01D0 02A8 | 0x01D0 42A8 | RBUF10(2) | Receive buffer register for serializer 10 |
0x01D0 02AC | 0x01D0 42AC | RBUF11(2) | Receive buffer register for serializer 11 |
0x01D0 02B0 | 0x01D0 42B0 | RBUF12(2) | Receive buffer register for serializer 12 |
0x01D0 02B4 | 0x01D0 42B4 | RBUF13(2) | Receive buffer register for serializer 13 |
0x01D0 02B8 | 0x01D0 42B8 | RBUF14(2) | Receive buffer register for serializer 14 |
0x01D0 02BC | 0x01D0 42BC | RBUF15(2) | Receive buffer register for serializer 15 |
HEX ADDRESS | McASP0
BYTE ADDRESS |
McASP1
BYTE ADDRESS |
REGISTER NAME | REGISTER DESCRIPTION |
---|---|---|---|---|
Read Accesses | 01D0 2000 | 01D0 6000 | RBUF | Receive buffer DMA port address. Cycles through receive serializers, skipping over transmit serializers and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Reads from DMA port only if RBUSEL = 0 in RFMT. |
Write Accesses | 01D0 2000 | 01D0 6000 | XBUF | Transmit buffer DMA port address. Cycles through transmit serializers, skipping over receive and inactive serializers. Starts at the lowest serializer at the beginning of each time slot. Writes to DMA port only if XBUSEL = 0 in XFMT. |
McASP0
BYTE ADDRESS |
McASP1
BYTE ADDRESS |
REGISTER NAME | REGISTER DESCRIPTION |
---|---|---|---|
0x01D0 1000 | 0x01D0 5000 | AFIFOREV | AFIFO revision identification register |
0x01D0 1010 | 0x01D0 5010 | WFIFOCTL | Write FIFO control register |
0x01D0 1014 | 0x01D0 5014 | WFIFOSTS | Write FIFO status register |
0x01D0 1018 | 0x01D0 5018 | RFIFOCTL | Read FIFO control register |
0x01D0 101C | 0x01D0 501C | RFIFOSTS | Read FIFO status register |