SPRS377F September   2008  – June 2014 TMS320C6745 , TMS320C6747

PRODUCTION DATA.  

  1. 1TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Overview
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. Table 3-4 C6747 Top Level Memory Map
      2. Table 3-5 C6745 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Terminal Functions
      1. 3.6.1  Device Reset and JTAG
      2. 3.6.2  High-Frequency Oscillator and PLL
      3. 3.6.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.6.4  External Memory Interface A (ASYNC, SDRAM)
      5. 3.6.5  External Memory Interface B (only SDRAM)
      6. 3.6.6  Serial Peripheral Interface Modules (SPI0, SPI1)
      7. 3.6.7  Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
      8. 3.6.8  Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
      9. 3.6.9  Enhanced Quadrature Encoder Pulse Module (eQEP)
      10. 3.6.10 Boot
      11. 3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      12. 3.6.12 Inter-Integrated Circuit Modules (I2C0, I2C1)
      13. 3.6.13 Timers
      14. 3.6.14 Universal Host-Port Interface (UHPI)
      15. 3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
      16. 3.6.16 Universal Serial Bus Modules (USB0, USB1)
      17. 3.6.17 Ethernet Media Access Controller (EMAC)
      18. 3.6.18 Multimedia Card/Secure Digital (MMC/SD)
      19. 3.6.19 Liquid Crystal Display Controller (LCD)
      20. 3.6.20 General Purpose Input Output (GPIO)
      21. 3.6.21 Reserved and No Connect
      22. 3.6.22 Supply and Ground
      23. 3.6.23 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Device Operating Conditions
    1. 5.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-on Sequence
      2. 6.3.2 Power-off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 PLL Controller 0 Registers
    7. 6.7  Interrupts
      1. 6.7.1 DSP Interrupts
    8. 6.8  General-Purpose Input/Output (GPIO)
      1. 6.8.1 GPIO Register Description(s)
      2. 6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-9  Timing Requirements for GPIO Inputs (see )
        2. Table 6-10 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-11 Timing Requirements for External Interrupts (see )
    9. 6.9  EDMA
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface A (EMIFA) Registers
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-19 EMIFA SDRAM Interface Timing Requirements
        2. Table 6-20 EMIFA SDRAM Interface Switching Characteristics
        3. Table 6-21 EMIFA Asynchronous Memory Timing Requirements
        4. Table 6-22 EMIFA Asynchronous Memory Switching Characteristics
    11. 6.11 External Memory Interface B (EMIFB)
      1. 6.11.1 EMIFB SDRAM Loading Limitations
      2. 6.11.2 Interfacing to SDRAM
      3. 6.11.3 EMIFB Electrical Data/Timing
        1. Table 6-26 EMIFB SDRAM Interface Timing Requirements
        2. Table 6-27 EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature Range
        3. Table 6-28 EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive Temperature Ranges
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-32 Timing Requirements for MMC/SD Module (see and )
        2. Table 6-33 Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module (see through )
    14. 6.14 Ethernet Media Access Controller (EMAC)
      1. 6.14.1 EMAC Peripheral Register Description(s)
    15. 6.15 Management Data Input/Output (MDIO)
      1. 6.15.1 MDIO Registers
      2. 6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-41 Timing Requirements for MDIO Input (see and )
        2. Table 6-42 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    16. 6.16 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
      1. 6.16.1 McASP Peripheral Registers Description(s)
      2. 6.16.2 McASP Electrical Data/Timing
        1. 6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-47 McASP0 Timing Requirements
          2. Table 6-48 McASP0 Switching Characteristics
        2. 6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
          1. Table 6-49 McASP1 Timing Requirements
          2. Table 6-50 McASP1 Switching Characteristics
        3. 6.16.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
          1. Table 6-51 McASP2 Timing Requirements
          2. Table 6-52 McASP2 Switching Characteristics
    17. 6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.17.1 SPI Peripheral Registers Description(s)
      2. 6.17.2 SPI Electrical Data/Timing
        1. 6.17.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-54 General Timing Requirements for SPI0 Master Modes
          2. Table 6-55 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-56 Additional SPI0 Master Timings, 4-Pin Enable Option
          4. Table 6-57 Additional SPI0 Master Timings, 4-Pin Chip Select Option
          5. Table 6-58 Additional SPI0 Master Timings, 5-Pin Option
          6. Table 6-59 Additional SPI0 Slave Timings, 4-Pin Enable Option
          7. Table 6-60 Additional SPI0 Slave Timings, 4-Pin Chip Select Option
          8. Table 6-61 Additional SPI0 Slave Timings, 5-Pin Option
          9. Table 6-62 General Timing Requirements for SPI1 Master Modes
          10. Table 6-63 General Timing Requirements for SPI1 Slave Modes
          11. Table 6-64 Additional SPI1 Master Timings, 4-Pin Enable Option
          12. Table 6-65 Additional SPI1 Master Timings, 4-Pin Chip Select Option
          13. Table 6-66 Additional SPI1 Master Timings, 5-Pin Option
          14. Table 6-67 Additional SPI1 Slave Timings, 4-Pin Enable Option
          15. Table 6-68 Additional SPI1 Slave Timings, 4-Pin Chip Select Option
          16. Table 6-69 Additional SPI1 Slave Timings, 5-Pin Option
    18. 6.18 Enhanced Capture (eCAP) Peripheral
      1. Table 6-71 Enhanced Capture (eCAP) Timing Requirement
      2. Table 6-72 eCAP Switching Characteristics
    19. 6.19 Enhanced Quadrature Encoder (eQEP) Peripheral
      1. Table 6-74 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
      2. Table 6-75 eQEP Switching Characteristics
    20. 6.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-77 eHRPWM Timing Requirements
        2. Table 6-78 eHRPWM Switching Characteristics
      2. 6.20.2 Trip-Zone Input Timing
    21. 6.21 LCD Controller
      1. 6.21.1 LCD Interface Display Driver (LIDD Mode)
      2. 6.21.2 LCD Raster Mode
        1. Table 6-84 LCD Raster Mode Timing
    22. 6.22 Timers
      1. 6.22.1 Timer Electrical Data/Timing
        1. Table 6-86 Timing Requirements for Timer Input (see )
        2. Table 6-87 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    23. 6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
      1. 6.23.1 I2C Device-Specific Information
      2. 6.23.2 I2C Peripheral Registers Description(s)
      3. 6.23.3 I2C Electrical Data/Timing
        1. 6.23.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-89 I2C Input Timing Requirements
          2. Table 6-90 I2C Switching Characteristics
    24. 6.24 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.24.1 UART Peripheral Registers Description(s)
      2. 6.24.2 UART Electrical Data/Timing
        1. Table 6-92 Timing Requirements for UARTx Receive (see )
        2. Table 6-93 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    25. 6.25 USB1 Host Controller Registers (USB1.1 OHCI)
      1. Table 6-95 Switching Characteristics Over Recommended Operating Conditions for USB1
      2. 6.25.1     USB1 Unused Signal Configuration
    26. 6.26 USB0 OTG (USB2.0 OTG)
      1. 6.26.1 USB2.0 Electrical Data/Timing
        1. Table 6-97 Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see )
      2. 6.26.2 USB0 Unused Signal Configuration
    27. 6.27 Host-Port Interface (UHPI)
      1. 6.27.1 HPI Device-Specific Information
      2. 6.27.2 HPI Peripheral Register Description(s)
      3. 6.27.3 HPI Electrical Data/Timing
        1. Table 6-99  Timing Requirements for Host-Port Interface Cycles
        2. Table 6-100 Switching Characteristics for Host-Port Interface Cycles
    28. 6.28 Power and Sleep Controller (PSC)
      1. 6.28.1 Power Domain and Module Topology
        1. 6.28.1.1 Power Domain States
        2. 6.28.1.2 Module States
    29. 6.29 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.29.1 PRUSS Register Descriptions
    30. 6.30 Emulation Logic
      1. 6.30.1 JTAG Port Description
      2. 6.30.2 Scan Chain Configuration Parameters
      3. 6.30.3 JTAG 1149.1 Boundary Scan Considerations
    31. 6.31 IEEE 1149.1 JTAG
      1. 6.31.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
      2. 6.31.2 JTAG Test-Port Electrical Data/Timing
        1. Table 6-115 Timing Requirements for JTAG Test Port (see )
        2. Table 6-116 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
    32. 6.32 Real Time Clock (RTC)
      1. 6.32.1 Clock Source
      2. 6.32.2 Real-Time Clock Registers
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
      2. 7.1.2 Device and Development-Support Tool Nomenclature
    2. 7.2 Documentation Support
    3. 7.3 Support Resources
    4. 7.4 Related Links
    5. 7.5 Trademarks
    6. 7.6 Electrostatic Discharge Caution
    7. 7.7 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZKB
    2. 8.2 Thermal Data for PTP
    3. 8.3 Supplementary Information About the 176-pin PTP PowerPAD™ Package
      1. 8.3.1 Standoff Height
      2. 8.3.2 PowerPAD™ PCB Footprint
    4. 8.4 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PTP|176
サーマルパッド・メカニカル・データ
発注情報

3.6.20 General Purpose Input Output (GPIO)

Table 3-25 General Purpose Input Output Terminal Functions

SIGNAL NAME PIN NO TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
GP0
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] - M16 I/O IPD EMIFA, UHPI, LCD GPIO Bank 0
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] - N14 I/O IPD
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] - N16 I/O IPD
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] - P14 I/O IPD
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] - P16 I/O IPD
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] - R14 I/O IPD
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] - T14 I/O IPD
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] - N12 I/O IPD
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] 54 M15 I/O IPU EMIFA, MMC/SD, UHPI, BOOT
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] 52 N13 I/O IPU EMIFA, MMC/SD, UHPI
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] 51 N15 I/O IPU
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] 49 P13 I/O IPU
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] 48 P15 I/O IPU
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] 46 R13 I/O IPU
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] 45 R15 I/O IPU
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] 44 T13 I/O IPU EMIFA, MMC/SD, UHPI, BOOT
GP1
EMA_CLK/OBSCLK/AHCLKR2/GP1[15] - R12 O IPU EMIFA, McASP2 GPIO Bank 1
EMA_BA[0]/LCD_D[4]/GP1[14] 25 R8 O IPU EMIFA, LCD
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] 26 P8 O IPU EMIFA, LCD, UHPI
EMA_A[12]/LCD_MCLK/GP1[12] 42 N11 O IPU EMIFA, LCD
EMA_A[11]/ LCD_AC_ENB_CS/GP1[11] 41 P11 O IPU
EMA_A[10]/LCD_VSYNC/GP1[10] 27 N8 O IPU
EMA_A[9]/LCD_HSYNC/GP1[9] 40 R11 O IPU
EMA_A[8]/LCD_PCLK/GP1[8] 39 T11 O IPU
EMA_A[7]/LCD_D[0]/GP1[7] 37 N10 O IPD
EMA_A[6]/LCD_D[1]/GP1[6] 36 P10 O IPD
EMA_A[5]/LCD_D[2]/GP1[5] 35 R10 O IPD
EMA_A[4]/LCD_D[3]/GP1[4] 34 T10 O IPD
EMA_A[3]/LCD_D[6]/GP1[3] 32 N9 O IPD
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] 31 P9 O IPU EMIFA, MMCSD, UHPI
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] 30 R9 O IPU
EMA_A[0]/LCD_D[7]/GP1[0] 29 T9 O IPD EMIFA, LCD
GP2
ACLKR0/ECAP1/APWM1/GP2[15] 130 b4 I/O IPD McASP0, eCAP1 GPIO Bank 2
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 A4 I/O IPD McASP0, EMAC, BOOT
AFSX0/GP2[13]/BOOT[10] 127 D5 I/O IPD McASP0, BOOT
ACLKX0/ECAP0/APWM0/GP2[12] 126 CD I/O IPD McASP0, eCAP0
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] 125 B5 I IPD McASP0, McASP2, USB
EMA_WAIT[0]/ UHPI_HRDY/GP2[10] 19 N6 I IPU EMIFA, UHPI
EMA_WE_DQM[0] /UHPI_HINT/AXR0[15]/GP2[9] - M14 O IPU EMIFA, UHPI, McASP0
EMA_WE_DQM[1] /UHPI_HDS2/AXR0[14]/GP2[8] - P12 O IPU
EMA_OE /UHPI_HDS1/AXR0[13]/GP2[7] 22 R7 O IPU
EMA_CS[3] /AMUTE2/GP2[6] 21 T7 O IPU EMIFA, McASP2
EMA_CS[2] /UHPI_HCS/GP2[5]/BOOT[15] 23 P7 O IPU EMIFA, UHPI, BOOT
EMA_CS[0] /UHPI_HAS/GP2[4] - T8 O IPU EMIFA, UHPI
EMA_WE /UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] 55 M13 O IPU EMIFA, UHPI, MCASP0, BOOT
EMA_RAS /EMA_CS[5]/GP2[2] - N7 O IPU EMIFA, EMIFA
EMA_CAS /EMA_CS[4]/GP2[1] - L16 O IPU
EMA_SDCKE/GP2[0] - T12 O IPU EMIFA
GP3
ACLKX1/EPWM0A/GP3[15] 162 K3 I/O IPD McASP1, eHRPWM0 GPIO Bank 3
AHCLKX1/EPWM0B/GP3[14] 160 K2 I/O IPD
EMB_A[12]/GP3[13] 89 B15 O IPD EMIFB
AFSR0/GP3[12] 131 C4 I/O IPD McASP0
AXR0[11]/AXR2[0]/GP3[11] - A5 I/O IPD EMAC,
UART1_TXD/AXR0[10]/GP3[10] 123 D6 I/O IPD UART1, McASP0
UART1_RXD/AXR0[9]/GP3[9] 122 C6 I/O IPD
AXR0[8]/MDIO_D/GP3[8] 121 B6 I/0 IPU McASP0, MDIO
AXR0[7]/MDIO_CLK/GP3[7] 120 A6 O IPD
AXR0[6]/RMII_RXER/ACLKR2/GP3[6] 118 D7 I IPD McASP0, EMAC, McASP2
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] 117 C7 I IPD
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] 116 B7 I IPD
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] 115 A7 I IPD
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] 113 D8 O IPD
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] 112 C8 O IPD
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] 111 B8 O IPD
GP4
USB0_DRVVBUS/GP4[15] - E4 O IPD USB0 GPIO Bank 4
AMUTE1/EPWMTZ/GP4[14] 132 D4 O IPD McASP1, eHRPWM0, eHRPWM1, eHRPWM2
AFSR1/GP4[13] 166 L3 I/O IPD McASP1
ACLKR1/ECAP2/APWM2/GP4[12] 165 L2 I/O IPD McASP1, eCAP2
AHCLKR1/GP4[11] - L1 I/O IPD McASP1
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] 163 K4 I/O IPD McASP1, eHRPWM0
AXR1[9]/GP4[9] - M1 I/O IPD McASP1
AXR1[8]/EPWM1A/GP4[8] 168 M2 I/O IPD McASP1, eHRPWM1 A
AXR1[7]/EPWM1B/GP4[7] 169 M3 I/O IPD McASP1, eHRPWM1 B
AXR1[6]/EPWM2A/GP4[6] 170 M4 I/O IPD McASP1, eHRPWM2 A
AXR1[5]/EPWM2B/GP4[5] 171 N1 I/O IPD McASP1, eHRPWM2 B
AXR1[4]/EQEP1B/GP4[4] 173 N2 I/O IPD McASP1, eQEP
AXR1[3]/EQEP1A/GP4[3] 174 P1 I/O IPD
AXR1[2]/GP4[2] 175 P2 I/O IPD McASP1
AXR1[1]/GP4[1] 176 R2 I/O IPD
AXR1[0]/GP4[0] 1 T3 I/O IPD
GP5
EMB_WE_DQM[0]/GP5[15] 60 K14 O IPU EMIFB GPIOBank 5
EMB_WE_DQM[1]/GP5[14] 85 C15 O IPU
SPI1_SCS[0]/UART2_TXD/GP5[13] 8 P4 O IPU SPI1, UART2
SPI1_ENA/UART2_RXD/GP5[12] 7 R4 I IPU
AXR1[11]/GP5[11] 6 T4 I/O IPU McASP1
AXR1[10]/GP5[10] 4 N3 I/O IPU
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 2 R3 I IPU UART0, I2C0, BOOT
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 3 P3 O IPU
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 T6 I IPD SPI1, eQEP1, BOOT
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 N5 I/O IPU SPI1, I2C1, BOOT
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 P5 I/O IPU
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 I IPU SPI0, UART0, eQEP0, BOOT
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I IPU
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 T5 I IPD SPI0, eQEP1, BOOT
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 P6 I IPD SPI0, eQEP0, BOOT
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 R6 I IPD
GP6
EMB_D[15]/GP6[15] 74 F13 I/O IPD EMIFB GPIO Bank 6
EMB_D[14]/GP6[14] 76 E`6 I/O IPD
EMB_D[13]/GP6[13] 78 E13 I/O IPD
EMB_D[12]/GP6[12] 79 D16 I/O IPD
EMB_D[11]/GP6[11] 80 D15 I/O IPD
EMB_D[10]/GP6[10] 82 D14 I/O IPD
EMB_D[9]/GP6[9] 83 D13 I/O IPD
EMB_D[8]/GP6[8] 84 C16 I/O IPD
EMB_D[7]/GP6[7] 62 J16 I/O IPD
EMB_D[6]/GP6[6] 63 J15 I/O IPD
EMB_D[5]/GP6[5] 64 J13 I/O IPD
EMB_D[4]/GP6[4] 66 H16 I/O IPD
EMB_D[3]/GP6[3] 68 H13 I/O IPD
EMB_D[2]/GP6[2] 70 G16 I/O IPD
EMB_D[1]/GP6[1] 72 G13 I/O IPD
EMB_D[0]/GP6[0] 73 F16 I/O IPD
GP7
EMU[0]/GP7[15] - J5 I/O IPU JTAG
RTCK/ GP7[14](3) 157 K1 I/O IPD General-Purpose IO signal
EMB_A[11]/GP7[13] 91 B12 O IPD EMIFB GPIO Bank 7
EMB_A[10]/GP7[12] 105 A9 O IPD
EMB_A[9]/GP7[11] 92 C12 O IPD
EMB_A[8]/GP7[10] 94 D12 O IPD
EMB_A[7]/GP7[9] 95 A11 O IPD
EMB_A[6]/GP7[8] 96 B11 O IPD
EMB_A[5]/GP7[7] 97 C11 O IPD
EMB_A[4]/GP7[6] 98 D11 O IPD
EMB_A[3]/GP7[5] 100 A10 O IPD
EMB_A[2]/GP7[4] 101 B10 O IPD
EMB_A[1]/GP7[3] 102 C10 O IPD
EMB_A[0]/GP7[2] 103 D10 O IPD
EMB_BA[0]/GP7[1] 107 C9 O IPU
EMB_BA[1]/GP7[0] 106 B9 O IPU
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) GP7[14] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an unknown state after reset.