JAJSDV6F November   2009  – January 2017 TMS320C6746

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Device Characteristics
    2. 3.2 Device Compatibility
    3. 3.3 DSP Subsystem
      1. 3.3.1 C674x DSP CPU Description
      2. 3.3.2 DSP Memory Mapping
        1. 3.3.2.1 External Memories
        2. 3.3.2.2 DSP Internal Memories
        3. 3.3.2.3 C674x CPU
    4. 3.4 Memory Map Summary
      1. Table 3-4 C6746 Top Level Memory Map
    5. 3.5 Pin Assignments
      1. 3.5.1 Pin Map (Bottom View)
    6. 3.6 Pin Multiplexing Control
    7. 3.7 Terminal Functions
      1. 3.7.1  Device Reset, NMI and JTAG
      2. 3.7.2  High-Frequency Oscillator and PLL
      3. 3.7.3  Real-Time Clock and 32-kHz Oscillator
      4. 3.7.4  DEEPSLEEP Power Control
      5. 3.7.5  External Memory Interface A (EMIFA)
      6. 3.7.6  DDR2/mDDR Controller
      7. 3.7.7  Serial Peripheral Interface Modules (SPI)
      8. 3.7.8  Programmable Real-Time Unit (PRU)
      9. 3.7.9  Enhanced Capture/Auxiliary PWM Modules (eCAP0)
      10. 3.7.10 Enhanced Pulse Width Modulators (eHRPWM)
      11. 3.7.11 Boot
      12. 3.7.12 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
      13. 3.7.13 Inter-Integrated Circuit Modules(I2C0, I2C1)
      14. 3.7.14 Timers
      15. 3.7.15 Multichannel Audio Serial Ports (McASP)
      16. 3.7.16 Multichannel Buffered Serial Ports (McBSP)
      17. 3.7.17 Universal Serial Bus Modules (USB0)
      18. 3.7.18 Ethernet Media Access Controller (EMAC)
      19. 3.7.19 Multimedia Card/Secure Digital (MMC/SD)
      20. 3.7.20 Universal Host-Port Interface (UHPI)
      21. 3.7.21 Universal Parallel Port (uPP)
      22. 3.7.22 Video Port Interface (VPIF)
      23. 3.7.23 General Purpose Input Output
      24. 3.7.24 Reserved and No Connect
      25. 3.7.25 Supply and Ground
    8. 3.8 Unused Pin Configurations
  4. 4Device Configuration
    1. 4.1 Boot Modes
    2. 4.2 SYSCFG Module
    3. 4.3 Pullup/Pulldown Resistors
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted)
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Notes on Recommended Power-On Hours (POH)
    5. 5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted)
  6. 6Peripheral Information and Electrical Specifications
    1. 6.1  Parameter Information
      1. 6.1.1 Parameter Information Device-Specific Information
        1. 6.1.1.1 Signal Transition Levels
    2. 6.2  Recommended Clock and Control Signal Transition Behavior
    3. 6.3  Power Supplies
      1. 6.3.1 Power-On Sequence
      2. 6.3.2 Power-Off Sequence
    4. 6.4  Reset
      1. 6.4.1 Power-On Reset (POR)
      2. 6.4.2 Warm Reset
      3. 6.4.3 Reset Electrical Data Timings
    5. 6.5  Crystal Oscillator or External Clock Input
    6. 6.6  Clock PLLs
      1. 6.6.1 PLL Device-Specific Information
      2. 6.6.2 Device Clock Generation
      3. 6.6.3 Dynamic Voltage and Frequency Scaling (DVFS)
    7. 6.7  Interrupts
      1. 6.7.1 DSP Interrupts
    8. 6.8  Power and Sleep Controller (PSC)
      1. 6.8.1 Power Domain and Module Topology
        1. 6.8.1.1 Power Domain States
        2. 6.8.1.2 Module States
    9. 6.9  Enhanced Direct Memory Access Controller (EDMA3)
      1. 6.9.1 EDMA3 Channel Synchronization Events
      2. 6.9.2 EDMA3 Peripheral Register Descriptions
    10. 6.10 External Memory Interface A (EMIFA)
      1. 6.10.1 EMIFA Asynchronous Memory Support
      2. 6.10.2 EMIFA Synchronous DRAM Memory Support
      3. 6.10.3 EMIFA SDRAM Loading Limitations
      4. 6.10.4 EMIFA Connection Examples
      5. 6.10.5 External Memory Interface Register Descriptions
      6. 6.10.6 EMIFA Electrical Data/Timing
        1. Table 6-19 Timing Requirements for EMIFA SDRAM Interface
        2. Table 6-20 Switching Characteristics for EMIFA SDRAM Interface
        3. Table 6-21 Timing Requirements for EMIFA Asynchronous Memory Interface
    11. 6.11 DDR2/mDDR Memory Controller
      1. 6.11.1 DDR2/mDDR Memory Controller Electrical Data/Timing
      2. 6.11.2 DDR2/mDDR Memory Controller Register Description(s)
      3. 6.11.3 DDR2/mDDR Interface
        1. 6.11.3.1  DDR2/mDDR Interface Schematic
        2. 6.11.3.2  Compatible JEDEC DDR2/mDDR Devices
        3. 6.11.3.3  PCB Stackup
        4. 6.11.3.4  Placement
        5. 6.11.3.5  DDR2/mDDR Keep Out Region
        6. 6.11.3.6  Bulk Bypass Capacitors
        7. 6.11.3.7  High-Speed Bypass Capacitors
        8. 6.11.3.8  Net Classes
        9. 6.11.3.9  DDR2/mDDR Signal Termination
        10. 6.11.3.10 VREF Routing
        11. 6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing
        12. 6.11.3.12 DDR2/mDDR Boundary Scan Limitations
    12. 6.12 Memory Protection Units
    13. 6.13 MMC / SD / SDIO (MMCSD0, MMCSD1)
      1. 6.13.1 MMCSD Peripheral Description
      2. 6.13.2 MMCSD Peripheral Register Description(s)
      3. 6.13.3 MMC/SD Electrical Data/Timing
        1. Table 6-40 Timing Requirements for MMC/SD (see and )
        2. Table 6-41 Switching Characteristics for MMC/SD (see through )
    14. 6.14 Multichannel Audio Serial Port (McASP)
      1. 6.14.1 McASP Peripheral Registers Description(s)
      2. 6.14.2 McASP Electrical Data/Timing
        1. 6.14.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
          1. Table 6-45 Timing Requirements for McASP0 (1.3V, 1.2V, 1.1V)
          2. Table 6-46 Timing Requirements for McASP0 (1.0V)
          3. Table 6-47 Switching Characteristics for McASP0 (1.3V, 1.2V, 1.1V)
          4. Table 6-48 Switching Characteristics for McASP0 (1.0V)
    15. 6.15 Multichannel Buffered Serial Port (McBSP)
      1. 6.15.1 McBSP Peripheral Register Description(s)
      2. 6.15.2 McBSP Electrical Data/Timing
        1. 6.15.2.1 Multichannel Buffered Serial Port (McBSP) Timing
          1. Table 6-50 Timing Requirements for McBSP0 [1.3V, 1.2V, 1.1V] (see )
          2. Table 6-51 Timing Requirements for McBSP0 [1.0V] (see )
          3. Table 6-52 Switching Characteristics for McBSP0 [1.3V, 1.2V, 1.1V] (see )
          4. Table 6-53 Switching Characteristics for McBSP0 [1.0V] (see )
          5. Table 6-54 Timing Requirements for McBSP1 [1.3V, 1.2V, 1.1V] (see )
          6. Table 6-55 Timing Requirements for McBSP1 [1.0V] (see )
          7. Table 6-56 Switching Characteristics for McBSP1 [1.3V, 1.2V, 1.1V] (see )
          8. Table 6-57 Switching Characteristics for McBSP1 [1.0V] (see )
          9. Table 6-58 Timing Requirements for McBSP0 FSR When GSYNC = 1 (see )
          10. Table 6-59 Timing Requirements for McBSP1 FSR When GSYNC = 1 (see )
    16. 6.16 Serial Peripheral Interface Ports (SPI0, SPI1)
      1. 6.16.1 SPI Peripheral Registers Description(s)
      2. 6.16.2 SPI Electrical Data/Timing
        1. 6.16.2.1 Serial Peripheral Interface (SPI) Timing
          1. Table 6-61 General Timing Requirements for SPI0 Master Modes
          2. Table 6-62 General Timing Requirements for SPI0 Slave Modes
          3. Table 6-69 General Timing Requirements for SPI1 Master Modes
          4. Table 6-70 General Timing Requirements for SPI1 Slave Modes
          5. Table 6-71 Additional SPI1 Master Timings, 4-Pin Enable Option
          6. Table 6-72 Additional SPI1 Master Timings, 4-Pin Chip Select Option
    17. 6.17 Inter-Integrated Circuit Serial Ports (I2C)
      1. 6.17.1 I2C Device-Specific Information
      2. 6.17.2 I2C Peripheral Registers Description(s)
      3. 6.17.3 I2C Electrical Data/Timing
        1. 6.17.3.1 Inter-Integrated Circuit (I2C) Timing
          1. Table 6-78 Timing Requirements for I2C Input
          2. Table 6-79 Switching Characteristics for I2C
    18. 6.18 Universal Asynchronous Receiver/Transmitter (UART)
      1. 6.18.1 UART Peripheral Registers Description(s)
      2. 6.18.2 UART Electrical Data/Timing
        1. Table 6-81 Timing Requirements for UART Receive (see )
        2. Table 6-82 Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit (see )
    19. 6.19 Universal Serial Bus OTG Controller (USB0) [USB2.0 OTG]
      1. 6.19.1 USB0 [USB2.0] Electrical Data/Timing
        1. Table 6-84 Switching Characteristics Over Recommended Operating Conditions for USB0 [USB2.0] (see )
    20. 6.20 Ethernet Media Access Controller (EMAC)
      1. 6.20.1 EMAC Peripheral Register Description(s)
        1. 6.20.1.1 EMAC Electrical Data/Timing
          1. Table 6-89 Timing Requirements for MII_RXCLK (see )
          2. Table 6-90 Timing Requirements for MII_TXCLK (see )
          3. Table 6-91 Timing Requirements for EMAC MII Receive 10/100 Mbit/s (see )
          4. Table 6-92 Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s (see )
    21. 6.21 Management Data Input/Output (MDIO)
      1. 6.21.1 MDIO Register Description(s)
      2. 6.21.2 Management Data Input/Output (MDIO) Electrical Data/Timing
        1. Table 6-96 Timing Requirements for MDIO Input (see and )
        2. Table 6-97 Switching Characteristics Over Recommended Operating Conditions for MDIO Output (see )
    22. 6.22 Host-Port Interface (UHPI)
      1. 6.22.1 HPI Device-Specific Information
      2. 6.22.2 HPI Peripheral Register Description(s)
      3. 6.22.3 HPI Electrical Data/Timing
        1. Table 6-99   Timing Requirements for Host-Port Interface [1.2V, 1.1V]
        2. Table 6-100 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.3V, 1.2V, 1.1V]
        3. Table 6-101 Switching Characteristics Over Recommended Operating Conditions for Host-Port Interface [1.0V]
    23. 6.23 Universal Parallel Port (uPP)
      1. 6.23.1 uPP Register Descriptions
        1. Table 6-102 Universal Parallel Port (uPP) Registers
      2. 6.23.2 uPP Electrical Data/Timing
        1. Table 6-103 Timing Requirements for uPP (see , , , )
        2. Table 6-104 Switching Characteristics Over Recommended Operating Conditions for uPP
    24. 6.24 Video Port Interface (VPIF)
      1. 6.24.1 VPIF Register Descriptions
        1. Table 6-105 Video Port Interface (VPIF) Registers
      2. 6.24.2 VPIF Electrical Data/Timing
        1. Table 6-106 Timing Requirements for VPIF VP_CLKINx Inputs (see )
        2. Table 6-107 Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs (see )
        3. Table 6-108 Switching Characteristics Over Recommended Operating Conditions for Video Data Shown With Respect to VP_CLKOUT2/3 (see )
    25. 6.25 Enhanced Capture (eCAP) Peripheral
      1. Table 6-110 Timing Requirements for Enhanced Capture (eCAP)
      2. Table 6-111 Switching Characteristics Over Recommended Operating Conditions for eCAP
    26. 6.26 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
      1. 6.26.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
        1. Table 6-113 Timing Requirements for eHRPWM
        2. Table 6-114 Switching Characteristics Over Recommended Operating Conditions for eHRPWM
      2. 6.26.2 Trip-Zone Input Timing
    27. 6.27 Timers
      1. 6.27.1 Timer Electrical Data/Timing
        1. Table 6-117 Timing Requirements for Timer Input (see )
        2. Table 6-118 Switching Characteristics Over Recommended Operating Conditions for Timer Output
    28. 6.28 Real Time Clock (RTC)
      1. 6.28.1 Clock Source
      2. 6.28.2 Real-Time Clock Register Descriptions
    29. 6.29 General-Purpose Input/Output (GPIO)
      1. 6.29.1 GPIO Register Description(s)
      2. 6.29.2 GPIO Peripheral Input/Output Electrical Data/Timing
        1. Table 6-121 Timing Requirements for GPIO Inputs (see )
        2. Table 6-122 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see )
      3. 6.29.3 GPIO Peripheral External Interrupts Electrical Data/Timing
        1. Table 6-123 Timing Requirements for External Interrupts (see )
    30. 6.30 Programmable Real-Time Unit Subsystem (PRUSS)
      1. 6.30.1 PRUSS Register Descriptions
    31. 6.31 Emulation Logic
      1. 6.31.1 JTAG Port Description
      2. 6.31.2 Scan Chain Configuration Parameters
      3. 6.31.3 Initial Scan Chain Configuration
      4. 6.31.4 IEEE 1149.1 JTAG
        1. 6.31.4.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
        2. 6.31.4.2 JTAG Test-Port Electrical Data/Timing
          1. Table 6-134 Timing Requirements for JTAG Test Port (see )
          2. Table 6-135 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port (see )
      5. 6.31.5 JTAG 1149.1 Boundary Scan Considerations
  7. 7Device and Documentation Support
    1. 7.1 Device Nomenclature
    2. 7.2 Tools and Software
    3. 7.3 Documentation Support
    4. 7.4 Community Resources
    5. 7.5 商標
    6. 7.6 静電気放電に関する注意事項
    7. 7.7 Export Control Notice
    8. 7.8 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Thermal Data for ZCE Package
    2. 8.2 Thermal Data for ZWT Package
    3. 8.3 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZCE|361
  • ZWT|361
サーマルパッド・メカニカル・データ
発注情報

6.11.3.11 DDR2/mDDR CK and ADDR_CTRL Routing

Figure 6-23 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A should be maximized.

TMS320C6746 f5_praar3.gifFigure 6-23 CK and ADDR_CTRL Routing and Topology

Table 6-34 CK and ADDR_CTRL Routing Specification

NO. PARAMETER MIN TYP MAX UNIT
1 Center to Center CK-CKN Spacing(3) 2w(4)
2 CK A to B/A to C Skew Length Mismatch(1) 25 Mils
3 CK B to C Skew Length Mismatch 25 Mils
4 Center to center CK to other DDR2/mDDR trace spacing(3) 4w(4)
5 CK/ADDR_CTRL nominal trace length(2) CACLM-50 CACLM CACLM+50 Mils
6 ADDR_CTRL to CK Skew Length Mismatch 100 Mils
7 ADDR_CTRL to ADDR_CTRL Skew Length Mismatch 100 Mils
8 Center to center ADDR_CTRL to other DDR2/mDDR trace spacing(3) 4w(4)
9 Center to center ADDR_CTRL to other ADDR_CTRL trace spacing(3) 3w (4)
10 ADDR_CTRL A to B/A to C Skew Length Mismatch(1) 100 Mils
11 ADDR_CTRL B to C Skew Length Mismatch 100 Mils
(1) Series terminator, if used, should be located closest to device.
(2) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.
(4) w = PCB trace width as defined in Table 6-27.

Figure 6-24 shows the topology and routing for the DQS and D net class; the routes are point to point. Skew matching across bytes is not needed nor recommended.

TMS320C6746 f6_praar3.gifFigure 6-24 DQS and D Routing and Topology

Table 6-35 DQS and D Routing Specification

NO. PARAMETER MIN TYP MAX UNIT
1 Center to center DQS to other DDR2/mDDR trace spacing(4) 4w(6)
2 DQS/D nominal trace length(1)(3) DQLM-50 DQLM DQLM+50 Mils
3 D to DQS Skew Length Mismatch(3) 100 Mils
4 D to D Skew Length Mismatch(3) 100 Mils
5 Center to center D to other DDR2/mDDR trace spacing(4)(5) 4w(6)
6 Center to Center D to other D trace spacing(4)(2) 3w(6)
(1) Series terminator, if used, should be located closest to DDR.
(2) DQLM is the longest Manhattan distance of each of the DQS and D net class.
(3) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte 1.
(4) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing congestion.
(5) D's from other DQS domains are considered other DDR2/mDDR trace.
(6) w = PCB trace width as defined in Table 6-27.

Figure 6-25 shows the routing for the DQGATE net class. Table 6-36 contains the routing specification.

TMS320C6746 f12_praar3.gifFigure 6-25 DQGATE Routing

Table 6-36 DQGATE Routing Specification

NO. PARAMETER MIN TYP MAX UNIT
1 DQGATE Length F CKB0B(1)
2 Center to center DQGATE to any other trace spacing 4w(3)
3 DQS/D nominal trace length DQLM-50 DQLM DQLM+50 Mils
4 DQGATE Skew(2) 100 Mils
(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.
(2) Skew from CKB0B1
(3) w = PCB trace width as defined in Table 6-27.