SPRS377F September 2008 – June 2014 TMS320C6745 , TMS320C6747
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
No. | PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
25 | td(SCSL_SPC)S | Required delay from SPI1_SCS asserted at slave to first SPI1_CLK edge at slave. | 2P | ns | ||
26 | td(SPC_SCSH)S | Required delay from final SPI1_CLK edge before SPI1_SCS is deasserted. | Polarity = 0, Phase = 0,
from SPI1_CLK falling |
0.5tc(SPC)M + P + 5 | ns | |
Polarity = 0, Phase = 1,
from SPI1_CLK falling |
P + 5 | |||||
Polarity = 1, Phase = 0,
from SPI1_CLK rising |
0.5tc(SPC)M + P + 5 | |||||
Polarity = 1, Phase = 1,
from SPI1_CLK rising |
P + 5 | |||||
27 | tena(SCSL_SOMI)S | Delay from master asserting SPI1_SCS to slave driving SPI1_SOMI valid | P + 19 | ns | ||
28 | tdis(SCSH_SOMI)S | Delay from master deasserting SPI1_SCS to slave 3-stating SPI1_SOMI | P + 19 | ns | ||
29 | tena(SCSL_ENA)S | Delay from master deasserting SPI1_SCS to slave driving SPI1_ENA valid | 19 | ns | ||
30 | tdis(SPC_ENA)S | Delay from final clock receive edge on SPI1_CLK to slave 3-stating or driving high SPI1_ENA.(3) | Polarity = 0, Phase = 0,
from SPI1_CLK falling |
2.5 P + 19 | ns | |
Polarity = 0, Phase = 1,
from SPI1_CLK rising |
2.5 P + 19 | |||||
Polarity = 1, Phase = 0,
from SPI1_CLK rising |
2.5 P + 19 | |||||
Polarity = 1, Phase = 1,
from SPI1_CLK falling |
2.5 P + 19 |