SPRS377F September 2008 – June 2014 TMS320C6745 , TMS320C6747
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
BYTE ADDRESS | ACRONYM | REGISTER DESCRIPTION |
---|---|---|
0x01E2 3000 | TXREV | Transmit Revision Register |
0x01E2 3004 | TXCONTROL | Transmit Control Register |
0x01E2 3008 | TXTEARDOWN | Transmit Teardown Register |
0x01E2 3010 | RXREV | Receive Revision Register |
0x01E2 3014 | RXCONTROL | Receive Control Register |
0x01E2 3018 | RXTEARDOWN | Receive Teardown Register |
0x01E2 3080 | TXINTSTATRAW | Transmit Interrupt Status (Unmasked) Register |
0x01E2 3084 | TXINTSTATMASKED | Transmit Interrupt Status (Masked) Register |
0x01E2 3088 | TXINTMASKSET | Transmit Interrupt Mask Set Register |
0x01E2 308C | TXINTMASKCLEAR | Transmit Interrupt Clear Register |
0x01E2 3090 | MACINVECTOR | MAC Input Vector Register |
0x01E2 3094 | MACEOIVECTOR | MAC End Of Interrupt Vector Register |
0x01E2 30A0 | RXINTSTATRAW | Receive Interrupt Status (Unmasked) Register |
0x01E2 30A4 | RXINTSTATMASKED | Receive Interrupt Status (Masked) Register |
0x01E2 30A8 | RXINTMASKSET | Receive Interrupt Mask Set Register |
0x01E2 30AC | RXINTMASKCLEAR | Receive Interrupt Mask Clear Register |
0x01E2 30B0 | MACINTSTATRAW | MAC Interrupt Status (Unmasked) Register |
0x01E2 30B4 | MACINTSTATMASKED | MAC Interrupt Status (Masked) Register |
0x01E2 30B8 | MACINTMASKSET | MAC Interrupt Mask Set Register |
0x01E2 30BC | MACINTMASKCLEAR | MAC Interrupt Mask Clear Register |
0x01E2 3100 | RXMBPENABLE | Receive Multicast/Broadcast/Promiscuous Channel Enable Register |
0x01E2 3104 | RXUNICASTSET | Receive Unicast Enable Set Register |
0x01E2 3108 | RXUNICASTCLEAR | Receive Unicast Clear Register |
0x01E2 310C | RXMAXLEN | Receive Maximum Length Register |
0x01E2 3110 | RXBUFFEROFFSET | Receive Buffer Offset Register |
0x01E2 3114 | RXFILTERLOWTHRESH | Receive Filter Low Priority Frame Threshold Register |
0x01E2 3120 | RX0FLOWTHRESH | Receive Channel 0 Flow Control Threshold Register |
0x01E2 3124 | RX1FLOWTHRESH | Receive Channel 1 Flow Control Threshold Register |
0x01E2 3128 | RX2FLOWTHRESH | Receive Channel 2 Flow Control Threshold Register |
0x01E2 312C | RX3FLOWTHRESH | Receive Channel 3 Flow Control Threshold Register |
0x01E2 3130 | RX4FLOWTHRESH | Receive Channel 4 Flow Control Threshold Register |
0x01E2 3134 | RX5FLOWTHRESH | Receive Channel 5 Flow Control Threshold Register |
0x01E2 3138 | RX6FLOWTHRESH | Receive Channel 6 Flow Control Threshold Register |
0x01E2 313C | RX7FLOWTHRESH | Receive Channel 7 Flow Control Threshold Register |
0x01E2 3140 | RX0FREEBUFFER | Receive Channel 0 Free Buffer Count Register |
0x01E2 3144 | RX1FREEBUFFER | Receive Channel 1 Free Buffer Count Register |
0x01E2 3148 | RX2FREEBUFFER | Receive Channel 2 Free Buffer Count Register |
0x01E2 314C | RX3FREEBUFFER | Receive Channel 3 Free Buffer Count Register |
0x01E2 3150 | RX4FREEBUFFER | Receive Channel 4 Free Buffer Count Register |
0x01E2 3154 | RX5FREEBUFFER | Receive Channel 5 Free Buffer Count Register |
0x01E2 3158 | RX6FREEBUFFER | Receive Channel 6 Free Buffer Count Register |
0x01E2 315C | RX7FREEBUFFER | Receive Channel 7 Free Buffer Count Register |
0x01E2 3160 | MACCONTROL | MAC Control Register |
0x01E2 3164 | MACSTATUS | MAC Status Register |
0x01E2 3168 | EMCONTROL | Emulation Control Register |
0x01E2 316C | FIFOCONTROL | FIFO Control Register |
0x01E2 3170 | MACCONFIG | MAC Configuration Register |
0x01E2 3174 | SOFTRESET | Soft Reset Register |
0x01E2 31D0 | MACSRCADDRLO | MAC Source Address Low Bytes Register |
0x01E2 31D4 | MACSRCADDRHI | MAC Source Address High Bytes Register |
0x01E2 31D8 | MACHASH1 | MAC Hash Address Register 1 |
0x01E2 31DC | MACHASH2 | MAC Hash Address Register 2 |
0x01E2 31E0 | BOFFTEST | Back Off Test Register |
0x01E2 31E4 | TPACETEST | Transmit Pacing Algorithm Test Register |
0x01E2 31E8 | RXPAUSE | Receive Pause Timer Register |
0x01E2 31EC | TXPAUSE | Transmit Pause Timer Register |
0x01E2 3200 - 0x01E2 32FC | (see Table 6-35) | EMAC Statistics Registers |
0x01E2 3500 | MACADDRLO | MAC Address Low Bytes Register, Used in Receive Address Matching |
0x01E2 3504 | MACADDRHI | MAC Address High Bytes Register, Used in Receive Address Matching |
0x01E2 3508 | MACINDEX | MAC Index Register |
0x01E2 3600 | TX0HDP | Transmit Channel 0 DMA Head Descriptor Pointer Register |
0x01E2 3604 | TX1HDP | Transmit Channel 1 DMA Head Descriptor Pointer Register |
0x01E2 3608 | TX2HDP | Transmit Channel 2 DMA Head Descriptor Pointer Register |
0x01E2 360C | TX3HDP | Transmit Channel 3 DMA Head Descriptor Pointer Register |
0x01E2 3610 | TX4HDP | Transmit Channel 4 DMA Head Descriptor Pointer Register |
0x01E2 3614 | TX5HDP | Transmit Channel 5 DMA Head Descriptor Pointer Register |
0x01E2 3618 | TX6HDP | Transmit Channel 6 DMA Head Descriptor Pointer Register |
0x01E2 361C | TX7HDP | Transmit Channel 7 DMA Head Descriptor Pointer Register |
0x01E2 3620 | RX0HDP | Receive Channel 0 DMA Head Descriptor Pointer Register |
0x01E2 3624 | RX1HDP | Receive Channel 1 DMA Head Descriptor Pointer Register |
0x01E2 3628 | RX2HDP | Receive Channel 2 DMA Head Descriptor Pointer Register |
0x01E2 362C | RX3HDP | Receive Channel 3 DMA Head Descriptor Pointer Register |
0x01E2 3630 | RX4HDP | Receive Channel 4 DMA Head Descriptor Pointer Register |
0x01E2 3634 | RX5HDP | Receive Channel 5 DMA Head Descriptor Pointer Register |
0x01E2 3638 | RX6HDP | Receive Channel 6 DMA Head Descriptor Pointer Register |
0x01E2 363C | RX7HDP | Receive Channel 7 DMA Head Descriptor Pointer Register |
0x01E2 3640 | TX0CP | Transmit Channel 0 Completion Pointer Register |
0x01E2 3644 | TX1CP | Transmit Channel 1 Completion Pointer Register |
0x01E2 3648 | TX2CP | Transmit Channel 2 Completion Pointer Register |
0x01E2 364C | TX3CP | Transmit Channel 3 Completion Pointer Register |
0x01E2 3650 | TX4CP | Transmit Channel 4 Completion Pointer Register |
0x01E2 3654 | TX5CP | Transmit Channel 5 Completion Pointer Register |
0x01E2 3658 | TX6CP | Transmit Channel 6 Completion Pointer Register |
0x01E2 365C | TX7CP | Transmit Channel 7 Completion Pointer Register |
0x01E2 3660 | RX0CP | Receive Channel 0 Completion Pointer Register |
0x01E2 3664 | RX1CP | Receive Channel 1 Completion Pointer Register |
0x01E2 3668 | RX2CP | Receive Channel 2 Completion Pointer Register |
0x01E2 366C | RX3CP | Receive Channel 3 Completion Pointer Register |
0x01E2 3670 | RX4CP | Receive Channel 4 Completion Pointer Register |
0x01E2 3674 | RX5CP | Receive Channel 5 Completion Pointer Register |
0x01E2 3678 | RX6CP | Receive Channel 6 Completion Pointer Register |
0x01E2 367C | RX7CP | Receive Channel 7 Completion Pointer Register |
BYTE ADDRESS | ACRONYM | REGISTER DESCRIPTION |
---|---|---|
0x01E2 3200 | RXGOODFRAMES | Good Receive Frames Register |
0x01E2 3204 | RXBCASTFRAMES | Broadcast Receive Frames Register
(Total number of good broadcast frames received) |
0x01E2 3208 | RXMCASTFRAMES | Multicast Receive Frames Register
(Total number of good multicast frames received) |
0x01E2 320C | RXPAUSEFRAMES | Pause Receive Frames Register |
0x01E2 3210 | RXCRCERRORS | Receive CRC Errors Register
(Total number of frames received with CRC errors) |
0x01E2 3214 | RXALIGNCODEERRORS | Receive Alignment/Code Errors Register
(Total number of frames received with alignment/code errors) |
0x01E2 3218 | RXOVERSIZED | Receive Oversized Frames Register
(Total number of oversized frames received) |
0x01E2 321C | RXJABBER | Receive Jabber Frames Register
(Total number of jabber frames received) |
0x01E2 3220 | RXUNDERSIZED | Receive Undersized Frames Register
(Total number of undersized frames received) |
0x01E2 3224 | RXFRAGMENTS | Receive Frame Fragments Register |
0x01E2 3228 | RXFILTERED | Filtered Receive Frames Register |
0x01E2 322C | RXQOSFILTERED | Received QOS Filtered Frames Register |
0x01E2 3230 | RXOCTETS | Receive Octet Frames Register
(Total number of received bytes in good frames) |
0x01E2 3234 | TXGOODFRAMES | Good Transmit Frames Register
(Total number of good frames transmitted) |
0x01E2 3238 | TXBCASTFRAMES | Broadcast Transmit Frames Register |
0x01E2 323C | TXMCASTFRAMES | Multicast Transmit Frames Register |
0x01E2 3240 | TXPAUSEFRAMES | Pause Transmit Frames Register |
0x01E2 3244 | TXDEFERRED | Deferred Transmit Frames Register |
0x01E2 3248 | TXCOLLISION | Transmit Collision Frames Register |
0x01E2 324C | TXSINGLECOLL | Transmit Single Collision Frames Register |
0x01E2 3250 | TXMULTICOLL | Transmit Multiple Collision Frames Register |
0x01E2 3254 | TXEXCESSIVECOLL | Transmit Excessive Collision Frames Register |
0x01E2 3258 | TXLATECOLL | Transmit Late Collision Frames Register |
0x01E2 325C | TXUNDERRUN | Transmit Underrun Error Register |
0x01E2 3260 | TXCARRIERSENSE | Transmit Carrier Sense Errors Register |
0x01E2 3264 | TXOCTETS | Transmit Octet Frames Register |
0x01E2 3268 | FRAME64 | Transmit and Receive 64 Octet Frames Register |
0x01E2 326C | FRAME65T127 | Transmit and Receive 65 to 127 Octet Frames Register |
0x01E2 3270 | FRAME128T255 | Transmit and Receive 128 to 255 Octet Frames Register |
0x01E2 3274 | FRAME256T511 | Transmit and Receive 256 to 511 Octet Frames Register |
0x01E2 3278 | FRAME512T1023 | Transmit and Receive 512 to 1023 Octet Frames Register |
0x01E2 327C | FRAME1024TUP | Transmit and Receive 1024 to 1518 Octet Frames Register |
0x01E2 3280 | NETOCTETS | Network Octet Frames Register |
0x01E2 3284 | RXSOFOVERRUNS | Receive FIFO or DMA Start of Frame Overruns Register |
0x01E2 3288 | RXMOFOVERRUNS | Receive FIFO or DMA Middle of Frame Overruns Register |
0x01E2 328C | RXDMAOVERRUNS | Receive DMA Start of Frame and Middle of Frame Overruns Register |
BYTE ADDRESS | ACRONYM | REGISTER DESCRIPTION |
---|---|---|
0x01E2 2000 | REV | EMAC Control Module Revision Register |
0x01E2 2004 | SOFTRESET | EMAC Control Module Software Reset Register |
0x01E2 200C | INTCONTROL | EMAC Control Module Interrupt Control Register |
0x01E2 2010 | C0RXTHRESHEN | EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register |
0x01E2 2014 | C0RXEN | EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register |
0x01E2 2018 | C0TXEN | EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register |
0x01E2 201C | C0MISCEN | EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register |
0x01E2 2020 | C1RXTHRESHEN | EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register |
0x01E2 2024 | C1RXEN | EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register |
0x01E2 2028 | C1TXEN | EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register |
0x01E2 202C | C1MISCEN | EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register |
0x01E2 2030 | C2RXTHRESHEN | EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register |
0x01E2 2034 | C2RXEN | EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register |
0x01E2 2038 | C2TXEN | EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register |
0x01E2 203C | C2MISCEN | EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register |
0x01E2 2040 | C0RXTHRESHSTAT | EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register |
0x01E2 2044 | C0RXSTAT | EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register |
0x01E2 2048 | C0TXSTAT | EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register |
0x01E2 204C | C0MISCSTAT | EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register |
0x01E2 2050 | C1RXTHRESHSTAT | EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register |
0x01E2 2054 | C1RXSTAT | EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register |
0x01E2 2058 | C1TXSTAT | EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register |
0x01E2 205C | C1MISCSTAT | EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register |
0x01E2 2060 | C2RXTHRESHSTAT | EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register |
0x01E2 2064 | C2RXSTAT | EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register |
0x01E2 2068 | C2TXSTAT | EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register |
0x01E2 206C | C2MISCSTAT | EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register |
0x01E2 2070 | C0RXIMAX | EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register |
0x01E2 2074 | C0TXIMAX | EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register |
0x01E2 2078 | C1RXIMAX | EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register |
0x01E2 207C | C1TXIMAX | EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register |
0x01E2 2080 | C2RXIMAX | EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register |
0x01E2 2084 | C2TXIMAX | EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register |
BYTE ADRESS | REGISTER DESCRIPTION |
---|---|
0x01E2 0000 - 0x01E2 1FFF | EMAC Local Buffer Descriptor Memory |
No. | PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
1 | tc(REFCLK) | Cycle Time, RMII_MHZ_50_CLK | 20 | ns | ||
2 | tw(REFCLKH) | Pulse Width, RMII_MHZ_50_CLK High | 7 | 13 | ns | |
3 | tw(REFCLKL) | Pulse Width, RMII_MHZ_50_CLK Low | 7 | 13 | ns | |
6 | tsu(RXD-REFCLK) | Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High | 4 | ns | ||
7 | th(REFCLK-RXD) | Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High | 2 | ns | ||
8 | tsu(CRSDV-REFCLK) | Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High | 4 | ns | ||
9 | th(REFCLK-CRSDV) | Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High | 2 | ns | ||
10 | tsu(RXER-REFCLK) | Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High | 4 | ns | ||
11 | th(REFCLKR-RXER) | Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High | 2 | ns |
Note: Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter tolerance of 50 ppm or less.
No. | PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
4 | td(REFCLK-TXD) | Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid | 2.5 | 13 | ns | |
5 | td(REFCLK-TXEN) | Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid | 2.5 | 13 | ns |