SPRS377F September 2008 – June 2014 TMS320C6745 , TMS320C6747
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
No. | PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
9 | tc(SPC)S | Cycle Time, SPI0_CLK, All Slave Modes | greater of 3P or 40 | ns | ||
10 | tw(SPCH)S | Pulse Width High, SPI0_CLK, All Slave Modes | 18 | ns | ||
11 | tw(SPCL)S | Pulse Width Low, SPI0_CLK, All Slave Modes | 18 | ns | ||
12 | tsu(SOMI_SPC)S | Setup time, transmit data written to SPI before initial clock edge from
master.(2)(3) |
Polarity = 0, Phase = 0,
to SPI0_CLK rising |
2P | ns | |
Polarity = 0, Phase = 1,
to SPI0_CLK rising |
2P | |||||
Polarity = 1, Phase = 0,
to SPI0_CLK falling |
2P | |||||
Polarity = 1, Phase = 1,
to SPI0_CLK falling |
2P | |||||
13 | td(SPC_SOMI)S | Delay, subsequent bits valid on SPI0_SOMI after transmit edge of SPI0_CLK | Polarity = 0, Phase = 0,
from SPI0_CLK rising |
18.5 | ns | |
Polarity = 0, Phase = 1,
from SPI0_CLK falling |
18.5 | |||||
Polarity = 1, Phase = 0,
from SPI0_CLK falling |
18.5 | |||||
Polarity = 1, Phase = 1,
from SPI0_CLK rising |
18.5 | |||||
14 | toh(SPC_SOMI)S | Output hold time, SPI0_SOMI valid after
receive edge of SPI0_CLK |
Polarity = 0, Phase = 0,
from SPI0_CLK falling |
0.5tc(SPC)S -3 | ns | |
Polarity = 0, Phase = 1,
from SPI0_CLK rising |
0.5tc(SPC)S -3 | |||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
0.5tc(SPC)S -3 | |||||
Polarity = 1, Phase = 1,
from SPI0_CLK falling |
0.5tc(SPC)S -3 | |||||
15 | tsu(SIMO_SPC)S | Input Setup Time, SPI0_SIMO valid before
receive edge of SPI0_CLK |
Polarity = 0, Phase = 0,
to SPI0_CLK falling |
0 | ns | |
Polarity = 0, Phase = 1,
to SPI0_CLK rising |
0 | |||||
Polarity = 1, Phase = 0,
to SPI0_CLK rising |
0 | |||||
Polarity = 1, Phase = 1,
to SPI0_CLK falling |
0 | |||||
16 | tih(SPC_SIMO)S | Input Hold Time, SPI0_SIMO valid after
receive edge of SPI0_CLK |
Polarity = 0, Phase = 0,
from SPI0_CLK falling |
5 | ns | |
Polarity = 0, Phase = 1,
from SPI0_CLK rising |
5 | |||||
Polarity = 1, Phase = 0,
from SPI0_CLK rising |
5 | |||||
Polarity = 1, Phase = 1,
from SPI0_CLK falling |
5 |