SPRS377F September 2008 – June 2014 TMS320C6745 , TMS320C6747
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
The C6745/6747 USB2.0 peripheral supports the following features:
Important Notice: On the original device pinout (marked "A" in the lower right corner of the package), pins USB0_VSSA33 (ZKB package pin H4; PTP package pin 139) and USB0_VSSA (ZKB package pin F3; PTP package pin 136) were connected to ground outside the package. For more robust ESD performance, the USB0 ground references are now connected inside the package on packages marked "B" and the package pins are unconnected. This change will require that any external filter circuits previously referenced to ground at these pins will need to reference the board ground instead.
Important Notice: The USB0 controller module clock (PLL0_SYSCLK2) must be greater than 30 MHz for proper operation of the USB controller. A clock rate of 60 MHz or greater is recommended to avoid data throughput reduction.
Table 6-96 is the list of USB OTG registers.
BYTE ADDRESS | ACRONYM | REGISTER DESCRIPTION |
---|---|---|
0x01E0 0000 | REVID | Revision Register |
0x01E0 0004 | CTRLR | Control Register |
0x01E0 0008 | STATR | Status Register |
0x01E0 000C | EMUR | Emulation Register |
0x01E0 0010 | MODE | Mode Register |
0x01E0 0014 | AUTOREQ | Autorequest Register |
0x01E0 0018 | SRPFIXTIME | SRP Fix Time Register |
0x01E0 001C | TEARDOWN | Teardown Register |
0x01E0 0020 | INTSRCR | USB Interrupt Source Register |
0x01E0 0024 | INTSETR | USB Interrupt Source Set Register |
0x01E0 0028 | INTCLRR | USB Interrupt Source Clear Register |
0x01E0 002C | INTMSKR | USB Interrupt Mask Register |
0x01E0 0030 | INTMSKSETR | USB Interrupt Mask Set Register |
0x01E0 0034 | INTMSKCLRR | USB Interrupt Mask Clear Register |
0x01E0 0038 | INTMASKEDR | USB Interrupt Source Masked Register |
0x01E0 003C | EOIR | USB End of Interrupt Register |
0x01E0 0040 | - | Reserved |
0x01E0 0050 | GENRNDISSZ1 | Generic RNDIS Size EP1 |
0x01E0 0054 | GENRNDISSZ2 | Generic RNDIS Size EP2 |
0x01E0 0058 | GENRNDISSZ3 | Generic RNDIS Size EP3 |
0x01E0 005C | GENRNDISSZ4 | Generic RNDIS Size EP4 |
0x01E0 0400 | FADDR | Function Address Register |
0x01E0 0401 | POWER | Power Management Register |
0x01E0 0402 | INTRTX | Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4 |
0x01E0 0404 | INTRRX | Interrupt Register for Receive Endpoints 1 to 4 |
0x01E0 0406 | INTRTXE | Interrupt Enable Register for INTRTX |
0x01E0 0408 | INTRRXE | Interrupt Enable Register for INTRRX |
0x01E0 040A | INTRUSB | Interrupt Register for Common USB Interrupts |
0x01E0 040B | INTRUSBE | Interrupt Enable Register for INTRUSB |
0x01E0 040C | FRAME | Frame Number Register |
0x01E0 040E | INDEX | Index Register for Selecting the Endpoint Status and Control Registers |
0x01E0 040F | TESTMODE | Register to Enable the USB 2.0 Test Modes |
INDEXED REGISTERS
These registers operate on the endpoint selected by the INDEX register |
||
0x01E0 0410 | TXMAXP | Maximum Packet Size for Peripheral/Host Transmit Endpoint
(Index register set to select Endpoints 1-4 only) |
0x01E0 0412 | PERI_CSR0 | Control Status Register for Endpoint 0 in Peripheral Mode.
(Index register set to select Endpoint 0) |
HOST_CSR0 | Control Status Register for Endpoint 0 in Host Mode.
(Index register set to select Endpoint 0) |
|
PERI_TXCSR | Control Status Register for Peripheral Transmit Endpoint.
(Index register set to select Endpoints 1-4) |
|
HOST_TXCSR | Control Status Register for Host Transmit Endpoint.
(Index register set to select Endpoints 1-4) |
|
0x01E0 0414 | RXMAXP | Maximum Packet Size for Peripheral/Host Receive Endpoint
(Index register set to select Endpoints 1-4 only) |
0x01E0 0416 | PERI_RXCSR | Control Status Register for Peripheral Receive Endpoint.
(Index register set to select Endpoints 1-4) |
HOST_RXCSR | Control Status Register for Host Receive Endpoint.
(Index register set to select Endpoints 1-4) |
|
0x01E0 0418 | COUNT0 | Number of Received Bytes in Endpoint 0 FIFO.
(Index register set to select Endpoint 0) |
RXCOUNT | Number of Bytes in Host Receive Endpoint FIFO.
(Index register set to select Endpoints 1- 4) |
|
0x01E0 041A | HOST_TYPE0 | Defines the speed of Endpoint 0 |
HOST_TXTYPE | Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint.
(Index register set to select Endpoints 1-4 only) |
|
0x01E0 041B | HOST_NAKLIMIT0 | Sets the NAK response timeout on Endpoint 0.
(Index register set to select Endpoint 0) |
HOST_TXINTERVAL | Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint.
(Index register set to select Endpoints 1-4 only) |
|
0x01E0 041C | HOST_RXTYPE | Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint.
(Index register set to select Endpoints 1-4 only) |
0x01E0 041D | HOST_RXINTERVAL | Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint.
(Index register set to select Endpoints 1-4 only) |
0x01E0 041F | CONFIGDATA | Returns details of core configuration.
(Index register set to select Endpoint 0) |
FIFO | ||
0x01E0 0420 | FIFO0 | Transmit and Receive FIFO Register for Endpoint 0 |
0x01E0 0424 | FIFO1 | Transmit and Receive FIFO Register for Endpoint 1 |
0x01E0 0428 | FIFO2 | Transmit and Receive FIFO Register for Endpoint 2 |
0x01E0 042C | FIFO3 | Transmit and Receive FIFO Register for Endpoint 3 |
0x01E0 0430 | FIFO4 | Transmit and Receive FIFO Register for Endpoint 4 |
OTG DEVICE CONTROL | ||
0x01E0 0460 | DEVCTL | Device Control Register |
DYNAMIC FIFO CONTROL | ||
0x01E0 0462 | TXFIFOSZ | Transmit Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only) |
0x01E0 0463 | RXFIFOSZ | Receive Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only) |
0x01E0 0464 | TXFIFOADDR | Transmit Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only) |
0x01E0 0466 | RXFIFOADDR | Receive Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only) |
0x01E0 046C | HWVERS | Hardware Version Register |
TARGET ENDPOINT 0 CONTROL REGISTERS, VALID ONLY IN HOST MODE | ||
0x01E0 0480 | TXFUNCADDR | Address of the target function that has to be accessed through the associated Transmit Endpoint. |
0x01E0 0482 | TXHUBADDR | Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 0483 | TXHUBPORT | Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 0484 | RXFUNCADDR | Address of the target function that has to be accessed through the associated Receive Endpoint. |
0x01E0 0486 | RXHUBADDR | Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 0487 | RXHUBPORT | Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
TARGET ENDPOINT 1 CONTROL REGISTERS, VALID ONLY IN HOST MODE | ||
0x01E0 0488 | TXFUNCADDR | Address of the target function that has to be accessed through the associated Transmit Endpoint. |
0x01E0 048A | TXHUBADDR | Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 048B | TXHUBPORT | Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 048C | RXFUNCADDR | Address of the target function that has to be accessed through the associated Receive Endpoint. |
0x01E0 048E | RXHUBADDR | Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 048F | RXHUBPORT | Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
TARGET ENDPOINT 2 CONTROL REGISTERS, VALID ONLY IN HOST MODE | ||
0x01E0 0490 | TXFUNCADDR | Address of the target function that has to be accessed through the associated Transmit Endpoint. |
0x01E0 0492 | TXHUBADDR | Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 0493 | TXHUBPORT | Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 0494 | RXFUNCADDR | Address of the target function that has to be accessed through the associated Receive Endpoint. |
0x01E0 0496 | RXHUBADDR | Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 0497 | RXHUBPORT | Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
TARGET ENDPOINT 3 CONTROL REGISTERS, VALID ONLY IN HOST MODE | ||
0x01E0 0498 | TXFUNCADDR | Address of the target function that has to be accessed through the associated Transmit Endpoint. |
0x01E0 049A | TXHUBADDR | Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 049B | TXHUBPORT | Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 049C | RXFUNCADDR | Address of the target function that has to be accessed through the associated Receive Endpoint. |
0x01E0 049E | RXHUBADDR | Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 049F | RXHUBPORT | Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
TARGET ENDPOINT 4 CONTROL REGISTERS, VALID ONLY IN HOST MODE | ||
0x01E0 04A0 | TXFUNCADDR | Address of the target function that has to be accessed through the associated Transmit Endpoint. |
0x01E0 04A2 | TXHUBADDR | Address of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 04A3 | TXHUBPORT | Port of the hub that has to be accessed through the associated Transmit Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 04A4 | RXFUNCADDR | Address of the target function that has to be accessed through the associated Receive Endpoint. |
0x01E0 04A6 | RXHUBADDR | Address of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
0x01E0 04A7 | RXHUBPORT | Port of the hub that has to be accessed through the associated Receive Endpoint. This is used only when full speed or low speed device is connected via a USB2.0 high-speed hub. |
CONTROL AND STATUS REGISTER FOR ENDPOINT 0 | ||
0x01E0 0502 | PERI_CSR0 | Control Status Register for Endpoint 0 in Peripheral Mode |
HOST_CSR0 | Control Status Register for Endpoint 0 in Host Mode | |
0x01E0 0508 | COUNT0 | Number of Received Bytes in Endpoint 0 FIFO |
0x01E0 050A | HOST_TYPE0 | Defines the Speed of Endpoint 0 |
0x01E0 050B | HOST_NAKLIMIT0 | Sets the NAK Response Timeout on Endpoint 0 |
0x01E0 050F | CONFIGDATA | Returns details of core configuration. |
CONTROL AND STATUS REGISTER FOR ENDPOINT 1 | ||
0x01E0 0510 | TXMAXP | Maximum Packet Size for Peripheral/Host Transmit Endpoint |
0x01E0 0512 | PERI_TXCSR | Control Status Register for Peripheral Transmit Endpoint
(peripheral mode) |
HOST_TXCSR | Control Status Register for Host Transmit Endpoint
(host mode) |
|
0x01E0 0514 | RXMAXP | Maximum Packet Size for Peripheral/Host Receive Endpoint |
0x01E0 0516 | PERI_RXCSR | Control Status Register for Peripheral Receive Endpoint
(peripheral mode) |
HOST_RXCSR | Control Status Register for Host Receive Endpoint
(host mode) |
|
0x01E0 0518 | RXCOUNT | Number of Bytes in Host Receive endpoint FIFO |
0x01E0 051A | HOST_TXTYPE | Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. |
0x01E0 051B | HOST_TXINTERVAL | Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. |
0x01E0 051C | HOST_RXTYPE | Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. |
0x01E0 051D | HOST_RXINTERVAL | Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. |
CONTROL AND STATUS REGISTER FOR ENDPOINT 2 | ||
0x01E0 0520 | TXMAXP | Maximum Packet Size for Peripheral/Host Transmit Endpoint |
0x01E0 0522 | PERI_TXCSR | Control Status Register for Peripheral Transmit Endpoint
(peripheral mode) |
HOST_TXCSR | Control Status Register for Host Transmit Endpoint
(host mode) |
|
0x01E0 0524 | RXMAXP | Maximum Packet Size for Peripheral/Host Receive Endpoint |
0x01E0 0526 | PERI_RXCSR | Control Status Register for Peripheral Receive Endpoint
(peripheral mode) |
HOST_RXCSR | Control Status Register for Host Receive Endpoint
(host mode) |
|
0x01E0 0528 | RXCOUNT | Number of Bytes in Host Receive endpoint FIFO |
0x01E0 052A | HOST_TXTYPE | Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. |
0x01E0 052B | HOST_TXINTERVAL | Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. |
0x01E0 052C | HOST_RXTYPE | Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. |
0x01E0 052D | HOST_RXINTERVAL | Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. |
CONTROL AND STATUS REGISTER FOR ENDPOINT 3 | ||
0x01E0 0530 | TXMAXP | Maximum Packet Size for Peripheral/Host Transmit Endpoint |
0x01E0 0532 | PERI_TXCSR | Control Status Register for Peripheral Transmit Endpoint
(peripheral mode) |
HOST_TXCSR | Control Status Register for Host Transmit Endpoint
(host mode) |
|
0x01E0 0534 | RXMAXP | Maximum Packet Size for Peripheral/Host Receive Endpoint |
0x01E0 0536 | PERI_RXCSR | Control Status Register for Peripheral Receive Endpoint
(peripheral mode) |
HOST_RXCSR | Control Status Register for Host Receive Endpoint
(host mode) |
|
0x01E0 0538 | RXCOUNT | Number of Bytes in Host Receive endpoint FIFO |
0x01E0 053A | HOST_TXTYPE | Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. |
0x01E0 053B | HOST_TXINTERVAL | Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. |
0x01E0 053C | HOST_RXTYPE | Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. |
0x01E0 053D | HOST_RXINTERVAL | Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. |
CONTROL AND STATUS REGISTER FOR ENDPOINT 4 | ||
0x01E0 0540 | TXMAXP | Maximum Packet Size for Peripheral/Host Transmit Endpoint |
0x01E0 0542 | PERI_TXCSR | Control Status Register for Peripheral Transmit Endpoint
(peripheral mode) |
HOST_TXCSR | Control Status Register for Host Transmit Endpoint
(host mode) |
|
0x01E0 0544 | RXMAXP | Maximum Packet Size for Peripheral/Host Receive Endpoint |
0x01E0 0546 | PERI_RXCSR | Control Status Register for Peripheral Receive Endpoint (peripheral mode) |
HOST_RXCSR | Control Status Register for Host Receive Endpoint
(host mode) |
|
0x01E0 0548 | RXCOUNT | Number of Bytes in Host Receive endpoint FIFO |
0x01E0 054A | HOST_TXTYPE | Sets the operating speed, transaction protocol and peripheral endpoint number for the host Transmit endpoint. |
0x01E0 054B | HOST_TXINTERVAL | Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Transmit endpoint. |
0x01E0 054C | HOST_RXTYPE | Sets the operating speed, transaction protocol and peripheral endpoint number for the host Receive endpoint. |
0x01E0 054D | HOST_RXINTERVAL | Sets the polling interval for Interrupt/ISOC transactions or the NAK response timeout on Bulk transactions for host Receive endpoint. |
DMA REGISTERS | ||
0x01E0 1000 | DMAREVID | DMA Revision Register |
0x01E0 1004 | TDFDQ | DMA Teardown Free Descriptor Queue Control Register |
0x01E0 1008 | DMAEMU | DMA Emulation Control Register |
0x01E0 1800 | TXGCR[0] | Transmit Channel 0 Global Configuration Register |
0x01E0 1808 | RXGCR[0] | Receive Channel 0 Global Configuration Register |
0x01E0 180C | RXHPCRA[0] | Receive Channel 0 Host Packet Configuration Register A |
0x01E0 1810 | RXHPCRB[0] | Receive Channel 0 Host Packet Configuration Register B |
0x01E0 1820 | TXGCR[1] | Transmit Channel 1 Global Configuration Register |
0x01E0 1828 | RXGCR[1] | Receive Channel 1 Global Configuration Register |
0x01E0 182C | RXHPCRA[1] | Receive Channel 1 Host Packet Configuration Register A |
0x01E0 1830 | RXHPCRB[1] | Receive Channel 1 Host Packet Configuration Register B |
0x01E0 1840 | TXGCR[2] | Transmit Channel 2 Global Configuration Register |
0x01E0 1848 | RXGCR[2] | Receive Channel 2 Global Configuration Register |
0x01E0 184C | RXHPCRA[2] | Receive Channel 2 Host Packet Configuration Register A |
0x01E0 1850 | RXHPCRB[2] | Receive Channel 2 Host Packet Configuration Register B |
0x01E0 1860 | TXGCR[3] | Transmit Channel 3 Global Configuration Register |
0x01E0 1868 | RXGCR[3] | Receive Channel 3 Global Configuration Register |
0x01E0 186C | RXHPCRA[3] | Receive Channel 3 Host Packet Configuration Register A |
0x01E0 1870 | RXHPCRB[3] | Receive Channel 3 Host Packet Configuration Register B |
0x01E0 2000 | DMA_SCHED_CTRL | DMA Scheduler Control Register |
0x01E0 2800 | WORD[0] | DMA Scheduler Table Word 0 |
0x01E0 2804 | WORD[1] | DMA Scheduler Table Word 1 |
. . . | . . . | . . . |
0x01E0 28FC | WORD[63] | DMA Scheduler Table Word 63 |
QUEUE MANAGER REGISTERS | ||
0x01E0 4000 | QMGRREVID | Queue Manager Revision Register |
0x01E0 4008 | DIVERSION | Queue Diversion Register |
0x01E0 4020 | FDBSC0 | Free Descriptor/Buffer Starvation Count Register 0 |
0x01E0 4024 | FDBSC1 | Free Descriptor/Buffer Starvation Count Register 1 |
0x01E0 4028 | FDBSC2 | Free Descriptor/Buffer Starvation Count Register 2 |
0x01E0 402C | FDBSC3 | Free Descriptor/Buffer Starvation Count Register 3 |
0x01E0 4080 | LRAM0BASE | Linking RAM Region 0 Base Address Register |
0x01E0 4084 | LRAM0SIZE | Linking RAM Region 0 Size Register |
0x01E0 4088 | LRAM1BASE | Linking RAM Region 1 Base Address Register |
0x01E0 4090 | PEND0 | Queue Pending Register 0 |
0x01E0 4094 | PEND1 | Queue Pending Register 1 |
0x01E0 5000 | QMEMRBASE[0] | Memory Region 0 Base Address Register |
0x01E0 5004 | QMEMRCTRL[0] | Memory Region 0 Control Register |
0x01E0 5010 | QMEMRBASE[1] | Memory Region 1 Base Address Register |
0x01E0 5014 | QMEMRCTRL[1] | Memory Region 1 Control Register |
. . . | . . . | . . . |
0x01E0 50F0 | QMEMRBASE[15] | Memory Region 15 Base Address Register |
0x01E0 50F4 | QMEMRCTRL[15] | Memory Region 15 Control Register |
0x01E0 600C | CTRLD[0] | Queue Manager Queue 0 Control Register D |
0x01E0 601C | CTRLD[1] | Queue Manager Queue 1 Control Register D |
. . . | . . . | . . . |
0x01E0 63FC | CTRLD[63] | Queue Manager Queue 63 Status Register D |
0x01E0 6800 | QSTATA[0] | Queue Manager Queue 0 Status Register A |
0x01E0 6804 | QSTATB[0] | Queue Manager Queue 0 Status Register B |
0x01E0 6808 | QSTATC[0] | Queue Manager Queue 0 Status Register C |
0x01E0 6810 | QSTATA[1] | Queue Manager Queue 1 Status Register A |
0x01E0 6814 | QSTATB[1] | Queue Manager Queue 1 Status Register B |
0x01E0 6818 | QSTATC[1] | Queue Manager Queue 1 Status Register C |
. . . | . . . | . . . |
0x01E0 6BF0 | QSTATA[63] | Queue Manager Queue 63 Status Register A |
0x01E0 6BF4 | QSTATB[63] | Queue Manager Queue 63 Status Register B |
0x01E0 6BF8 | QSTATC[63] | Queue Manager Queue 63 Status Register C |