SPRS614F March 2011 – March 2015 TMS320DM8165 , TMS320DM8167 , TMS320DM8168
PRODUCTION DATA.
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The L3 interconnect allows the sharing of resources, such as peripherals and external or on-chip memories, between all the initiators of the platform. The L4 interconnects control access to the peripherals.
Transfers between initiators and targets across the platform are physically conditioned by the chip interconnect.
The L3 topology is driven by performance requirements, bus types, and clocking structure. Figure 7-1 shows the interconnect of the device and the main modules and subsystems in the platform. Arrows indicate the master-and-slave relationship, not data flow. Master-and-slave connectivity is shown in Table 7-1.
MASTERS | SLAVES | ||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
SYSTEM MMU | DMM TILER0 | DMM TILER1 | DMM ELLA | GPMC | SGX530 | C674x_SDMA | PCIe GEN2 SLAVE | McASPs | McBSP | HDMI 1.3 TX AUDIO | L4 HS PERIPH PORT 0 | L4 HS PERIPH PORT 1 | L4 STD PERIPH PORT 0 | L4 STD PERIPH PORT 1 | EDMA TPTC0 - 3 CFG | EDMA TPCC | OCMC RAM0 AND RAM1 | USB2.0 CFG | |
ARM Cortex-A8 M1 (128-bit) | X | ||||||||||||||||||
ARM Cortex-A8 M2 (64-bit) | X | X | X | X | X | X | X | X | X | X | X | X | X | X | |||||
C674x MDMA | X | ||||||||||||||||||
System MMU | X | X | X | X | |||||||||||||||
C674x CFG | X | X | |||||||||||||||||
HDVICP2-0 VDMA | X | X | |||||||||||||||||
HDVICP2-1 VDMA | X | X | |||||||||||||||||
HDVICP2-2 VDMA | X | X | |||||||||||||||||
HDVPSS Mstr0 | X | X | |||||||||||||||||
HDVPSS Mstr1 | X | X | |||||||||||||||||
SGX530 BIF | X | ||||||||||||||||||
SATA | X | X | |||||||||||||||||
EMAC0 Rx and Tx | X | X | |||||||||||||||||
EMAC1 Rx and Tx | X | X | |||||||||||||||||
USB2.0 DMA | X | ||||||||||||||||||
USB2.0 Queue Mgr | X | X | |||||||||||||||||
PCIe Gen2 | X | X | X | X | |||||||||||||||
EDMA TPTC0 | S | X | X | X | X | X | X | X | X | X | X | X | |||||||
EDMA TPTC1 | X | X | X | X | X | X | X | X | X | X | X | ||||||||
EDMA TPTC2 | X | X | X | X | X | X | X | X | X | X | X | ||||||||
EDMA TPTC3 | X | X | X | X | X | X | X | X | X | X | X |
The L4 interconnect is a non-blocking peripheral interconnect that provides low-latency access to a large number of low-bandwidth, physically-dispersed target cores. The L4 can handle incoming traffic from up to four initiators and can distribute those communication requests to and collect related responses from up to 63 targets.
The device provides three interfaces with L3 interconnect for high-speed peripheral and standard peripheral.Figure 7-2 and Table 7-2 show the L4 bus architecture and memory-mapped peripherals.
L4 PERIPHERALS | MASTERS | ||||||
---|---|---|---|---|---|---|---|
Cortex-A8 M2 (64-bit) | EDMA TPTC0 | EDMA TPTC1 | EDMA TPTC2 | EDMA TPTC3 | C674x CONFIG | SYSTEM MMU | |
L4 High-Speed Peripherals Port0 and Port1 | |||||||
EMAC0 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
EMAC1 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
SATA | Port0 | Port1 | Port0 | Port1 | Port0 | ||
L4 Standard-Speed Peripherals Port0 and Port1 | |||||||
I2C0 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
I2C1 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
SPI | Port0 | Port1 | Port0 | Port1 | Port0 | ||
UART0 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
UART1 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
Timer1 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
Timer2 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
Timer3 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
Timer4 | Port0 | Port1 | Port0 | Port1 | Port0 | Port0 | |
Timer5 | Port0 | Port1 | Port0 | Port1 | Port0 | Port0 | |
Timer6 | Port0 | Port1 | Port0 | Port1 | Port0 | Port0 | |
Timer7 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
GPIO0 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
GPIO1 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
SD and SDIO | Port0 | Port1 | Port0 | Port1 | Port0 | ||
WDT | Port0 | Port1 | Port0 | Port1 | Port0 | ||
RTC | Port0 | Port1 | Port0 | Port1 | Port0 | ||
System MMU | Port0 | Port1 | Port0 | Port1 | Port0 | ||
SmartReflex0 | Port0 | ||||||
SmartReflex1 | Port0 | ||||||
DDR_CFG0 | Port0 | ||||||
DDR_CFG1 | Port0 | ||||||
Spinlock | Port0 | Port0 | Port0 | ||||
PRCM | Port0 | ||||||
Control and Top Regs | Port0 | ||||||
ELM | Port0 | ||||||
HDMIphy | Port0 | ||||||
OCPWP | Port0 | ||||||
McASP0 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
McASP1 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
McASP2 | Port0 | Port1 | Port0 | Port1 | Port0 | ||
Mailbox | Port0 | Port1 | Port0 | Port1 | Port0 | Port0 | Port0 |