SPRS614F March 2011 – March 2015 TMS320DM8165 , TMS320DM8167 , TMS320DM8168
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. For more information on pin muxing, see Section 6.5, Pin Multiplexing Control.
Figure 4-1 through Figure 4-19 show the bottom view of the package pin assignments in 15 sections (A, B, C, D, E, F, G, H, I, J, K, L, M, N, and O).
NOTE
Pin map sections D, E, K, and L show the different pin names for silicon revision 1.x devices and silicon revision 2.x devices.
The terminal functions tables identify the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown resistors, and a functional pin description. Bolded pin names denote the muxed pin function being described in each table. For more detailed information on device configurations, peripheral selection, multiplexed pin, and shared pin see Section 6, Device Configurations.
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
BOOT | |||||
Boot Mode inputs. Select the peripheral over which the Host ARM Cortex™-A8 will boot. | |||||
GPMC_A[5]/GP0[13]/ BTMODE[4] |
AE2 | I | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, GP0 PINCTRL226 |
Boot Mode Selection pins. For boot mode information, see Table 6-6. |
GPMC_A[4]/GP0[12]/ BTMODE[3] |
AE1 | GPMC, GP0 PINCTRL225 |
|||
GPMC_A[3]/GP0[11]/ BTMODE[2] |
AE3 | GPMC, GP0 PINCTRL224 |
|||
GPMC_A[2]/GP0[10]/ BTMODE[1] |
AE4 | GPMC, GP0 PINCTRL223 |
|||
GPMC_A[1]/GP0[9]/ BTMODE[0] |
AE5 | GPMC, GP0 PINCTRL222 |
|||
DEVICE CONTROL | |||||
GPMC_A[8]/GP0[16]/ CS0BW |
AD4 | I | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, GP0 PINCTRL229 |
GPMC CS0 default Data Bus Width input 0 = 8-bit data bus 1 = 16-bit data bus The CS0BW pin is also used by the ROM bootloader to set up the size of BAR ranges in PCIe boot mode.(4) |
GPMC_A[7]/GP0[15]/ CS0MUX[1] |
AD3 | I | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, GP0 PINCTRL228 |
GPMC CS0 default Address/Data multiplexing mode input 00 = Not multiplexed 01 = A/A/D muxed 10 = A/D muxed 11 = Reserved The CS0MUX[1:0] pins are also used by the ROM bootloader to set up the size of BAR ranges in PCIe boot mode.(4) |
GPMC_A[6]/GP0[14]/ CS0MUX[0] |
AD8 | GPMC, GP0 PINCTRL227 |
|||
GPMC_A[9]/GP0[17]/ CS0WAIT |
AD2 | I | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, GP0 PINCTRL230 |
GPMC CS0 default GPMC_Wait enable input 0 = Wait disabled 1 = Wait enabled The CS0WAIT pin is also used by the ROM bootloader to set up the size of BAR ranges in PCIe boot mode.(4) |
SIGNAL | TYPE(1) | OTHER(2) | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
DDR[0]_CLK[0] | B12 | O | DVDD_DDR[0] | DDR[0] Clock 0 |
DDR[0]_CLK[0] | A12 | O | DVDD_DDR[0] | DDR[0] Negative Clock 0 |
DDR[0]_CLK[1] | A15 | O | DVDD_DDR[0] | DDR[0] Clock 1 |
DDR[0]_CLK[1] | B15 | O | DVDD_DDR[0] | DDR[0] Negative Clock 1 |
DDR[0]_CKE | C18 | O | DVDD_DDR[0] | DDR[0] Clock Enable |
DDR[0]_WE | E13 | O | DVDD_DDR[0] | DDR[0] Write Enable |
DDR[0]_CS[0] | B17 | O | DVDD_DDR[0] | DDR[0] Chip Select 0 |
DDR[0]_CS[1] | F18 | O | DVDD_DDR[0] | DDR[0] Chip Select 1 |
DDR[0]_RAS | D13 | O | DVDD_DDR[0] | DDR[0] Row Address Strobe output |
DDR[0]_CAS | C13 | O | DVDD_DDR[0] | DDR[0] Column Address Strobe output |
DDR[0]_DQM[3] | D9 | O | DVDD_DDR[0] | DDR[0] Data Mask outputs DDR[0]_DQM[3]: For upper byte data bus DDR[0]_D[31:24] DDR[0]_DQM[2]: For DDR[0]_D[23:16] DDR[0]_DQM[1]: For DDR[0]_D[15:8] DDR[0]_DQM[0]: For lower byte data bus DDR[0]_D[7:0] |
DDR[0]_DQM[2] | G9 | O | DVDD_DDR[0] | |
DDR[0]_DQM[1] | B5 | O | DVDD_DDR[0] | |
DDR[0]_DQM[0] | C2 | O | DVDD_DDR[0] | |
DDR[0]_DQS[3] | B9 | IO | DVDD_DDR[0] | Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[0] memory when writing and inputs when reading. They are used to synchronize the data transfers. DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24] DDR[0]_DQS[2]: For DDR[0]_D[23:16] DDR[0]_DQS[1]: For DDR[0]_D[15:8] DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0] |
DDR[0]_DQS[2] | B8 | IO | DVDD_DDR[0] | |
DDR[0]_DQS[1] | B4 | IO | DVDD_DDR[0] | |
DDR[0]_DQS[0] | F4 | IO | DVDD_DDR[0] | |
DDR[0]_DQS[3] | A9 | IO | DVDD_DDR[0] | Complementary data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[0] memory when writing and inputs when reading. They are used to synchronize the data transfers. DDR[0]_DQS[3]: For upper byte data bus DDR[0]_D[31:24] DDR[0]_DQS[2]: For DDR[0]_D[23:16] DDR[0]_DQS[1]: For DDR[0]_D[15:8] DDR[0]_DQS[0]: For lower byte data bus DDR[0]_D[7:0] |
DDR[0]_DQS[2] | A8 | IO | DVDD_DDR[0] | |
DDR[0]_DQS[1] | A4 | IO | DVDD_DDR[0] | |
DDR[0]_DQS[0] | E3 | IO | DVDD_DDR[0] | |
DDR[0]_ODT[0] | E18 | O | DVDD_DDR[0] | DDR[0] On-Die Termination for Chip Select 0. |
DDR[0]_ODT[1] | A16 | O | DVDD_DDR[0] | DDR[0] On-Die Termination for Chip Select 1. |
DDR[0]_RST | D18 | O | DVDD_DDR[0] | DDR[0] Reset output |
DDR[0]_BA[2] | N15 | O | DVDD_DDR[0] | DDR[0] Bank Address outputs |
DDR[0]_BA[1] | B14 | O | DVDD_DDR[0] | |
DDR[0]_BA[0] | F13 | O | DVDD_DDR[0] | |
DDR[0]_A[14] | D17 | O | DVDD_DDR[0] | DDR[0] Address Bus |
DDR[0]_A[13] | B16 | O | DVDD_DDR[0] | |
DDR[0]_A[12] | N16 | O | DVDD_DDR[0] | |
DDR[0]_A[11] | B13 | O | DVDD_DDR[0] | |
DDR[0]_A[10] | C14 | O | DVDD_DDR[0] | |
DDR[0]_A[9] | K13 | O | DVDD_DDR[0] | |
DDR[0]_A[8] | N14 | O | DVDD_DDR[0] | |
DDR[0]_A[7] | A14 | O | DVDD_DDR[0] | |
DDR[0]_A[6] | L13 | O | DVDD_DDR[0] | |
DDR[0]_A[5] | J13 | O | DVDD_DDR[0] | |
DDR[0]_A[4] | H13 | O | DVDD_DDR[0] | |
DDR[0]_A[3] | G13 | O | DVDD_DDR[0] | |
DDR[0]_A[2] | D15 | O | DVDD_DDR[0] | |
DDR[0]_A[1] | N17 | O | DVDD_DDR[0] | |
DDR[0]_A[0] | A13 | O | DVDD_DDR[0] | |
DDR[0]_D[31] | C9 | IO | DVDD_DDR[0] | DDR[0] Data Bus |
DDR[0]_D[30] | J11 | IO | DVDD_DDR[0] | |
DDR[0]_D[29] | C11 | IO | DVDD_DDR[0] | |
DDR[0]_D[28] | G10 | IO | DVDD_DDR[0] | |
DDR[0]_D[27] | E8 | IO | DVDD_DDR[0] | |
DDR[0]_D[26] | B10 | IO | DVDD_DDR[0] | |
DDR[0]_D[25] | B11 | IO | DVDD_DDR[0] | |
DDR[0]_D[24] | E9 | IO | DVDD_DDR[0] | |
DDR[0]_D[23] | E7 | IO | DVDD_DDR[0] | |
DDR[0]_D[22] | F9 | IO | DVDD_DDR[0] | |
DDR[0]_D[21] | D8 | IO | DVDD_DDR[0] | |
DDR[0]_D[20] | F8 | IO | DVDD_DDR[0] | |
DDR[0]_D[19] | B7 | IO | DVDD_DDR[0] | |
DDR[0]_D[18] | H10 | IO | DVDD_DDR[0] | |
DDR[0]_D[17] | A7 | IO | DVDD_DDR[0] | |
DDR[0]_D[16] | C8 | IO | DVDD_DDR[0] | |
DDR[0]_D[15] | B3 | IO | DVDD_DDR[0] | DDR[0] Data Bus |
DDR[0]_D[14] | A3 | IO | DVDD_DDR[0] | |
DDR[0]_D[13] | B6 | IO | DVDD_DDR[0] | |
DDR[0]_D[12] | A5 | IO | DVDD_DDR[0] | |
DDR[0]_D[11] | D6 | IO | DVDD_DDR[0] | |
DDR[0]_D[10] | C6 | IO | DVDD_DDR[0] | |
DDR[0]_D[9] | D7 | IO | DVDD_DDR[0] | |
DDR[0]_D[8] | C5 | IO | DVDD_DDR[0] | |
DDR[0]_D[7] | C1 | IO | DVDD_DDR[0] | |
DDR[0]_D[6] | F3 | IO | DVDD_DDR[0] | |
DDR[0]_D[5] | B2 | IO | DVDD_DDR[0] | |
DDR[0]_D[4] | D2 | IO | DVDD_DDR[0] | |
DDR[0]_D[3] | G4 | IO | DVDD_DDR[0] | |
DDR[0]_D[2] | E2 | IO | DVDD_DDR[0] | |
DDR[0]_D[1] | F2 | IO | DVDD_DDR[0] | |
DDR[0]_D[0] | B1 | IO | DVDD_DDR[0] | |
DDR[0]_VTP | A6 | I | DVDD_DDR[0] | DDR VTP Compensation Resistor Connection |
SIGNAL | TYPE(1) | OTHER(2) | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
DDR[1]_CLK[0] | B26 | O | DVDD_DDR[1] | DDR[1] Clock 0 |
DDR[1]_CLK[0] | A26 | O | DVDD_DDR[1] | DDR[1] Negative Clock 0 |
DDR[1]_CLK[1] | A23 | O | DVDD_DDR[1] | DDR[1] Clock 1 |
DDR[1]_CLK[1] | B23 | O | DVDD_DDR[1] | DDR[1] Negative Clock 1 |
DDR[1]_CKE | C20 | O | DVDD_DDR[1] | DDR[1] Clock Enable |
DDR[1]_WE | E25 | O | DVDD_DDR[1] | DDR[1] Write Enable |
DDR[1]_CS[0] | B21 | O | DVDD_DDR[1] | DDR[1] Chip Select 0 |
DDR[1]_CS[1] | F20 | O | DVDD_DDR[1] | DDR[1] Chip Select 1 |
DDR[1]_RAS | D25 | O | DVDD_DDR[1] | DDR[1] Row Address Strobe output |
DDR[1]_CAS | C25 | O | DVDD_DDR[1] | DDR[1] Column Address Strobe output |
DDR[1]_DQM[3] | D29 | O | DVDD_DDR[1] | DDR[1] Data Mask outputs DDR[1]_DQM[3]: For upper byte data bus DDR[1]_D[31:24] DDR[1]_DQM[2]: For DDR[1]_D[23:16] DDR[1]_DQM[1]: For DDR[1]_D[15:8] DDR[1]_DQM[0]: For lower byte data bus DDR[1]_D[7:0] |
DDR[1]_DQM[2] | G29 | O | DVDD_DDR[1] | |
DDR[1]_DQM[1] | B33 | O | DVDD_DDR[1] | |
DDR[1]_DQM[0] | C36 | O | DVDD_DDR[1] | |
DDR[1]_DQS[3] | B29 | O | DVDD_DDR[1] | Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[1] memory when writing and inputs when reading. They are used to synchronize the data transfers. DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24] DDR[1]_DQS[2]: For DDR[1]_D[23:16] DDR[1]_DQS[1]: For DDR[1]_D[15:8] DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0] |
DDR[1]_DQS[2] | B30 | IO | DVDD_DDR[1] | |
DDR[1]_DQS[1] | B34 | IO | DVDD_DDR[1] | |
DDR[1]_DQS[0] | F34 | IO | DVDD_DDR[1] | |
DDR[1]_DQS[3] | A29 | IO | DVDD_DDR[1] | Complementary data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[1] memory when writing and inputs when reading. They are used to synchronize the data transfers. DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24] DDR[1]_DQS[2]: For DDR[1]_D[23:16] DDR[1]_DQS[1]: For DDR[1]_D[15:8] DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0] |
DDR[1]_DQS[2] | A30 | IO | DVDD_DDR[1] | |
DDR[1]_DQS[1] | A34 | IO | DVDD_DDR[1] | |
DDR[1]_DQS[0] | E35 | IO | DVDD_DDR[1] | |
DDR[1]_ODT[0] | E20 | O | DVDD_DDR[1] | DDR[1] On-Die Termination for Chip Select 0. |
DDR[1]_ODT[1] | A22 | O | DVDD_DDR[1] | DDR[1] On-Die Termination for Chip Select 1. |
DDR[1]_RST | D20 | O | DVDD_DDR[1] | DDR[1] Reset output |
DDR[1]_BA[2] | N23 | O | DVDD_DDR[1] | DDR[1] Bank Address outputs |
DDR[1]_BA[1] | B24 | O | DVDD_DDR[1] | |
DDR[1]_BA[0] | F25 | O | DVDD_DDR[1] | |
DDR[1]_A[14] | D21 | O | DVDD_DDR[1] | DDR[1] Address Bus |
DDR[1]_A[13] | B22 | O | DVDD_DDR[1] | |
DDR[1]_A[12] | N22 | O | DVDD_DDR[1] | |
DDR[1]_A[11] | B25 | O | DVDD_DDR[1] | |
DDR[1]_A[10] | C24 | O | DVDD_DDR[1] | |
DDR[1]_A[9] | K25 | O | DVDD_DDR[1] | |
DDR[1]_A[8] | N24 | O | DVDD_DDR[1] | |
DDR[1]_A[7] | A24 | O | DVDD_DDR[1] | |
DDR[1]_A[6] | L25 | O | DVDD_DDR[1] | |
DDR[1]_A[5] | J25 | O | DVDD_DDR[1] | |
DDR[1]_A[4] | H25 | O | DVDD_DDR[1] | |
DDR[1]_A[3] | G25 | O | DVDD_DDR[1] | |
DDR[1]_A[2] | D23 | O | DVDD_DDR[1] | |
DDR[1]_A[1] | N21 | O | DVDD_DDR[1] | |
DDR[1]_A[0] | A25 | O | DVDD_DDR[1] | |
DDR[1]_D[31] | C29 | IO | DVDD_DDR[1] | DDR[1] Data Bus |
DDR[1]_D[30] | J27 | IO | DVDD_DDR[1] | |
DDR[1]_D[29] | C27 | IO | DVDD_DDR[1] | |
DDR[1]_D[28] | G28 | IO | DVDD_DDR[1] | |
DDR[1]_D[27] | E30 | IO | DVDD_DDR[1] | |
DDR[1]_D[26] | B28 | IO | DVDD_DDR[1] | |
DDR[1]_D[25] | B27 | IO | DVDD_DDR[1] | |
DDR[1]_D[24] | E29 | IO | DVDD_DDR[1] | |
DDR[1]_D[23] | E31 | IO | DVDD_DDR[1] | |
DDR[1]_D[22] | F29 | IO | DVDD_DDR[1] | |
DDR[1]_D[21] | D30 | IO | DVDD_DDR[1] | |
DDR[1]_D[20] | F30 | IO | DVDD_DDR[1] | |
DDR[1]_D[19] | B31 | IO | DVDD_DDR[1] | |
DDR[1]_D[18] | H28 | IO | DVDD_DDR[1] | |
DDR[1]_D[17] | A31 | IO | DVDD_DDR[1] | |
DDR[1]_D[16] | C30 | IO | DVDD_DDR[1] | |
DDR[1]_D[15] | B35 | IO | DVDD_DDR[1] | DDR[1] Data Bus |
DDR[1]_D[14] | A35 | IO | DVDD_DDR[1] | |
DDR[1]_D[13] | B32 | IO | DVDD_DDR[1] | |
DDR[1]_D[12] | A33 | IO | DVDD_DDR[1] | |
DDR[1]_D[11] | D32 | IO | DVDD_DDR[1] | |
DDR[1]_D[10] | C32 | IO | DVDD_DDR[1] | |
DDR[1]_D[9] | D31 | IO | DVDD_DDR[1] | |
DDR[1]_D[8] | C33 | IO | DVDD_DDR[1] | |
DDR[1]_D[7] | C37 | IO | DVDD_DDR[1] | |
DDR[1]_D[6] | F35 | IO | DVDD_DDR[1] | |
DDR[1]_D[5] | B36 | IO | DVDD_DDR[1] | |
DDR[1]_D[4] | D36 | IO | DVDD_DDR[1] | |
DDR[1]_D[3] | G34 | IO | DVDD_DDR[1] | |
DDR[1]_D[2] | E36 | IO | DVDD_DDR[1] | |
DDR[1]_D[1] | F36 | IO | DVDD_DDR[1] | |
DDR[1]_D[0] | B37 | IO | DVDD_DDR[1] | |
DDR[1]_VTP | A32 | I | DVDD_DDR[1] | DDR VTP Compensation Resistor Connection |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
MDIO_MCLK | AH37 | O | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
- PINCTRL275 |
Management Data Serial Clock output |
MDIO_MDIO | AH36 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL276 |
Management Data IO |
EMAC0 | |||||
EMAC[0]_COL | AB25 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL251 |
[G]MII Collision Detect (Sense) input |
EMAC[0]_CRS | AA25 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL252 |
[G]MII Carrier Sense input |
EMAC[0]_GMTCLK | AC37 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL253 |
GMII Source Asynchronous Transmit Clock |
EMAC[0]_RXCLK | AE37 | I | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL254 |
[G]MII Receive Clock |
EMAC[0]_RXD[7] | AE36 | I | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL262 |
[G]MII Receive Data [7:0]. For 1000 EMAC GMII operation, EMAC[0]_RXD[7:0] are used. For 10/100 EMAC MII operation, only EMAC[0]_RXD[3:0] are used. |
EMAC[0]_RXD[6] | AC25 | - PINCTRL261 |
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EMAC[0]_RXD[5] | AD25 | - PINCTRL260 |
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EMAC[0]_RXD[4] | AC35 | - PINCTRL259 |
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EMAC[0]_RXD[3] | AD35 | - PINCTRL258 |
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EMAC[0]_RXD[2] | AC36 | - PINCTRL257 |
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EMAC[0]_RXD[1] | AD36 | - PINCTRL256 |
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EMAC[0]_RXD[0] | AD37 | - PINCTRL255 |
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EMAC[0]_RXDV | AE35 | I | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL263 |
[G]MII Receive Data Valid input |
EMAC[0]_RXER | AE34 | I | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL264 |
[G]MII Receive Data Error input |
EMAC[0]_TXCLK | AF37 | I | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
- PINCTRL265 |
[G]MII Transmit Clock input |
EMAC[0]_TXD[7] | AG35 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL273 |
[G]MII Transmit Data [7:0]. For 1000 EMAC GMII operation, EMAC[0]_TXD[7:0] are used. For 10/100 EMAC MII operation, only EMAC[0]_TXD[3:0] are used. |
EMAC[0]_TXD[6] | AG36 | - PINCTRL272 |
|||
EMAC[0]_TXD[5] | AF36 | - PINCTRL271 |
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EMAC[0]_TXD[4] | AG28 | - PINCTRL270 |
|||
EMAC[0]_TXD[3] | AE30 | - PINCTRL269 |
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EMAC[0]_TXD[2] | AE31 | - PINCTRL268 |
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EMAC[0]_TXD[1] | AE32 | - PINCTRL267 |
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EMAC[0]_TXD[0] | AE33 | - PINCTRL266 |
|||
EMAC[0]_TXEN | AG37 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL274 |
[G]MII Transmit Data Enable output |
EMAC1 | |||||
EMAC[1]_COL | AR30 | I | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
-
PINCTRL72 |
[G]MII Collision Detect (Sense) input |
EMAC[1]_CRS | AN31 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL73 |
[G]MII Carrier Sense input |
EMAC[1]_GMTCLK | AU33 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL61 |
GMII Source Asynchronous Transmit Clock |
EMAC[1]_RXCLK | AT37 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL51 |
[G]MII Receive Clock |
EMAC[1]_RXD[7] | AP32 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL59 |
[G]MII Receive Data [7:0]. For 1000 EMAC GMII operation, EMAC[1]_RXD[7:0] are used. For 10/100 EMAC MII operation, only EMAC[1]_RXD[3:0] are used. |
EMAC[1]_RXD[6] | AU34 | -
PINCTRL58 |
|||
EMAC[1]_RXD[5] | AR33 | -
PINCTRL57 |
|||
EMAC[1]_RXD[4] | AU35 | -
PINCTRL56 |
|||
EMAC[1]_RXD[3] | AT34 | -
PINCTRL55 |
|||
EMAC[1]_RXD[2] | AU36 | -
PINCTRL54 |
|||
EMAC[1]_RXD[1] | AT35 | -
PINCTRL53 |
|||
EMAC[1]_RXD[0] | AT36 | -
PINCTRL52 |
|||
EMAC[1]_RXDV | AT33 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL60 |
[G]MII Receive Data Valid input |
EMAC[1]_RXER | AN30 | I | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
-
PINCTRL74 |
[G]MII Receive Data Error input |
EMAC[1]_TXCLK | AT30 | I | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
-
PINCTRL71 |
[G]MII Transmit Clock input |
EMAC[1]_TXD[7] | AM30 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL69 |
[G]MII Transmit Data [7:0]. For 1000 EMAC GMII operation, EMAC[1]_TXD[7:0] are used. For 10/100 EMAC MII operation, only EMAC[1]_TXD[3:0] are used. |
EMAC[1]_TXD[6] | AP30 | -
PINCTRL68 |
|||
EMAC[1]_TXD[5] | AT31 | -
PINCTRL67 |
|||
EMAC[1]_TXD[4] | AU31 | -
PINCTRL66 |
|||
EMAC[1]_TXD[3] | AU32 | -
PINCTRL65 |
|||
EMAC[1]_TXD[2] | AT32 | -
PINCTRL64 |
|||
EMAC[1]_TXD[1] | AR32 | -
PINCTRL63 |
|||
EMAC[1]_TXD[0] | AP31 | -
PINCTRL62 |
|||
EMAC[1]_TXEN | AU30 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL70 |
[G]MII Transmit Data Enable output |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
GPIO0 | |||||
Note: General-Purpose Input/Output (IO) pins can also serve as external interrupt inputs. | |||||
TIM7_OUT/ GPMC_A[12]/ GP0[31] |
G1 | IO | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
TIM7, GPMC PINCTRL206 |
General-Purpose Input/Output (IO) 0 [GP0] pin 31. |
TIM6_OUT/ GPMC_A[24]/ GP0[30] |
H1 | IO | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
TIM6, GPMC PINCTRL205 |
General-Purpose Input/Output (IO) 0 [GP0] pin 30. |
TIM5_OUT/ GP0[29] |
H34 | IO | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
TIM5 PINCTRL204 |
General-Purpose Input/Output (IO) 0 [GP0] pin 29. |
TIM4_OUT/ GP0[28] |
H33 | IO | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
TIM4 PINCTRL203 |
General-Purpose Input/Output (IO) 0 [GP0] pin 28. |
GPMC_A[12]/ GP0[27] |
H2 | IO | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
GPMC PINCTRL202 |
General-Purpose Input/Output (IO) 0 [GP0] pin 27. |
GPMC_A[21]/ GP0[26] |
H3 | IO | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
GPMC PINCTRL201 |
General-Purpose Input/Output (IO) 0 [GP0] pin 26. |
GP0[25] | H4 | IO | PULL: IPU / DIS DRIVE: H / L DVDD_3P3 |
-
PINCTRL200 |
General-Purpose Input/Output (IO) 0 [GP0] pin 25. |
GPMC_A[13]/ GP0[24] |
H6 | IO | PULL: IPU / IPD DRIVE: H / L DVDD_3P3 |
GPMC PINCTRL199 |
General-Purpose Input/Output (IO) 0 [GP0] pin 24. |
GPMC_A[14]/ GP0[23] |
H5 | IO | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
GPMC PINCTRL198 |
General-Purpose Input/Output (IO) 0 [GP0] pin 23. |
GPMC_A[15]/ GP0[22] |
J1 | IO | PULL: IPU / DIS DRIVE: H / L DVDD_3P3 |
GPMC PINCTRL197 |
General-Purpose Input/Output (IO) 0 [GP0] pin 22. |
GPMC_A[16]/ GP0[21] |
J2 | IO | PULL: DIS / IPD DRIVE: Z / Z DVDD_3P3 |
GPMC PINCTRL196 |
General-Purpose Input/Output (IO) 0 [GP0] pin 21. |
GPMC_A[27]/ GP0[20] |
AC5 | IO | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC PINCTRL233 |
General-Purpose Input/Output (IO) 0 [GP0] pin 20. |
GPMC_A[11]/ GP0[19] |
AC2 | IO | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC PINCTRL232 |
General-Purpose Input/Output (IO) 0 [GP0] pin 19. |
GPMC_A[10]/ GP0[18] |
AD1 | IO | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC PINCTRL231 |
General-Purpose Input/Output (IO) 0 [GP0] pin 18. |
GPMC_A[9]/ GP0[17]/ CS0WAIT |
AD2 | IO | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, BOOT PINCTRL230 |
General-Purpose Input/Output (IO) 0 [GP0] pin 17. |
GPMC_A[8]/ GP0[16]/ CS0BW |
AD4 | IO | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, BOOT PINCTRL229 |
General-Purpose Input/Output (IO) 0 [GP0] pin 16. |
GPMC_A[7]/ GP0[15]/ CS0MUX[1] |
AD3 | IO | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, BOOT PINCTRL228 |
General-Purpose Input/Output (IO) 0 [GP0] pin 15. |
GPMC_A[6]/ GP0[14]/ CS0MUX[0] |
AD8 | IO | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, BOOT PINCTRL227 |
General-Purpose Input/Output (IO) 0 [GP0] pin 14. |
GPMC_A[5]/ GP0[13]/ BTMODE[4] |
AE2 | IO | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, BOOT PINCTRL226 |
General-Purpose Input/Output (IO) 0 [GP0] pin 13. |
GPMC_A[4]/ GP0[12]/ BTMODE[3] |
AE1 | IO | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, BOOT PINCTRL225 |
General-Purpose Input/Output (IO) 0 [GP0] pin 12. |
GPMC_A[3]/ GP0[11]/ BTMODE[2] |
AE3 | IO | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, BOOT PINCTRL224 |
General-Purpose Input/Output (IO) 0 [GP0] pin 11. |
GPMC_A[2]/ GP0[10]/ BTMODE[1] |
AE4 | IO | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, BOOT PINCTRL223 |
General-Purpose Input/Output (IO) 0 [GP0] pin 10. |
GPMC_A[1]/ GP0[9]/ BTMODE[0] |
AE5 | IO | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, BOOT PINCTRL222 |
General-Purpose Input/Output (IO) 0 [GP0] pin 9. |
GPMC_A[0]/ GP0[8] |
AE6 | IO | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC PINCTRL221 |
General-Purpose Input/Output (IO) 0 [GP0] pin 8. |
GP0[7]/ MCA[0]_AMUTEIN |
H35 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[0] PINCTRL298 |
General-Purpose Input/Output (IO) 0 [GP0] pin 7. |
GP0[6]/ MCA[1]_AMUTEIN/ GPMC_A[23] |
G5 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[1], GPMC PINCTRL297 |
General-Purpose Input/Output (IO) 0 [GP0] pin 6. |
GP0[5]/ MCA[2]_AMUTEIN/ GPMC_A[24] |
G2 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[2], GPMC PINCTRL296 |
General-Purpose Input/Output (IO) 0 [GP0] pin 5. |
GP0[4] | H32 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL295 |
General-Purpose Input/Output (IO) 0 [GP0] pin 4. |
GP0[3]/ TCLKIN |
J31 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
Timer CLKIN PINCTRL294 |
General-Purpose Input/Output (IO) 0 [GP0] pin 3. |
GP0[2] | K30 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL293 |
General-Purpose Input/Output (IO) 0 [GP0] pin 2. |
GP0[1] | L29 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL292 |
General-Purpose Input/Output (IO) 0 [GP0] pin 1. |
GP0[0] | K31 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL291 |
General-Purpose Input/Output (IO) 0 [GP0] pin 0. |
GPIO1 | |||||
Note: General-Purpose Input/Output (IO) pins can also serve as external interrupt inputs. | |||||
GP1[31]/ SATA_ACT1_LED (silicon revision 1.x) SATA_ACT0_LED (silicon revision 2.x) |
J33 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SATA PINCTRL300 |
General-Purpose Input/Output (IO) 1 [GP1] pin 31. |
GP1[30]/ SATA_ACT0_LED (silicon revision 1.x) SATA_ACT1_LED (silicon revision 2.x) |
J32 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SATA PINCTRL299 |
General-Purpose Input/Output (IO) 1 [GP1] pin 30. |
GPMC_CLK/ GP1[29] |
V1 | IO | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
GPMC PINCTRL250 |
General-Purpose Input/Output (IO) 1 [GP1] pin 29. |
UART0_CTS/ GP1[28] |
N7 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART0 PINCTRL176 |
General-Purpose Input/Output (IO) 1 [GP1] pin 28. |
UART0_RTS/ GP1[27] |
N9 | IO | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
UART0 PINCTRL175 |
General-Purpose Input/Output (IO) 1 [GP1] pin 27. |
UART1_CTS/ GPMC_A[13]/ GPMC_A[17]/ GP1[26] |
L3 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART1, GPMC PINCTRL184 |
General-Purpose Input/Output (IO) 1 [GP1] pin 26. |
UART1_RTS/ GPMC_A[14]/ GPMC_A[18]/ GP1[25] |
M2 | IO | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
UART1, GPMC PINCTRL183 |
General-Purpose Input/Output (IO) 1 [GP1] pin 25. |
UART2_CTS/ GPMC_A[16]/ GPMC_A[25]/ GP1[24] |
K7 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART2, GPMC PINCTRL188 |
General-Purpose Input/Output (IO) 1 [GP1] pin 24. |
UART2_RTS/ GPMC_A[15]/ GPMC_A[26]/ GP1[23] |
L9 | IO | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
UART2, GPMC PINCTRL187 |
General-Purpose Input/Output (IO) 1 [GP1] pin 23. |
SPI_SCS[3]/ GPMC_A[21]/ GP1[22] |
P1 | IO | PULL: DIS / IPU DRIVE: Z / Z DVDD_3P3 |
SPI, GPMC PINCTRL170 |
General-Purpose Input/Output (IO) 1 [GP1] pin 22. |
GPMC_CS[4]/ GP1[21] |
AG3 | IO | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
GPMC PINCTRL211 |
General-Purpose Input/Output (IO) 1 [GP1] pin 21. |
GPMC_DIR/ GP1[20] |
AE7 | IO | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
GPMC PINCTRL218 |
General-Purpose Input/Output (IO) 1 [GP1] pin 20. |
UART0_RIN/ GPMC_A[17]/ GPMC_A[22]/ GP1[19] |
N3 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART0, GPMC PINCTRL180 |
General-Purpose Input/Output (IO) 1 [GP1] pin 19. |
UART0_DCD/ GPMC_A[18]/ GPMC_A[23]/ GP1[18] |
N5 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART0, GPMC PINCTRL179 |
General-Purpose Input/Output (IO) 1 [GP1] pin 18. |
UART0_DSR/ GPMC_A[19]/ GPMC_A[24]/ GP1[17] |
N4 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART0, GPMC PINCTRL178 |
General-Purpose Input/Output (IO) 1 [GP1] pin 17. |
UART0_DTR/ GPMC_A[20]/ GPMC_A[12]/ GP1[16] |
N6 | IO | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
UART0, GPMC PINCTRL177 |
General-Purpose Input/Output (IO) 1 [GP1] pin 16. |
GPMC_A[24]/ GP1[15] |
J3 | IO | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
GPMC PINCTRL195 |
General-Purpose Input/Output (IO) 1 [GP1] pin 15. |
GPMC_A[23]/ GP1[14] |
J4 | IO | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
GPMC PINCTRL194 |
General-Purpose Input/Output (IO) 1 [GP1] pin 14. |
GP1[13] | J5 | IO | PULL: IPU / DIS DRIVE: H / L DVDD_3P3 |
-
PINCTRL193 |
General-Purpose Input/Output (IO) 1 [GP1] pin 13. |
GPMC_A[25]/ GP1[12] |
J7 | IO | PULL: IPU / IPD DRIVE: H / L DVDD_3P3 |
GPMC PINCTRL192 |
General-Purpose Input/Output (IO) 1 [GP1] pin 12. |
GPMC_A[26]/ GP1[11] |
J6 | IO | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
GPMC PINCTRL191 |
General-Purpose Input/Output (IO) 1 [GP1] pin 11. |
GPMC_A[22]/ GP1[10] |
K2 | IO | PULL: IPU / DIS DRIVE: H / L DVDD_3P3 |
GPMC PINCTRL190 |
General-Purpose Input/Output (IO) 1 [GP1] pin 10. |
GPMC_A[27]/ GP1[9] |
K8 | IO | PULL: DIS / IPD DRIVE: Z / Z DVDD_3P3 |
GPMC PINCTRL189 |
General-Purpose Input/Output (IO) 1 [GP1] pin 9. |
SD_SDWP/ GPMC_A[15]/ GP1[8] |
R5 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GPMC PINCTRL165 |
General-Purpose Input/Output (IO) 1 [GP1] pin 8. |
SD_SDCD/ GPMC_A[16]/ GP1[7] |
R13 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GPMC PINCTRL164 |
General-Purpose Input/Output (IO) 1 [GP1] pin 7. |
SD_DAT[3]/ GPMC_A[17]/ GP1[6] |
T13 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GPMC PINCTRL163 |
General-Purpose Input/Output (IO) 1 [GP1] pin 6. |
SD_DAT[2]_SDRW/ GPMC_A[18]/ GP1[5] |
T2 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GPMC PINCTRL162 |
General-Purpose Input/Output (IO) 1 [GP1] pin 5. |
SD_DAT[1]_SDIRQ/ GPMC_A[19]/ GP1[4] |
T1 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GPMC PINCTRL161 |
General-Purpose Input/Output (IO) 1 [GP1] pin 4. |
SD_DAT[0]/ GPMC_A[20]/ GP1[3] |
U1 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GPMC PINCTRL160 |
General-Purpose Input/Output (IO) 1 [GP1] pin 3. |
SD_CMD/ GPMC_A[21]/ GP1[2] |
U3 | IO | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
SD, GPMC PINCTRL159 |
General-Purpose Input/Output (IO) 1 [GP1] pin 2. |
SD_CLK/ GPMC_A[13]/ GP1[1] |
U2 | IO | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
SD, GPMC PINCTRL158 |
General-Purpose Input/Output (IO) 1 [GP1] pin 1. |
SD_POW/ GPMC_A[14]/ GP1[0] |
U4 | IO | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
SD, GPMC PINCTRL157 |
General-Purpose Input/Output (IO) 1 [GP1] pin 0. |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
GPMC_CLK/ GP1[29] |
V1 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
GP1 | GPMC Clock output |
GPMC_CS[5]/ GPMC_A[12] |
AG1 | O | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
GPMC PINCTRL212 |
GPMC Chip Select 5 |
GPMC_CS[4]/ GP1[21] |
AG3 | O | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
GP1 PINCTRL211 |
GPMC Chip Select 4 |
GPMC_CS[3] | AG9 | O | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
- PINCTRL210 |
GPMC Chip Select 3 |
GPMC_CS[2] | AH2 | O | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
- PINCTRL209 |
GPMC Chip Select 2 |
GPMC_CS[1] | AH1 | O | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
- PINCTRL208 |
GPMC Chip Select 1 |
GPMC_CS[0] | AH7 | O | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
- PINCTRL207 |
GPMC Chip Select 0 |
GPMC_WE | AG2 | O | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
- PINCTRL213 |
GPMC Write Enable output |
GPMC_OE_RE | AF2 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
- PINCTRL214 |
GPMC Output Enable output |
GPMC_BE1 | AF1 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
- PINCTRL216 |
GPMC Upper Byte Enable output |
GPMC_BE0_CLE | AE11 | O | PULL: IPU / DIS DRIVE: H / L DVDD_3P3 |
- PINCTRL215 |
GPMC Lower Byte Enable output or Command Latch Enable output |
GPMC_ADV_ALE | AE10 | O | PULL: IPU / DIS DRIVE: H / L DVDD_3P3 |
- PINCTRL217 |
GPMC Address Valid output or Address Latch Enable output |
GPMC_DIR/ GP1[20] |
AE7 | O | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
GP1 PINCTRL218 |
GPMC Direction Control for External Transceivers |
GPMC_WP | AE9 | O | PULL: IPU / IPD DRIVE: H / L DVDD_3P3 |
- PINCTRL219 |
GPMC Write Protect output |
GPMC_WAIT | AE8 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL220 |
GPMC Wait input |
GPMC_A[27]/ GP0[20] |
AC5 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
GP0 PINCTRL233 |
GPMC Address 27 |
GPMC_A[27]/ GP1[9] |
K8 | O | PULL: DIS / IPD DRIVE: Z / Z DVDD_3P3 |
GP1 PINCTRL189 |
|
UART1_RXD/ GPMC_A[26]/ GPMC_A[20] |
N1 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
UART1, GPMC PINCTRL181 |
GPMC Address 26 |
UART2_RTS/ GPMC_A[15]/ GPMC_A[26]/ GP1[23] |
L9 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
UART2, GPMC, GP1 PINCTRL187 |
|
GPMC_A[26]/ GP1[11] |
J6 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
GP1 PINCTRL191 |
|
UART1_TXD/ GPMC_A[25]/ GPMC_A[19] |
N2 | O | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
UART1, GPMC PINCTRL182 |
GPMC Address 25 |
UART2_CTS/ GPMC_A[16]/ GPMC_A[25]/ GP1[24] |
K7 | O | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART2, GPMC, GP1 PINCTRL188 |
|
GPMC_A[25]/ GP1[12] |
J7 | O | PULL: IPU / IPD DRIVE: H / L DVDD_3P3 |
GP1 PINCTRL192 |
|
GP0[5]/ MCA[2]_AMUTEIN/ GPMC_A[24] |
G2 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GP0, MCA[2] PINCTRL296 |
GPMC Address 24 |
GPMC_A[24]/ GP1[15] |
J3 | O | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
GP1 PINCTRL195 |
|
TIM6_OUT/ GPMC_A[24]/ GP0[30] |
H1 | O | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
TIM6, GP0 PINCTRL205 |
|
UART0_DSR/ GPMC_A[19]/ GPMC_A[24]/ GP1[17] |
N4 | O | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART0, GPMC, GP1 PINCTRL178 |
|
GP0[6]/ MCA[1]_AMUTEIN/ GPMC_A[23] |
G5 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GP0, MCA[1] PINCTRL297 |
GPMC Address 23 |
SPI_SCS[1]/ GPMC_A[23] |
P2 | O | PULL: DIS / IPU DRIVE: Z / Z DVDD_3P3 |
SPI PINCTRL168 |
|
UART0_DCD/ GPMC_A[18]/ GPMC_A[23]/ GP1[18] |
N5 | O | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART0, GPMC, GP1 PINCTRL179 |
|
GPMC_A[23]/ GP1[14] |
J4 | O | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
GP1 PINCTRL194 |
|
SPI_SCS[2]/ GPMC_A[22] |
P3 | O | PULL: DIS / IPU DRIVE: Z / Z DVDD_3P3 |
SPI PINCTRL169 |
GPMC Address 22 |
GPMC_A[22]/ GP1[10] |
K2 | O | PULL: IPU / DIS DRIVE: H / L DVDD_3P3 |
GP1 PINCTRL190 |
|
UART0_RIN/ GPMC_A[17]/ GPMC_A[22]/ GP1[19] |
N3 | O | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART0, GPMC, GP1 PINCTRL180 |
|
SPI_SCS[3]/ GPMC_A[21]/ GP1[22] |
P1 | O | PULL: DIS / IPU DRIVE: Z / Z DVDD_3P3 |
SPI, GP1 PINCTRL170 |
GPMC Address 21 |
SD_CMD/ GPMC_A[21]/ GP1[2] |
U3 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
SD, GP1 PINCTRL159 |
|
GPMC_A[21]/ GP0[26] |
H3 | O | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
GP0 PINCTRL201 |
|
SD_DAT[0]/ GPMC_A[20]/ GP1[3] |
U1 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GP1 PINCTRL160 |
GPMC Address 20 |
UART0_DTR/ GPMC_A[20]/ GPMC_A[12]/ GP1[16] |
N6 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
UART0, GPMC, GP1 PINCTRL177 |
|
UART1_RXD/ GPMC_A[26]/ GPMC_A[20] |
N1 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
UART12, GPMC PINCTRL181 |
|
UART0_DSR/ GPMC_A[19]/ GPMC_A[24]/ GP1[17] |
N4 | O | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART0, GPMC, GP1 PINCTRL178 |
GPMC Address 19 |
SD_DAT[1]_SDIRQ/ GPMC_A[19]/ GP1[4] |
T1 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GP1 PINCTRL161 |
|
UART1_TXD/ GPMC_A[25]/ GPMC_A[19] |
N2 | O | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
UART1, GPMC PINCTRL182 |
|
SD_DAT[2]_SDRW/ GPMC_A[18]/ GP1[5] |
T2 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GP1 PINCTRL162 |
GPMC Address 18 |
UART0_DCD/ GPMC_A[18]/ GPMC_A[23]/ GP1[18] |
N5 | O | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART0, GPMC, GP1 PINCTRL179 |
|
UART1_RTS/ GPMC_A[14]/ GPMC_A[18]/ GP1[25] |
M2 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
UART1, GPMC, GP1 PINCTRL183 |
|
SD_DAT[3]/ GPMC_A[17]/ GP1[6] |
T13 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GP1 PINCTRL163 |
GPMC Address 17 |
UART0_RIN/ GPMC_A[17]/ GPMC_A[22]/ GP1[19] |
N3 | O | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART0, GPMC, GP1 PINCTRL180 |
|
UART1_CTS/ GPMC_A[13]/ GPMC_A[17]/ GP1[26] |
L3 | O | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART1, GPMC, GP1 PINCTRL184 |
|
SD_SDCD/ GPMC_A[16]/ GP1[7] |
R13 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GP1 PINCTRL164 |
GPMC Address 16 |
UART2_CTS/ GPMC_A[16]/ GPMC_A[25]/ GP1[24] |
K7 | O | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART2, GPMC, GP1 PINCTRL188 |
|
GPMC_A[16]/ GP0[21] |
J2 | O | PULL: DIS / IPD DRIVE: Z / Z DVDD_3P3 |
GPMC, GP0 PINCTRL196 |
|
SD_SDWP/ GPMC_A[15]/ GP1[8] |
R5 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
SD, GP1 PINCTRL165 |
GPMC Address 15 |
UART2_RTS/ GPMC_A[15]/ GPMC_A[26]/ GP1[23] |
L9 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
UART2, GPMC, GP1 PINCTRL187 |
|
GPMC_A[15]/ GP0[22] |
J1 | O | PULL: IPU / DIS DRIVE: H / L DVDD_3P3 |
GP0 PINCTRL197 |
|
SD_POW/ GPMC_A[14]/ GP1[0] |
U4 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
SD, GPMC, GP1 PINCTRL157 |
GPMC Address 14 |
UART1_RTS/ GPMC_A[14]/ GPMC_A[18]/ GP1[25] |
M2 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
UART1, GPMC, GP1 PINCTRL183 |
|
GPMC_A[14]/
GP0[23] |
H5 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
GP0 PINCTRL198 |
|
SD_CLK/ GPMC_A[13] / GP1[1] |
U2 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
SD, GP1 PINCTRL158 |
GPMC Address 13 |
UART1_CTS/ GPMC_A[13]/ GPMC_A[17]/ GP1[26] |
L3 | O | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
UART1, GPMC, GP1 PINCTRL184 |
|
GPMC_A[13]/ GP0[24] |
H6 | O | PULL: IPU / IPD DRIVE: H / L DVDD_3P3 |
GP0 PINCTRL199 |
|
UART0_DTR/ GPMC_A[20]/ GPMC_A[12]/ GP1[16] |
N6 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
UART0, GPMC, GP1 PINCTRL177 |
GPMC Address 12 |
GPMC_A[12]/ GP0[27] |
H2 | O | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
GP0 PINCTRL202 |
|
TIM7_OUT/ GPMC_A[12]/ GP0[31] |
G1 | O | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
TIM7, GP0 PINCTRL206 |
|
GPMC_CS[5]/ GPMC_A[12] |
AG1 | O | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
GPMC PINCTRL212 |
|
GPMC_A[11]/ GP0[19] |
AC2 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
GP0 PINCTRL232 |
GPMC Address 11 |
GPMC_A[10]/ GP0[18] |
AD1 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
GP0 PINCTRL231 |
GPMC Address 10 |
GPMC_A[9]/ GP0[17]/ CS0WAIT |
AD2 | O | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GP0, BOOT PINCTRL230 |
GPMC Address 9 |
GPMC_A[8]/ GP0[16]/ CS0BW |
AD4 | O | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GP0, BOOT PINCTRL229 |
GPMC Address 8 |
GPMC_A[7]/ GP0[15]/ CS0MUX[1] |
AD3 | O | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GP0, BOOT PINCTRL228 |
GPMC Address 7 |
GPMC_A[6]/ GP0[14]/ CS0MUX[0] |
AD8 | O | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GP0, BOOT PINCTRL227 |
GPMC Address 6 |
GPMC_A[5]/ GP0[13]/ BTMODE[4] |
AE2 | O | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GP0, BOOT PINCTRL226 |
GPMC Address 5 |
GPMC_A[4]/ GP0[12]/ BTMODE[3] |
AE1 | O | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GP0, BOOT PINCTRL225 |
GPMC Address 4 |
GPMC_A[3]/ GP0[11]/ BTMODE[2] |
AE3 | O | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GP0, BOOT PINCTRL224 |
GPMC Address 3 |
GPMC_A[2]/ GP0[10]/ BTMODE[1] |
AE4 | O | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GP0, BOOT PINCTRL223 |
GPMC Address 2 |
GPMC_A[1]/ GP0[9]/ BTMODE[0] |
AE5 | O | PULL: IPU / DIS DRIVE: Z / Z DVDD_3P3 |
GP0, BOOT PINCTRL222 |
GPMC Address 1 |
GPMC_A[0]/ GP0[8] |
AE6 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
GP0 PINCTRL221 |
GPMC Address 0 |
GPMC_D[15] | V2 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL249 |
GPMC Data IOs. Only D[7:0] are used for 8-bit interfaces |
GPMC_D[14] | V3 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL248 |
|
GPMC_D[13] | V10 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL247 |
|
GPMC_D[12] | W2 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL246 |
|
GPMC_D[11] | W1 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL245 |
|
GPMC_D[10] | W3 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL244 |
|
GPMC_D[9] | Y1 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL243 |
|
GPMC_D[8] | W4 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL242 |
|
GPMC_D[7] | Y2 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL241 |
|
GPMC_D[6] | Y10 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL240 |
|
GPMC_D[5] | AA2 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL239 |
|
GPMC_D[4] | Y3 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL238 |
|
GPMC_D[3] | AA3 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL237 |
|
GPMC_D[2] | AB2 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL236 |
|
GPMC_D[1] | AA4 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL235 |
|
GPMC_D[0] | AC1 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL234 |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
HDMI_TMDSCLKP | AT24 | O | - VDDA_HDMI |
- | HDMI Clock Output. When the HDMI PHY is powered down, these pins should be left unconnected. |
HDMI_TMDSCLKN | AU24 | O | - VDDA_HDMI |
- | |
HDMI_TMDSDN2 | AU27 | O | - VDDA_HDMI |
- | HDMI Data 2 output. When the HDMI PHY is powered down, these pins should be left unconnected. |
HDMI_TMDSDP2 | AT27 | O | - VDDA_HDMI |
- | |
HDMI_TMDSDN1 | AU26 | O | - VDDA_HDMI |
- | HDMI Data 1 output. When the HDMI PHY is powered down, these pins should be left unconnected. |
HDMI_TMDSDP1 | AT26 | O | - VDDA_HDMI |
- | |
HDMI_TMDSDN0 | AU25 | O | - VDDA_HDMI |
- | HDMI Data 0 output. When the HDMI PHY is powered down, these pins should be left unconnected. |
HDMI_TMDSDP0 | AT25 | O | - VDDA_HDMI |
- | |
HDMI_SCL | AL25 | O | PULL: DIS / DIS DRIVE: Z / Z DVDD_3P3 |
- PINCTRL301 |
HDMI I2C Serial Clock Output |
HDMI_SDA | AK25 | IO | PULL: DIS / DIS DRIVE: Z / Z DVDD_3P3 |
- PINCTRL302 |
HDMI I2C Serial Data IO |
HDMI_CEC | AP25 | IO | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
- PINCTRL303 |
HDMI Consumer Electronics Control IO |
HDMI_HPDET | AE24 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL304 |
HDMI Hot Plug Detect Input. Signals the connection / removal of an HDMI cable at the connector. |
HDMI_EXTSWING | AN25 | A | - | - | HDMI Voltage Reference. When HDMI is used, this pin must be connected via an external 6.8K-Ω (±1% tolerance) resistor to VSS. When the HDMI PHY is powered down, this pin should be left unconnected. |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
I2C0 | |||||
I2C[0]_SCL | N32 | IO | PULL: DIS / DIS DRIVE: Z / Z DVDD_3P3 |
- PINCTRL287 |
I2C0 Clock IO |
I2C[0]_SDA | N33 | IO | PULL: DIS / DIS DRIVE: Z / Z DVDD_3P3 |
- PINCTRL288 |
I2C0 Data IO |
I2C1 | |||||
I2C[1]_SCL | N34 | IO | PULL: DIS / DIS DRIVE: Z / Z DVDD_3P3 |
- PINCTRL289 |
I2C1 Clock IO |
I2C[1]_SDA | N35 | IO | PULL: DIS / DIS DRIVE: Z / Z DVDD_3P3 |
- PINCTRL290 |
I2C1 Data IO |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
MCA[0]_ACLKR | AK28 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL126 |
McASP0 Receive Bit Clock IO |
MCA[0]_AHCLKR | AJ27 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL127 |
McASP0 Receive High-Frequency Master Clock IO |
MCA[0]_AFSR | AG29 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL128 |
McASP0 Receive Frame Sync IO |
GP0[7]/ MCA[0]_AMUTEIN |
H35 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GP0 PINCTRL298 |
McASP0 Mute Input |
MCA[0]_ACLKX | AH30 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL129 |
McASP0 Transmit Bit Clock IO |
MCA[0]_AHCLKX | AH31 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL130 |
McASP0 Transmit High-Frequency Master Clock IO |
MCA[0]_AFSX | AJ31 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL131 |
McASP0 Transmit Frame Sync IO |
MCA[0]_AMUTE | AJ35 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL132 |
McASP0 Mute Output |
MCA[0]_AXR[5]/ MCB_DR |
AJ37 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCB PINCTRL138 |
McASP0 Transmit/Receive Data IOs |
MCA[0]_AXR[4]/ MCB_DX |
AJ36 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCB PINCTRL137 |
|
MCA[0]_AXR[3]/ MCB_FSR |
AJ34 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCB PINCTRL136 |
|
MCA[0]_AXR[2]/ MCB_FSX |
AJ33 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCB PINCTRL135 |
|
MCA[0]_AXR[1] | AJ32 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL134 |
|
MCA[0]_AXR[0] | AK37 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL133 |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
MCA[1]_ACLKR | AK36 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL139 |
McASP1 Receive Bit Clock IO |
MCA[1]_AHCLKR | AL37 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL140 |
McASP1 Receive High-Frequency Master Clock IO |
MCA[1]_AFSR | AK35 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL141 |
McASP1 Receive Frame Sync IO |
GP0[6]/ MCA[1]_AMUTEIN/ GPMC_A[23] |
G5 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GP0, GPMC PINCTRL297 |
McASP1 Mute Input |
MCA[1]_ACLKX | AL36 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL142 |
McASP1 Transmit Bit Clock IO |
MCA[1]_AHCLKX | AM37 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL143 |
McASP1 Transmit High-Frequency Master Clock IO |
MCA[1]_AFSX | AK34 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL144 |
McASP1 Transmit Frame Sync IO |
MCA[1]_AMUTE | AK33 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL145 |
McASP1 Mute Output |
MCA[1]_AXR[1] | AK32 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL147 |
McASP1 Transmit/Receive Data IOs |
MCA[1]_AXR[0] | AL33 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL146 |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
MCA[2]_ACLKR/ MCB_CLKR/ MCB_DR |
AL34 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCB PINCTRL148 |
McASP2 Receive Bit Clock IO |
MCA[2]_AHCLKR/ MCB_CLKS |
AM34 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCB PINCTRL149 |
McASP2 Receive High-Frequency Master Clock IO |
MCA[2]_AFSR/ MCB_CLKX/ MCB_FSR |
AM35 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCB PINCTRL150 |
McASP2 Receive Frame Sync IO |
GP0[5]/ MCA[2]_AMUTEIN/ GPMC_A[24] |
G2 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GP0, GPMC PINCTRL296 |
McASP2 Mute Input |
MCA[2]_ACLKX/ MCB_CLKX |
AM36 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCB PINCTRL151 |
McASP2 Transmit Bit Clock IO |
MCA[2]_AHCLKX/ MCB_CLKR |
AN36 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCB PINCTRL152 |
McASP2 Transmit High-Frequency Master Clock IO |
MCA[2]_AFSX/ MCB_CLKS/ MCB_FSX |
AN35 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCB PINCTRL153 |
McASP2 Transmit Frame Sync IO |
MCA[2]_AMUTE | AP36 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL154 |
McASP2 Mute Output |
MCA[2]_AXR[1]/ MCB_DX |
AR37 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCB PINCTRL156 |
McASP2 Transmit/Receive Data IOs |
MCA[2]_AXR[0] | AR36 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL155 |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
MCA[2]_ACLKR/ MCB_CLKR/ MCB_DR |
AL34 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[2], MCB PINCTRL148 |
McBSP Receive Clock IO |
MCA[2]_AHCLKX/ MCB_CLKR |
AN36 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[2] PINCTRL152 |
|
MCA[0]_AXR[3]/ MCB_FSR |
AJ34 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[0] PINCTRL136 |
McBSP Receive Frame Sync IO |
MCA[2]_AFSR/ MCB_CLKX/ MCB_FSR |
AM35 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[2], MCB PINCTRL150 |
|
MCA[0]_AXR[5]/ MCB_DR |
AJ37 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[0] PINCTRL138 |
McBSP Receive Data Input |
MCA[2]_ACLKR/ MCB_CLKR/ MCB_DR |
AL34 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[2], MCB PINCTRL148 |
|
MCA[2]_AFSR/ MCB_CLKX/ MCB_FSR |
AM35 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[2], MCB PINCTRL150 |
McBSP Transmit Clock IO |
MCA[2]_ACLKX/ MCB_CLKX |
AM36 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[2] PINCTRL151 |
|
MCA[0]_AXR[2]/ MCB_FSX |
AJ33 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[0] PINCTRL135 |
McBSP Transmit Frame Sync IO |
MCA[2]_AFSX/ MCB_CLKS/ MCB_FSX |
AN35 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[2], MCB PINCTRL153 |
|
MCA[0]_AXR[4]/ MCB_DX |
AJ36 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[0] PINCTRL137 |
McBSP Transmit Data Output |
MCA[2]_AXR[1]/ MCB_DX |
AR37 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[2] PINCTRL156 |
|
MCA[2]_AHCLKR/ MCB_CLKS |
AM34 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[2] PINCTRL149 |
McBSP Source Clock Input |
MCA[2]_AFSX/ MCB_CLKS/ MCB_FSX |
AN35 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
MCA[2], MCB PINCTRL153 |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
CLOCK GENERATOR | |||||
CLKOUT | F1 | O | PULL: IPU / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL320 |
Device Clock output. Can be used as a system clock for other devices |
OSCILLATOR/PLL | |||||
DEV_MXI/ DEV_CLKIN |
A19 | I | DIS DEV_DVDD18 |
- | Device Crystal input. Crystal connection to internal oscillator for system clock. Functions as CLKINDEV clock input when an external oscillator is used. |
DEV_MXO | C19 | O | DIS DEV_DVDD18 |
- | Device Crystal output. Crystal connection to internal oscillator for system clock. When device oscillator is BYPASSED, leave this pin unconnected. |
DEVOSC_DVDD18 | E19 | S | - | - | 1.8 V Power Supply for Device (DEV) Oscillator. If the internal oscillator is bypassed, DEVOSC_DVDD18 should still be connected to the 1.8-V power supply. |
DEVOSC_VSS | B19 | GND | - | - | Supply Ground for DEV Oscillator. If the internal oscillator is bypassed, DEVOSC_VSS should be connected to ground (VSS). |
CLKIN32 | H37 | I | PULL: IPU / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL321 |
RTC Clock input. Optional 32.768 kHz clock for RTC reference. If this pin is not used, it should be held low. |
SIGNAL | TYPE(1) | OTHER(2) | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
PCIE_TXP0 | AB31 | O | VDDR_PCIE | PCIE Transmit Data Lane 0. When the PCIe SERDES are powered down, or if this lane is not used, these pins should be left unconnected. |
PCIE_TXN0 | AB30 | O | ||
PCIE_RXP0 | Y29 | I | VDDR_PCIE | PCIE Receive Data Lane 0. When the PCIe SERDES are powered down, or if this lane is not used, these pins should be left unconnected. |
PCIE_RXN0 | V29 | I | ||
PCIE_TXP1 | Y27 | O | VDDR_PCIE | PCIE Transmit Data Lane 1. When the PCIe SERDES are powered down, or if this lane is not used, these pins should be left unconnected. |
PCIE_TXN1 | AB28 | O | ||
PCIE_RXP1 | V31 | I | VDDR_PCIE | PCIE Receive Data Lane 1. When the PCIe SERDES are powered down, or if this lane is not used, these pins should be left unconnected. |
PCIE_RXN1 | V30 | I | ||
SERDES_CLKP | AB34 | I | VDD_LJCB | PCIE Serdes Reference Clock Inputs. Shared between PCI Express and Serial ATA. When neither PCI Express nor Serial ATA are used, these pins should be left unconnected. |
SERDES_CLKN | AB33 | I | VDD_LJCB |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
RESET | |||||
RESET | G33 | I | PULL: IPD / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL316 |
Device Reset input |
POR | F37 | I | IPU DVDD_3P3 |
- | Power-On Reset input |
RSTOUT | G37 | O | PULL: DIS / DIS DVDD_3P3 |
- PINCTRL318 |
Reset output For more detailed information on RSTOUT pin behavior, see Section 8.2.13 |
INTERRUPTS | |||||
NMI | G36 | I | PULL: IPD / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL317 |
External active low maskable interrupt |
GP0[31:3] | see Table 4-5 |
IO | see NOTE | - | Interrupt-capable general-purpose IOs NOTE: All pins are multiplexed with other pin functions. For muxing and internal pullup, pulldown, or disable details, see Table 4-5, GPIO Terminal Functions. |
GP1[31:0] | see Table 4-5 |
IO | see NOTE | - | Interrupt-capable general-purpose IOs NOTE: All pins are multiplexed with other pin functions. For muxing and internal pullup, pulldown, or disable details, see Table 4-5, GPIO Terminal Functions. |
JTAG | |||||
TCLK | J37 | I | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
- PINCTRL305 |
JTAG test clock input |
RTCK | J36 | O | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
- PINCTRL306 |
JTAG return clock output |
TDI | J34 | I | PULL: IPU / IPU DRIVE: H / H DVDD_3P3 |
- PINCTRL307 |
JTAG test data input |
TDO | N30 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
- PINCTRL308 |
JTAG test port data output |
TMS | N31 | I | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL309 |
JTAG test port mode select input. For proper operation, do not oppose the IPU on this pin. |
TRST | K36 | I | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
- PINCTRL310 |
JTAG test port reset input |
EMU4 | M37 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL315 |
Emulator pin 4 |
EMU3 | M36 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL314 |
Emulator pin 3 |
EMU2 | L37 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL313 |
Emulator pin 2 |
EMU1 | L36 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL312 |
Emulator pin 1 |
EMU0 | J35 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL311 |
Emulator pin 0 |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
SD_CLK/ GPMC_A[13]/ GP1[1] |
U2 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
GPMC, GP1 PINCTRL158 |
SD Clock output |
SD_CMD/ GPMC_A[21]/ GP1_[2] |
U3 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
GPMC, GP1 PINCTRL159 |
SD Command output |
SD_DAT[0]/ GPMC_A[20]/ GP1[3] |
U1 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GPMC, GP1 PINCTRL160 |
SD Data0 IO. Functions as data bit 0 for 4-bit SD mode and single data bit for 1-bit SD mode. |
SD_DAT[1]_SDIRQ/ GPMC_A[19]/ GP1[4] |
T1 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GMPC, GP1 PINCTRL161 |
SD Data1 IO. Functions as data bit 1 for 4-bit SD mode and as an IRQ input for 1-bit SD mode |
SD_DAT[2]_SDRW/ GPMC_A[18]/ GP1[5] |
T2 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GPMC, GP1 PINCTRL162 |
SD Data2 IO. Functions as data bit 2 for 4-bit SD mode and as a Read Wait input for 1-bit SD mode. |
SD_DAT[3]/ GPMC_A[17]/ GP1[6] |
T13 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GPMC, GP1 PINCTRL163 |
SD Data3 IO. Functions as data bit 3 for 4-bit SD mode. |
SD_POW/ GPMC_A[14]/ GP1[0] |
U4 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
GPMC, GP1 PINCTRL157 |
SD Card Power Enable output |
SD_SDCD/ GPMC_A[16]/ GP1[7] |
R13 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GPMC, GP1 PINCTRL164 |
SD Card Detect input |
SD_SDWP/ GPMC_A[15]/ GP1[8] |
R5 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GMC, GP1 PINCTRL165 |
SD Card Write Protect input |
NOTE
Serial ATA pins J32 and J33 have a different naming convention and functionality for silicon revision 1.x devices and silicon revision 2.x devices. These pins are listed separately in Table 4-18.
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
SATA_TXN0 | T31 | O | - VDDR_SATA |
- | Serial ATA Data Transmit for disk 0. When the SATA SERDES are powered down, these pins should be left unconnected. |
SATA_TXP0 | T32 | O | - VDDR_SATA |
- | |
SATA_TXN1 | U33 | O | - VDDR_SATA |
- | Serial ATA Data Transmit for disk 1. When the SATA SERDES are powered down, these pins should be left unconnected. |
SATA_TXP1 | V33 | O | - VDDR_SATA |
- | |
SATA_RXN0 | V37 | I | - VDDR_SATA |
- | Serial ATA Data Receive for disk 0. When the SATA SERDES are powered down, these pins should be left unconnected. |
SATA_RXP0 | V36 | I | - VDDR_SATA |
- | |
SATA_RXN1 | V35 | I | - VDDR_SATA |
- | Serial ATA Data Receive for disk 1. When the SATA SERDES are powered down, these pins should be left unconnected. |
SATA_RXP1 | W35 | I | - VDDR_SATA |
- | |
SERDES_CLKP | AB34 | I | - VDD_LJCB |
- | PCIE Serdes Reference Clock Input. Shared between PCI Express and Serial ATA. |
SERDES_CLKN | AB33 | I | - VDD_LJCB |
- |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
Silicon Revision 1.x | |||||
GP1[30]/ SATA_ACT0_LED |
J32 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GP1 PINCTRL299 |
Serial ATA disk 0 Activity LED output |
GP1[31]/ SATA_ACT1_LED |
J33 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GP1 PINCTRL300 |
Serial ATA disk 1 Activity LED output |
Silicon Revision 2.x | |||||
GP1[30]/ SATA_ACT1_LED |
J32 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GP1 PINCTRL299 |
Serial ATA disk 1 Activity LED output |
GP1[31]/ SATA_ACT0_LED |
J33 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GP1 PINCTRL300 |
Serial ATA disk 0 Activity LED output |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
SPI_SCLK | R2 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL166 |
SPI Clock IO |
SPI_SCS[3]/ GPMC_A[21]/ GP1[22] |
P1 | IO | PULL: DIS / IPU DRIVE: Z / Z DVDD_3P3 |
GPMC, GP1 PINCTRL170 |
SPI Chip Select IO |
SPI_SCS[2]/ GPMC_A[22] |
P3 | IO | PULL: DIS / IPU DRIVE: Z / Z DVDD_3P3 |
GPMC PINCTRL169 |
|
SPI_SCS[1]/ GPMC_A[23] |
P2 | IO | PULL: DIS / IPU DRIVE: Z / Z DVDD_3P3 |
GPMC PINCTRL168 |
|
SPI_SCS[0] | R1 | IO | PULL: DIS / IPU DRIVE: Z / Z DVDD_3P3 |
- PINCTRL167 |
|
SPI_D[1] | P13 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL172 |
SPI Data IO. Can be configured as either MISO or MOSI |
SPI_D[0] | N11 | IO | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL171 |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
General-Purpose Timers7-1 and Watchdog Timer | |||||
GP0[3]/ TCLKIN |
J31 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GP0 PINCTRL294 |
Timer external clock input |
Timer7 | |||||
TIM7_OUT/ GPMC_A[12]/ GP0[31] |
G1 | IO | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
GPMC, GP0 PINCTRL206 |
Timer7 capture event input or PWM output |
Timer6 | |||||
TIM6_OUT/ GPMC_A[24]/ GP0[30] |
H1 | IO | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
GPMC, GP0 PINCTRL205 |
Timer6 capture event input or PWM output |
Timer5 | |||||
TIM5_OUT/ GP0[29] |
H34 | IO | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
GP0 PINCTRL204 |
Timer5 capture event input or PWM output |
Timer4 | |||||
TIM4_OUT/ GP0[28] |
H33 | IO | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
GP0 PINCTRL203 |
Timer4 capture event input or PWM output |
Timer3-1 | |||||
There are no external pins on these timers for this device. | |||||
Watchdog Timer | |||||
WD_OUT | H36 | O | PULL: IPU / IPU DRIVE: H / L DVDD_3P3 |
- PINCTRL319 |
Watchdog timer event output |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
UART0_RXD | N10 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL173 |
UART0 Receive Data Input. Functions as IrDA receive input in IrDA modes and CIR receive input in CIR mode. |
UART0_TXD | N8 | O | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
- PINCTRL174 |
UART0 Transmit Data Output. Functions as transmit output in CIR and IrDA modes. |
UART0_RTS/ GP1[27] |
N9 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
GP1 PINCTRL175 |
UART0 Request to Send Output. Indicates module is ready to receive data. Functions as SD output in IrDA mode. |
UART0_CTS/ GP1[28] |
N7 | I | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
GP1 PINCTRL176 |
UART0 Clear to Send Input. Has no function in IrDA and CIR modes. |
UART0_DTR/ GPMC_A[20]/ GPMC_A[12]/ GP1[16] |
N6 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
GPMC, GP1 PINCTRL177 |
UART0 Data Terminal Ready Output |
UART0_DSR/ GPMC_A[19]/ GPMC_A[24]/ GP1[17] |
N4 | I | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
GPMC, GP1 PINCTRL178 |
UART0 Data Set Ready Input |
UART0_DCD/ GPMC_A[18]/ GPMC_A[23]/ GP1[18] |
N5 | I | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
GPMC, GP1 PINCTRL179 |
UART0 Data Carrier Detect Input |
UART0_RIN/ GPMC_A[17]/ GPMC_A[22]/ GP1[19] |
N3 | I | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
GPMC, GP1 PINCTRL180 |
UART0 Ring Indicator Input |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
UART1_RXD/ GPMC_A[26]/ GPMC_A[20] |
N1 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
GPMC PINCTRL181 |
UART1 Receive Data Input. Functions as IrDA receive input in IrDA modes and CIR receive input in CIR mode. |
UART1_TXD/ GPMC_A[25]/ GPMC_A[19] |
N2 | O | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
GPMC PINCTRL182 |
UART1 Transmit Data Output. Functions as transmit output in CIR and IrDA modes. |
UART1_RTS/ GPMC_A[14]/ GPMC_A[18]/ GP1[25] |
M2 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
GPMC, GP1 PINCTRL183 |
UART1 Request to Send Output. Indicates module is ready to receive data. Functions as SD output in IrDA mode. |
UART1_CTS/ GPMC_A[13]/ GPMC_A[17]/ GP1[26] |
L3 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
GPMC, GP1 PINCTRL184 |
UART1 Clear to Send Input. Has no function in IrDA and CIR modes. |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
UART2_RXD | M1 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL185 |
UART2 Receive Data Input. Functions as IrDA receive input in IrDA modes and CIR receive input in CIR mode. |
UART2_TXD | L2 | O | PULL: IPD / IPD DRIVE: L / H DVDD_3P3 |
- PINCTRL186 |
UART2 Transmit Data Output. Functions as transmit output in CIR and IrDA modes. |
UART2_RTS/ GPMC_A[15]/ GPMC_A[26]/ GP1[23] |
L9 | O | PULL: IPU / DIS DRIVE: H / H DVDD_3P3 |
GPMC, GP1 PINCTRL187 |
UART2 Request to Send Output. Indicates module is ready to receive data. Functions as SD output in IrDA mode. |
UART2_CTS/ GPMC_A[16]/ GPMC_A[25]/ GP1[24] |
K7 | IO | PULL: IPU / IPU DRIVE: Z / Z DVDD_3P3 |
GPMC, GP1 PINCTRL188 |
UART2 Clear to Send Input. Has no function in IrDA and CIR modes. |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
USB0 | |||||
USB0_DP | P37 | A IO | - | - | USB0 bidirectional Data Differential signal pair [positive/negative]. When the USB0 PHY is powered down, these pins should be left unconnected. |
USB0_DN | P36 | A IO | - | - | |
USB0_R1 | N37 | A O | - | - | USB0 current reference output. When the USB0 peripheral is used, this pin must be connected via a 44.2-Ω ±1% resistor to VSS. When the USB0 PHY is powered down, this pin should be left unconnected. |
USB0_DRVVBUS | P35 | O | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
- PINCTRL322 |
When this pin is used as USB0_DRVVBUS and the USB0 Controller is operating as a Host, this signal is used by the USB0 Controller to enable the external VBUS charge pump. When the USB0 PHY is powered down, this pin should be left unconnected. |
VDD_USB0_VBUS | N36 | I | - | - | USB0 VBUS input (5 V). The voltage level on this pin is sampled to determine session status. When the USB0 PHY is powered down, this pin should be left unconnected. |
USB1 | |||||
USB1_DP | R37 | A IO | - | - | USB1 bidirectional Data Differential signal pair [positive/negative]. When the USB1 PHY is powered down, these pins should be left unconnected. |
USB1_DN | R36 | A IO | - | - | |
USB1_R1 | T37 | A O | - | - | USB1 current reference output. When the USB1 peripheral is used, this pin must be connected via a 44.2-Ω ±1% resistor to VSS. When the USB1 PHY is powered down, this pin should be left unconnected. |
USB1_DRVVBUS | R35 | O | PULL: IPD / IPD DRIVE: L / L DVDD_3P3 |
- PINCTRL323 |
When this pin is used as USB1_DRVVBUS and the USB1 Controller is operating as a Host, this signal is used by the USB1 Controller to enable the external VBUS charge pump. When the USB1 PHY is powered down, this pin should be left unconnected. |
VDD_USB1_VBUS | T36 | I | - | - | USB1 VBUS input (5 V). The voltage level on this pin is sampled to determine session status. When the USB1 PHY is powered down, this pin should be left unconnected. |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
VIN[0]A_CLK | AR14 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL83 |
Video Input 0 Port A Clock input. Input clock for 8-bit, 16-bit, or 24-bit Port A video capture. |
VIN[0]B_CLK | AR19 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL84 |
Video Input 0 Port B Clock input. Input clock for 8-bit Port B video capture. This signal is not used in 16-bit and 24-bit capture modes. |
VIN[0]A_D[23]/ VIN[0]B_HSYNC |
AT2 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]B PINCTRL15 |
Video Input 0 Port A Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs and D[15:8] are Port B YCbCr data inputs. For RGB capture, D[23:16] are R, D[15:8] are G, and D[7:0] are B data inputs. |
VIN[0]A_D[22]/ VIN[0]B_VSYNC |
AR2 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]B PINCTRL14 |
|
VIN[0]A_D[21]/ VIN[0]B_FLD |
AU4 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]B PINCTRL13 |
|
VIN[0]A_D[20]/ VIN[0]B_DE |
AN3 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]B PINCTRL12 |
|
VIN[0]A_D[19]/ VIN[1]A_DE[0]/ VOUT[1]_C[9] |
AK4 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A, VOUT[1] PINCTRL25 |
|
VIN[0]A_D[18]/ VIN[1]A_FLD/ VOUT[1]_C[8] |
AK5 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A, VOUT[1] PINCTRL24 |
|
VIN[0]A_D[17]/ VIN[1]A_VSYNC/ VOUT[1]_VSYNC (silicon revision 1.x) DAC_VOUT[1]_VSYNC (silicon revision 2.x) |
AL5 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A, VOUT[1] PINCTRL23 |
|
VIN[0]A_D[16]/ VIN[1]A_HSYNC/ VOUT[1]_FLD |
AT5 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A, VOUT[1] PINCTRL22 |
|
VIN[0]A_D[15] | AU14 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL100 |
Video Input 0 Port A Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs and D[15:8] are Port B YCbCr data inputs. For RGB capture, D[23:16] are R, D[15:8] are G, and D[7:0] are B data inputs. |
VIN[0]A_D[14] | AU15 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL99 |
|
VIN[0]A_D[13] | AT15 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL98 |
|
VIN[0]A_D[12] | AU16 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL97 |
|
VIN[0]A_D[11] | AU17 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL96 |
|
VIN[0]A_D[10] | AT16 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL95 |
|
VIN[0]A_D[9] | AE16 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL94 |
|
VIN[0]A_D[8] | AP17 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL93 |
|
VIN[0]A_D[7] | AR17 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL92 |
|
VIN[0]A_D[6] | AP18 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL91 |
|
VIN[0]A_D[5] | AT17 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL90 |
|
VIN[0]A_D[4] | AT18 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL89 |
|
VIN[0]A_D[3] | AR18 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL88 |
|
VIN[0]A_D[2] | AH18 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL87 |
|
VIN[0]A_D[1] | AU18 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL86 |
|
VIN[0]A_D[0] | AJ19 | I | IPD DVDD_3P3 |
- PINCTRL85 |
|
VIN[0]A_D[23]/ VIN[0]B_HSYNC |
AT2 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A PINCTRL15 |
Video Input 0 Port B Horizontal Sync input. Discrete horizontal synchronization signal for Port B 8-bit YCbCr capture without embedded syncs ("BT.601" modes). Not used in RGB or 16-bit YCbCr capture modes |
VIN[0]A_HSYNC | AU5 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL32 |
Video Input 0 Port A Horizontal Sync input. Discrete horizontal synchronization signal for Port A RGB capture mode or YCbCr capture without embedded syncs ("BT.601" modes). |
VIN[0]A_D[22]/ VIN[0]B_VSYNC |
AR2 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A PINCTRL14 |
Video Input 0 Port B Vertical Sync input. Discrete vertical synchronization signal for Port B 8-bit YCbCr capture without embedded syncs ("BT.601" modes). Not used in RGB or 16-bit YCbCr capture modes. |
VIN[0]A_VSYNC | AM4 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL33 |
Video Input 0 Port A Vertical Sync input. Discrete vertical synchronization signal for Port A RGB capture mode or YCbCr capture without embedded syncs ("BT.601" modes). |
VIN[0]A_D[21]/ VIN[0]B_FLD |
AU4 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A PINCTRL13 |
Video Input 0 Port B Field ID input. Discrete field identification signal for Port B 8-bit YCbCr capture without embedded syncs ("BT.601" modes). Not used in RGB or 16-bit YCbCr capture modes |
VIN[0]A_FLD | AL4 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL34 |
Video Input 0 Port A Field ID input. Discrete field identification signal for Port A RGB capture mode or YCbCr capture without embedded syncs ("BT.601" modes). |
VIN[0]A_D[20]/ VIN[0]B_DE |
AN3 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A PINCTRL12 |
Video Input 0 Port B Data Enable input. Discrete data valid signal for Port B RGB capture mode or YCbCr capture without embedded syncs ("BT.601" modes). |
VIN[0]A_DE | AT3 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL35 |
Video Input 0 Port A Data Enable input. Discrete data valid signal for Port A RGB capture mode or YCbCr capture without embedded syncs ("BT.601" modes). |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
VOUT[1]_CLK/ VIN[1]A_CLK |
AT7 | I | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL46 |
Video Input 1 Port A Clock input. Input clock for 8-bit or 16-bit Port A video capture. Input data is sampled on the CLK0 edge. |
VOUT[1]_AVID/ VIN[1]B_CLK |
AT4 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL31 |
Video Input 1 Port B Clock input. Input clock for 8-bit Port B video capture. Input data is sampled on the CLK1 edge. This signal is not used in 16-bit capture modes. |
VOUT[1]_HSYNC (silicon revision 1.x) DAC_VOUT[1]_HSYNC (silicon revision 2.x)/ VIN[1]A_D[15] |
AR5 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL21 |
Video Input 1 Port A Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs and D[15:8] are Port B YCbCr data inputs. For VIN[1], only D[15:0] are available. |
VIN[1]A_D[14] | AM3 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL11 |
|
VOUT[1]_C[7]/ VIN[1]A_D[13] |
AD13 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL10 |
|
VOUT[1]_C[6] VIN[1]A_D[12] |
AN8 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL9 |
|
VOUT[1]_C[5]/ VIN[1]A_D[11] |
AP8 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL8 |
|
VOUT[1]_C[4]/ VIN[1]A_D[10] |
AN7 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL7 |
|
VOUT[1]_C[3]/ VIN[1]A_D[9] |
AM8 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL6 |
|
VOUT[1]_C[2]/ VIN[1]A_D[8] |
AK6 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL20 |
|
VOUT[1]_Y_YC[9]/ VIN[1]A_D[7] |
AP6 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL19 |
Video Input 1 Port A Data inputs. For 16-bit capture, D[7:0] are Cb/Cr and [15:8] are Y Port A inputs. For 8-bit capture, D[7:0] are Port A YCbCr data inputs and D[15:8] are Port B YCbCr data inputs. For VIN[1], only D[15:0] are available. |
VOUT[1]_Y_YC[8]/ VIN[1]A_D[6] |
AT6 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL18 |
|
VOUT[1]_Y_YC[7]/ VIN[1]A_D[5] |
AR6 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL17 |
|
VOUT[1]_Y_YC[6]/ VIN[1]A_D[4] |
AC13 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL16 |
|
VOUT[1]_Y_YC[5]/ VIN[1]A_D[3] |
AJ7 | I | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL50 |
|
VOUT[1]_Y_YC[4]/ VIN[1]A_D[2] |
AU6 | I | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL49 |
|
VOUT[1]_Y_YC[3]/ VIN[1]A_D[1] |
AP7 | I | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL48 |
|
VOUT[1]_Y_YC[2]/ VIN[1]A_D[0] |
AU7 | I | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL47 |
|
VOUT[0]_B_CB_C[0]/ VOUT[1]_C[9]/ VIN[1]B_HSYNC_DE |
AR9 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL27 |
Video Input 1 Port B Horizontal Sync or Data Valid signal input. Discrete horizontal synchronization signal for Port B 8-bit YCbCr capture without embedded syncs ("BT.601" modes). Not used in 16-bit YCbCr capture mode. |
VIN[0]A_D[16]/ VIN[1]A_HSYNC/ VOUT[1]_FLD |
AT5 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A, VOUT[1] PINCTRL22 |
Video Input 1 Port A Horizontal Sync input. Discrete horizontal synchronization signal for Port A YCbCr capture modes without embedded syncs ("BT.601" modes). |
VOUT[0]_G_Y_YC[0]/
VOUT[1]_VSYNC (silicon revision 1.x) DAC_VOUT[1]_VSYNC (silicon revision 2.x)/ VIN[1]B_VSYNC |
AP9 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL29 |
Video Input 1 Port B Vertical Sync input. Discrete vertical synchronization signal for Port B 8-bit YCbCr capture without embedded syncs ("BT.601" modes). Not used in 16-bit YCbCr capture mode. |
VIN[0]A_D[17]/ VIN[1]A_VSYNC/ VOUT[1]_VSYNC (silicon revision 1.x) DAC_VOUT[1]_VSYNC (silicon revision 2.x) |
AL5 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A, VOUT[1] PINCTRL23 |
Video Input 1 Port A Vertical Sync input. Discrete vertical synchronization signal for Port A YCbCr capture modes without embedded syncs ("BT.601" modes). |
VIN[0]A_D[19]/ VIN[1]A_DE/ VOUT[1]_C[9] |
AK4 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A, VOUT[1] PINCTRL25 |
Video Input 1 Port A Data Enable input. Discrete data valid signal for Port A YCbCr capture modes without embedded syncs ("BT.601" modes). |
VIN[0]A_D[18]/ VIN[1]A_FLD/ VOUT[1]_C[8] |
AK5 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A, VOUT[1] PINCTRL24 |
Video Input 1Port A Field ID input. Discrete field identification signal for Port A YCbCr capture modes without embedded syncs ("BT.601" modes). |
VOUT[0]_G_Y_YC[1]/ VOUT[1]_FLD/ VIN[1]B_FLD |
AU8 | I | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL30 |
Video Input 1 Port B Field ID input. Discrete field identification signal for Port B 8-bit YCbCr capture without embedded syncs ("BT.601" modes). Not used in 16-bit YCbCr capture mode. |
NOTE
Video output 0 pins AR8 and AL9 and video output 1 pins AT9, AR5, AP9, and AL5 have a different naming convention and functionality for silicon revision 1.x devices and silicon revision 2.x devices. These pins are listed separately in Table 4-28 and Table 4-30.
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
VOUT[0]_CLK | AT14 | O | PULL: IPD / DIS DRIVE: L / H DVDD_3P3 |
- PINCTRL101 |
Video Output 0 Clock output. |
VOUT[0]_G_Y_YC[9] | AR13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL109 |
Video Output 0 Data. These signals represent the 8 MSBs of G/Y/YC video data. For RGB mode they are green data bits, for YUV444 mode they are Y data bits, for Y/C mode they are Y (Luma) data bits and for BT.656 mode they are multiplexed Y/Cb/Cr (Luma and Chroma) data bits. |
VOUT[0]_G_Y_YC[8] | AU13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL108 |
|
VOUT[0]_G_Y_YC[7] | AT13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL107 |
|
VOUT[0]_G_Y_YC[6] | AE14 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL106 |
|
VOUT[0]_G_Y_YC[5] | AM14 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL105 |
|
VOUT[0]_G_Y_YC[4] | AL14 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL104 |
|
VOUT[0]_G_Y_YC[3] | AP14 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL103 |
|
VOUT[0]_G_Y_YC[2] | AE15 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL102 |
|
VOUT[0]_G_Y_YC[1]/ VOUT[1]_FLD/ VIN[1]B_FLD |
AU8 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT,[1] VIN[1]B PINCTRL30 |
Video Output 0 Data. These signals represent the 2 LSBs of G/Y/YC video data for 10-bit, 20-bit and 30-bit video modes (VOUT0 only). For RGB mode they are green data bits, for YUV444 mode they are Y data bits, for Y/C mode they are Y (Luma) data bits and for BT.656 mode they are multiplexed Y/Cb/Cr (Luma and Chroma) data bits. These signals are not used in 8/16/24-bit modes |
VOUT[0]_G_Y_YC[0]/
VOUT[1]_VSYNC (silicon revision 1.x) DAC_VOUT[1]_VSYNC (silicon revision 2.x)/ VIN[1]B_VSYNC |
AP9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1], VIN[1]B PINCTRL29 |
|
VOUT[0]_B_CB_C[9] | AT12 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL117 |
Video Output 0 Data. These signals represent the 8 MSBs of B/CB/C video data. For RGB mode they are blue data bits, for YUV444 mode they are Cb (Chroma) data bits, for Y/C mode they are multiplexed Cb/Cr (Chroma) data bits and for BT.656 mode they are unused |
VOUT[0]_B_CB_C[8] | AH13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL116 |
|
VOUT[0]_B_CB_C[7] | AM13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL115 |
|
VOUT[0]_B_CB_C[6] | AJ13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL114 |
|
VOUT[0]_B_CB_C[5] | AK13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL113 |
|
VOUT[0]_B_CB_C[4] | AN13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL112 |
|
VOUT[0]_B_CB_C[3] | AL13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL111 |
|
VOUT[0]_B_CB_C[2] | AP13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
- PINCTRL110 |
|
VOUT[0]_B_CB_C[1]/
VOUT[1]_HSYNC (silicon revision 1.x) DAC_VOUT[1]_HSYNC (silicon revision 2.x)/ VOUT[1]_AVID |
AT9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL28 |
Video Output 0 Data. These signals represent the 2 LSBs of B/CB/C video data for 20-bit and 30-bit video modes (VOUT[0] only). For RGB mode they are blue data bits, for YUV444 mode they are Cb (Chroma) data bits, for Y/C mode they are multiplexed Cb/Cr (Chroma) data bits and for BT.656 mode they are unused. These signals are not used in 16/24-bit modes. |
VOUT[0]_R_CR[9]/ VOUT[0]_B_CB_C[1]/ VOUT[1]_Y_YC[9] |
AU9 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL125 |
|
VOUT[0]_B_CB_C[0]/ VOUT[1]_C[9]/ VIN[1]B_HSYNC_DE |
AR9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1], VIN[1]B PINCTRL27 |
|
VOUT[0]_R_CR[8]/ VOUT[0]_B_CB_C[0]/ VOUT[1]_Y_YC[8] |
AK10 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL124 |
|
VOUT[0]_R_CR[9]/ VOUT[0]_B_CB_C[1]/ VOUT[1]_Y_YC[9] |
AU9 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL125 |
Video Output 0 Data. These signals represent the 8 MSBs of R/CR video data. For RGB mode they are red data bits, for YUV444 mode they are Cr (Chroma) data bits, for Y/C mode and BT.656 modes they are unused. |
VOUT[0]_R_CR[8]/ VOUT[0]_B_CB_C[0]/ VOUT[1]_Y_YC[8] |
AK10 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL124 |
|
VOUT[0]_R_CR[7]/ VOUT[0]_G_Y_YC[1]/ VOUT[1]_Y_YC[7] |
AL10 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL123 |
|
VOUT[0]_R_CR[6]/ VOUT[0]_G_Y_YC[0]/ VOUT[1]_Y_YC[6] |
AU10 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL122 |
|
VOUT[0]_R_CR[5]/ VOUT[0]_AVID/ VOUT[1]_Y_YC[5] |
AT10 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL121 |
|
VOUT[0]_R_CR[4]/ VOUT[0]_FLD/ VOUT[1]_Y_YC[4] |
AG13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL120 |
|
VOUT[0]_R_CR[3]/ VOUT[0]_VSYNC/ VOUT[1]_Y_YC[3] |
AR11 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL119 |
|
VOUT[0]_R_CR[2]/ VOUT[0]_HSYNC/ VOUT[1]_Y_YC[2] |
AT11 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL118 |
|
VOUT[0]_R_CR[1] | AT8 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL40 |
Video Output 0 Data. These signals represent the 2 LSBs of R/CR video data for 30-bit video modes (VOUT[0] only). For RGB mode they are red data bits, for YUV444 mode they are Cr (Chroma) data bits, for Y/C mode and BT.656 modes they are unused. These signals are not used in 24-bit mode. |
VOUT[0]_R_CR[0]/
VOUT[1]_C[8]/ VOUT[1]_CLK |
AJ11 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[1] PINCTRL26 |
|
VOUT[0]_VSYNC | AN9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL37 |
Video Output 0 Vertical Sync output. This is the discrete vertical synchronization output. This signal is not used for embedded sync modes. |
VOUT[0]_R_CR[3]/ VOUT[0]_VSYNC/ VOUT[1]_Y_YC[3] |
AR11 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL119 |
|
VOUT[0]_HSYNC | AM9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
-
PINCTRL36 |
Video Output 0 Horizontal Sync output. This is the discrete horizontal synchronization output. This signal is not used for embedded sync modes. |
VOUT[0]_R_CR[2]/ VOUT[0]_HSYNC/ VOUT[1]_Y_YC[2] |
AT11 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL118 |
|
VOUT[0]_R_CR[4]/ VOUT[0]_FLD/ VOUT[1]_Y_YC[4] |
AG13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL120 |
Video Output 0 Field ID output. This is the discrete field identification output. This signal is not used for embedded sync modes. |
VOUT[0]_R_CR[5]/ VOUT[0]_AVID/ VOUT[1]_Y_YC[5] |
AT10 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL121 |
Video Output 0 Active Video output. This is the discrete active video indicator output. This signal is not used for embedded sync modes. |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
Silicon Revision 1.x Devices | |||||
HSYNC_VOUT[0]_AVID | AR8 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL39 |
Video Output 0 Active Video output. This is the discrete active video indicator output. This signal is not used for embedded sync modes. |
VSYNC_VOUT[0]_FLD | AL9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL38 |
Video Output 0 Field ID output. This is the discrete field identification output. This signal is not used for embedded sync modes. |
Silicon Revision 2.x Devices | |||||
DAC_HSYNC_ VOUT[0]_AVID |
AR8 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL39 |
Pin supports two functions in silicon revision 2.x devices:
Functionality is set in SPARE_CTRL0 register as defined in Section 9.10. |
DAC_VSYNC_ VOUT[0]_FLD |
AL9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
- PINCTRL38 |
Pin supports two functions in silicon revision 2.x devices:
Functionality is set in SPARE_CTRL0 register as defined in Section 9.10. |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
VOUT[0]_R_CR[0]/ VOUT[1]_C[8]/ VOUT[1]_CLK |
AJ11 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL26 |
Video Output 1 Clock output |
VOUT[1]_CLK/ VIN[1]A_CLK |
AT7 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL46 |
|
VOUT[0]_R_CR[9]/ VOUT[0]_B_CB_C[1]/ VOUT[1]_Y_YC[9] |
AU9 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0] PINCTRL125 |
Video Output 1 Data. These signals represent the 8 bits of Y/YC video data. For Y/C mode they are Y (Luma) data bits and for BT.656 mode they are multiplexed Y/Cb/Cr (Luma and Chroma) data bits. |
VOUT[1]_Y_YC[9]/ VIN[1]A_D[7] |
AP6 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL19 |
|
VOUT[0]_R_CR[8]/ VOUT[0]_B_CB_C[0]/ VOUT[1]_Y_YC[8] |
AK10 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0] PINCTRL124 |
|
VOUT[1]_Y_YC[8]/ VIN[1]A_D[6] |
AT6 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL18 |
|
VOUT[0]_R_CR[7]/ VOUT[0]_G_Y_YC[1]/ VOUT[1]_Y_YC[7] |
AL10 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0] PINCTRL123 |
|
VOUT[1]_Y_YC[7]/ VIN[1]A_D[5] |
AR6 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL17 |
|
VOUT[0]_R_CR[6]/ VOUT[0]_G_Y_YC[0]/ VOUT[1]_Y_YC[6] |
AU10 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0] PINCTRL122 |
|
VOUT[1]_Y_YC[6]/ VIN[1]A_D[4] |
AC13 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL16 |
|
VOUT[0]_R_CR[5]/ VOUT[0]_AVID/ VOUT[1]_Y_YC[5] |
AT10 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0] PINCTRL121 |
Video Output 1 Data. These signals represent the 8 bits of Y/YC video data. For Y/C mode they are Y (Luma) data bits and for BT.656 mode they are multiplexed Y/Cb/Cr (Luma and Chroma) data bits. |
VOUT[1]_Y_YC[5]/ VIN[1]A_D[3] |
AJ7 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL50 |
|
VOUT[0]_R_CR[4]/ VOUT[0]_FLD/ VOUT[1]_Y_YC[4] |
AG13 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0] PINCTRL120 |
|
VOUT[1]_Y_YC[4]/ VIN[1]A_D[2] |
AU6 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL49 |
|
VOUT[0]_R_CR[3]/ VOUT[0]_VSYNC / VOUT[1]_Y_YC[3] |
AR11 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0] PINCTRL119 |
|
VOUT[1]_Y_YC[3]
VIN[1]A_D[1] |
AP7 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL48 |
|
VOUT[0]_R_CR[2]/ VOUT[0]_HSYNC/ VOUT[1]_Y_YC[2] |
AT11 | O | PULL: IPD / DIS DRIVE: L / L DVDD_3P3 |
VOUT[0] PINCTRL118 |
|
VOUT[1]_Y_YC[2]/ VIN[1]A_D[0] |
AU7 | O | PULL: IPD / DIS DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL47 |
|
VOUT[0]_B_CB_C[0]/ VOUT[1]_C[9]/ VIN[1]B_HSYNC_DE |
AR9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VIN[1]B PINCTRL27 |
Video Output 1 Data. These signals represent the 8 bits of C video data. For Y/C mode they are multiplexed Cb/Cr (Chroma) data bits, and for BT.656 mode they are unused. |
VIN[0]A_D[19]/ VIN[1]A_DE/ VOUT[1]_C[9] |
AK4 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A, VIN[1]A | |
VIN[0]A_D[18]/ VIN[1]A_FLD/ VOUT[1]_C[8] |
AK5 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A, VIN[1]A PINCTRL24 |
|
VOUT[0]_R_CR[0]/ VOUT[1]_C[8]/ VOUT[1]_CLK |
AJ11 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL26 |
|
VOUT[1]_C[7]/ VIN[1]A_D[13] |
AD13 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL10 |
|
VOUT[1]_C[6]/ VIN[1]A_D[12] |
AN8 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL9 |
|
VOUT[1]_C[5]/ VIN[1]A_D[11] |
AP8 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL8 |
|
VOUT[1]_C[4]/ VIN[1]A_D[10] |
AN7 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL7 |
|
VOUT[1]_C[3]/
VIN[1]A_D[9]/ |
AM8 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL6 |
|
VOUT[1]_C[2]/ VIN[1]A_D[8] |
AK6 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL20 |
|
VIN[0]A_D[16]/ VIN[1]A_HSYNC/ VOUT[1]_FLD |
AT5 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A, VIN[1]A PINCTRL22 |
Video Output 1 Field ID output. This is the discrete field identification output. This signal is not used for embedded sync modes. |
VOUT[0]_G_Y_YC[1]/ VOUT[1]_FLD/ VIN[1]B_FLD |
AU8 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VIN[1]B PINCTRL30 |
|
VOUT[0]_B_CB_C[1]/
VOUT[1]_HSYNC (silicon revision 1.x) DAC_VOUT[1]_HSYNC (silicon revision 2.x)/ VOUT[1]_AVID |
AT9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL28 |
Video Output 1 Active Video output. This is the discrete active video indicator output. This signal is not used for embedded sync modes. |
VOUT[1]_AVID/ VIN[1]B_CLK |
AT4 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]B PINCTRL31 |
SIGNAL | TYPE(1) | OTHER(2)(3) | MUXED | DESCRIPTION | |
---|---|---|---|---|---|
NAME | NO. | ||||
Silicon Revision 1.x Devices | |||||
VOUT[0]_B_CB_C[1]/ VOUT[1]_HSYNC/ VOUT[1]_AVID |
AT9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL28 |
Video Output 1 Horizontal Sync output. This is the discrete horizontal synchronization output. This signal is not used for embedded sync modes. |
VOUT[1]_HSYNC/ VIN[1]A_D[15] |
AR5 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL21 |
|
VOUT[0]_G_Y_YC[0]/ VOUT[1]_VSYNC/ VIN[1]B_VSYNC |
AP9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VIN[1]B PINCTRL29 |
Video Output 1 Vertical Sync output. This is the discrete vertical synchronization output. This signal is not used for embedded sync modes. |
VIN[0]A_D[17]/ VIN[1]A_VSYNC/ VOUT[1]_VSYNC |
AL5 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A, VIN[1]A PINCTRL23 |
|
Silicon Revision 2.x Devices | |||||
VOUT[0]_B_CB_C[1]/ DAC_VOUT[1]_HSYNC/ VOUT[1]_AVID |
AT9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VOUT[1] PINCTRL28 |
Pin supports two functions in silicon revision 2.x devices:
Functionality is set in SPARE_CTRL0 register as defined in Section 9.10. |
DAC_VOUT[1]_HSYNC/ VIN[1]A_D[15] |
AR5 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[1]A PINCTRL21 |
|
VOUT[0]_G_Y_YC[0]/ DAC_VOUT[1]_VSYNC/ VIN[1]B_VSYNC |
AP9 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VOUT[0], VIN[1]B PINCTRL29 |
Pin supports two functions in silicon revision 2.x devices:
Functionality is set in SPARE_CTRL0 register as defined in Section 9.10. |
VIN[0]A_D[17]/ VIN[1]A_VSYNC/ DAC_VOUT[1]_VSYNC |
AL5 | O | PULL: IPD / IPD DRIVE: Z / Z DVDD_3P3 |
VIN[0]A, VIN[1]A PINCTRL23 |
SIGNAL | TYPE(1) | OTHER | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
When a specific Video DAC output [IOUTA - IOUTG] is powered down, the corresponding Analog Video Output terminal functions should be left unconnected. | ||||
IOUTA | AT21 | O | - | Video DAC A output. Analog HD Video DAC (G/Y) |
IOUTB | AR21 | O | - | Video DAC B output. Analog HD Video DAC (B/Pb) |
IOUTC | AP21 | O | - | Video DAC C output. Analog HD Video DAC (R/Pr) |
IOUTD | AR20 | O | - | Video DAC D output. Analog SD Video DAC |
IOUTE | AT19 | O | - | Video DAC E output. Analog SD Video DAC |
IOUTF | AT20 | O | - | Video DAC F output. Analog SD Video DAC |
IOUTG | AU20 | O | - | Video DAC G output. Analog SD Video DAC |
DAC_VOUT[1]_HSYNC, DAC_HSYNC_ VOUT[0]_AVID |
AR5, AT9, AR8 | O | - | Analog HD Video DAC Discrete HSYNC Output |
DAC_VOUT[1]_VSYNC, DAC_VSYNC_ VOUT[0]_FLD |
AL5, AP9, AL9 | O | - | Analog HD Video DAC Discrete VSYNC Output |
VDAC_VREF | AH19 | I | - | Video DAC reference voltage (0.5 V). When the video DACs are powered down, this pin should be left unconnected. |
VDAC_RBIAS_HD | AE22 | IO | - | Video DAC HD current bias connection. This pin must be connected via an external 1.2-kΩ resistor to VSSA_HD. When the HD DACs are powered down, this pin should be left unconnected. |
VDAC_RBIAS_SD | AP19 | IO | - | Video DAC SD current bias connection. This pin must be connected via an external 1.2-kΩ resistor to VSSA_SD. When the SD DACs are powered down, this pin should be left unconnected. |
SIGNAL | TYPE(1) | OTHER(2)(3) | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
RSV1 | AB36 | O | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV2 | P25 | O | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV3 | N19 | O | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV4 | N20 | O | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV5 | T28 | IO | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV6 | T27 | IO | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV7 | AE23 | O | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV8 | D24 | O | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV9 | AU37 | I | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV10 | N28 | IO | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV11 | N29 | IO | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV12 | AG25 | S | - | Reserved. For proper device operation, this pin must be tied directly to the 1.8-V supply. |
RSV13 | AG24 | S | - | Reserved. For proper device operation, this pin must be tied directly to the 1.8-V supply. |
RSV14 | AH25 | S | - | Reserved. For proper device operation, this pin must be tied directly to the 1.8-V supply. |
RSV15 | AH24 | S | - | Reserved. For proper device operation, this pin must be tied directly to the 1.8-V supply. |
RSV16 | R34 | I | - | Reserved. For proper device operation, this pin must be tied directly to VSS. |
RSV17 | P34 | O | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV18 | P33 | S | - | Reserved. For proper device operation, this pin must be tied directly to the 1.8-V supply. |
RSV19 | P32 | GND | - | Reserved. For proper device operation, this pin must be tied directly to VSS. |
RSV20 | D14 | O | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV21 | AN18 | O | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV22 | AN19 | O | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV23 | AP2 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV24 | AU3 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV25 | AN2 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV26 | AT1 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV27 | AR1 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV28 | AP1 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV29 | AM2 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV30 | AL2 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV31 | AK1 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV32 | AL1 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV33 | AM29 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV34 | AL28 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV35 | AL29 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV36 | AN29 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV37 | AP29 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV38 | AR29 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV39 | AT29 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV40 | AT28 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV41 | AU21 | O | - | Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV42 | AJ1 | IO | IPU DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV43 | AK2 | IO | IPU DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV44 | AH8 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV45 | AJ2 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV46 | AK3 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV47 | AJ3 | O | DIS DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV48 | AJ4 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV49 | AJ5 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV50 | AJ6 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV51 | AB13 | I | IPD DVDD_3P3 |
Reserved. (Leave unconnected, do not connect to power or ground.) |
RSV52 | AE21 | S | - | Reserved. For proper device operation, this pin should be connected to a 1.0-V power supply. |
RSV53 | AG22 | S | - | Reserved. For proper device operation, this pin should be connected to a 1.8-V power supply. |
RSV54 | AG23 | S | - | Reserved. For proper device operation, this pin should be connected to a 1.8-V power supply. |
RSV55 | AH23 | S | - | Reserved. For proper device operation, this pin should be connected to a 1.8-V power supply. |
RSV56 | AJ23 | S | - | Reserved. For proper device operation, this pin should be connected to a 1.8-V power supply. |
RSV57 | AK22 | GND | - | Reserved. For proper device operation, this pin must be tied directly to VSS. |
RSV58 | AL22 | GND | - | Reserved. For proper device operation, this pin must be tied directly to VSS. |
RSV59 | AM22 | GND | - | Reserved. For proper device operation, this pin must be tied directly to VSS. |
RSV60 | AM21 | GND | - | Reserved. For proper device operation, this pin must be tied directly to VSS. |
RSV61 | AN21 | GND | - | Reserved. For proper device operation, this pin must be tied directly to VSS. |
SIGNAL | TYPE(1) | OTHER | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
VREFSSTL_DDR[0] | A17 | S | - | Reference Power Supply DDR[0]:
|
VREFSSTL_DDR[1] | A21 | S | - | Reference Power Supply DDR[1]
|
CVDD | AD22, AD21, AD20, AD19, AD18, AD17, AD16, AC22, AC21, AC20, AC19, AC18, AC17, AC16, AB24, AB23, AB22, AB21, AB20, AB19, AB18, AB17, AB16, AB15, AB14, T24, T23, T22, T21, T20, T19, T18, T17, T16, T15, T14, R22, R21, R20, R19, R18, R17, R16, P22, P21, P20, P19, P18, P17, P16 |
S | - | Variable Core Voltage Supply for the Always ON Domain |
CVDDC | AE25, AE13, AD24, AD23, AD15, AD14, AC24, AC23, AC15, AC14, R24, R23, R15, R14, P24, P23, P15, P14, N25, N13 |
S | - | 1.0-V Constant Power Supply for Memories and PLLs |
VDD_USB_0P9 | N27 | S | - | 0.9-V Power Supply for USB PHYs. Note: If the USB is not used, for proper device operation, this pin must be connected to a power supply (0.9 V or CVDDC). |
VDDT_SATA | Y34, Y33, V34, V32 | S | - | 1.0-V Power Supply for SATA Termination and Analog Front End Note: If the SATA is not used, for proper device operation, these pins must be connected to a 1.0-V power supply. |
VDDT_PCIE | Y30, Y28, AB32, AB29, AB27 |
S | - | 1.0-V Power Supply for PCIe Termination and Analog Front End Note: If the PCIe is not used, these pins should be connected to a 1.0-V power supply. |
VDDA_PLL | B18, A18 | S | - | 1.5-V Analog Power Supply for PLLs |
VDDA_HDMI | AR27, AP24, AP23, AN24, AN23 |
S | - | 1.0-V Analog Power Supply for HDMI Note: If the HDMI is not used, these pins should be connected to a 1.0-V power supply. |
VDDA_HD_1P0 | AG21 | S | - | 1.0-V Analog Power Supply for VDAC HD DAC Note: If the HD DAC is not used, this pin should be connected to a 1.0-V power supply. |
VDDA_SD_1P0 | AG20 | S | - | 1.0-V Analog Power Supply for VDAC SD DAC Note: If the SD DAC is not used, this pin should be connected to a 1.0-V power supply. |
VDDR_SATA | V25, U25 | S | - | 1.5-V Regulator Power Supply for SATA Note: If the SATA is not used, for proper device operation, these pins must be connected to a 1.5-V power supply. |
VDDR_PCIE | Y25, W25 | S | - | 1.5-V Regulator Power Supply for PCIe Note: If the PCIe is not used, for proper device operation, these pins must be connected to a 1.5-V power supply. |
DVDD_DDR[0] | L19, L18, L17, L16, L15, L14, K19, K18, K17, K16, K15, K14, J18, J17, J16, J15, J14, E11, A11, E1, A2 |
S | - | Power Supply for DDR[0] IOs:
|
DVDD_DDR[1] | L24, L23, L22, L21, L20, K24, K23, K22, K21, K20, J24, J23, J22, J21, J20, J19, E27, D37, A36, A27 |
S | - | 1.5-V Power Supply for DDR[1] IOs:
|
DEVOSC_DVDD18 | E19 | S | - | 1.8-V Power Supply for Device Oscillator Note: If the oscillator is not used, this pin should be connected to the 1.8-V power supply (DVDD1P8). |
VDD_USB0_1P8 | R25 | S | - | 1.8-V Power Supply for USB0 Note: If the USB is not used, for proper device operation, this pin must be connected to a 1.8-V power supply, or when the USB PHY is not used, this pin can be optionally connected to CVDDC. |
VDD_USB1_1P8 | T25 | S | - | 1.8-V Power Supply for USB1 Note: If the USB is not used, for proper device operation, this pin must be connected to a 1.8-V power supply, or when the USB PHY is not used, this pin can be optionally connected to CVDDC. |
DVDD1P8 | AJ20, AJ24 | S | - | 1.8-V Power Supply |
VDDA_REF_1P8 | AT22 | S | - | 1.8-V Reference Power Supply for VDAC Note: If the VDAC is not used, these pins should be connected to a 1.8-V power supply. |
VDDA_HD_1P8 | AJ22, AH22 | S | - | 1.8-V Analog Power Supply for VDAC HD DAC Note: If the HD DAC is not used, these pins should be connected to a 1.8-V power supply. |
VDDA_SD_1P8 | AJ21, AH21, AH20 | S | - | 1.8-V Analog Power Supply for VDAC SD DAC Note: If the SD DAC is not used, these pins should be connected to a 1.8-V power supply. |
DVDD_3P3 | AU29, AU11, AU2, AN37, AN27, AN11, AN1, AJ17, AJ16, AJ15, AJ14, AH17, AH16, AH15, AH14, AG33, AG17, AG16, AG15, AG14, AE29, AE28, AE27, AD29, AD28, AD27, AD11, AD10, AD9, AC29, AC28, AC27, AC11, AC10, AC9, AB11, AB10, AB9, AA11, AA10, AA9, AA1, Y9, U11, U10, U9, T11, T10, T9, R28, R27, R11, R10, R9, P30, P29, P28, P27, P11, P10, P9, P8, L35, L30, L5, L1 |
S | - | 3.3-V Power Supply |
VDD_USB0_3P3 | T29, R29 | S | - | 3.3-V Power Supply for USB0 |
VDD_USB1_3P3 | T30, R30 | S | - | 3.3-V Power Supply for USB1 |
SIGNAL | TYPE(1) | OTHER | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
VSS | AU28, AU23, AU12, AU1, AT23, AR25, AR24, AR23, AR15, AP37, AP15, AN15, AN14, AM31, AM25, AM24, AM23, AM19, AM18, AM17, AM16, AM15, AM7, AM1, AL32, AL31, AL24, AL23, AL19, AL18, AL17, AL16, AL15, AL7, AL6, AK27, AK24, AK23, AK19, AK18, AK17, AK16, AK15, AK11, AJ25, AJ18, AG30, AG26, AG12, AG8, AG5, AF27, AF11, AE20, AE19, AE18, AE17, AD34, AD33, AD32, AD31, AD30, AD7, AD6, AD5, AC34, AC33, AC32, AC31, AC30, AC8, AC7, AC6, AC4, AC3, AB37, AB35, AB8, AB7, AB6, AB1, AA24, AA23, AA22, AA21, AA20, AA19, AA18, AA17, AA16, AA15, AA14, AA13, AA8, AA7, AA6, AA5, Y37, Y36, Y32, Y31, Y24, Y23, Y22, Y21, Y20, Y19, Y18, Y17, Y16, Y15, Y14, Y13, Y8, Y7, Y6, Y5, Y4, W24, W23, W22, W21, W20, W19, W18, W17, W16 | GND | - | Ground (GND) |
VSS | W15, W14, W13, W9, W8, W7, W6, V28, V27, V24, V23, V22, V21, V20, V19, V18, V17, V16, V15, V14, V13, V9, V8, V7, V6, V5, V4, U24, U23, U22, U21, U20, U18, U17, U16, U15, U14, U13, U8, U7, U6, U5, T35, T34, T33, T8, T7, T6, R33, R32, R31, R8, R7, R6, R4, R3, P31, P7, P6, P5, P4, N18, M27, M11, L33, L26, L12, L8, K37, K1, H27, H24, H23, H22, H21, H20, H19, H18, H17, H16, H15, H14, H11, G32, G31, G24, G23, G22, G21, G20, G18, G17, G16, G15, G14, G7, G6, F31, F24, F23, F22, F21, F17, F16, F15, F14, F7, E37, E24, E14, D1, C23, C21, C17, C15, A37, A28, A10, A1 | GND | - | Ground (GND) |
VSSA_PLL | U19, B20, A20 | GND | - | Analog GND for PLLs |
VSSA_HD | AK21, AK20, AL21 | GND | - | Analog GND for VDAC HD DAC |
VSSA_SD | AU19, AM20, AN20, AL20 | GND | - | Analog GND for VDAC SD DAC |
VSSA_REF_1P8 | AU22 | GND | - | Reference GND for VDAC (1.8 V) |
DEVOSC_VSS | B19 | GND | - | Ground for Device Oscillator |