JAJSGF4F November 2012 – September 2021 TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28052F , TMS320F28052M , TMS320F28053 , TMS320F28054 , TMS320F28054F , TMS320F28054M , TMS320F28055
PRODUCTION DATA
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. Table 8-13 defines the registers.
NAME | ADDRESS RANGE | SIZE (×16) | DESCRIPTION | EALLOW PROTECTED | ||
---|---|---|---|---|---|---|
DEVICECNF | 0x0880 to 0x0881 |
2 | Device Configuration Register | Yes | ||
PARTID | 0x0882 | 1 | PARTID Register | TMS320F28055 | 0x0105 | No |
TMS320F28054 | 0x0104 | |||||
TMS320F28054M | 0x0184 | |||||
TMS320F28054F | 0x0144 | |||||
TMS320F28053 | 0x0103 | |||||
TMS320F28052 | 0x0102 | |||||
TMS320F28052M | 0x0182 | |||||
TMS320F28052F | 0x0142 | |||||
TMS320F28051 | 0x0101 | |||||
TMS320F28050 | 0x0100 | |||||
REVID(1) | 0x0883 | 1 | Revision ID Register | 0x0000 - Silicon Rev. 0 - TMX | No | |
0x0000 - Silicon Rev. A - TMS | ||||||
DC1 | 0x0886 to 0x0887 |
2 | Device
Capability Register 1. The Device Capability Register is predefined by the part and can be used to verify features. If any bit is 0 in this register, the module is not present. See Table 8-14. |
Yes | ||
DC2 | 0x0888 to 0x0889 |
2 | Device
Capability Register 2. The Device Capability Register is predefined by the part and can be used to verify features. If any bit is 0 in this register, the module is not present. See Table 8-15. |
Yes | ||
DC3 | 0x088A to 0x088B |
2 | Device
Capability Register 3. The Device Capability Register is predefined by the part and can be used to verify features. If any bit is 0 in this register, the module is not present. See Table 8-16. |
Yes |
BIT(1) | FIELD | TYPE | DESCRIPTION |
---|---|---|---|
31:30 | RSVD | R = 0 | Reserved |
29:22 | PARTNO | R | These 8 bits set the PARTNO field value in the PARTID register for the device. They are readable in the PARTID[7:0] register bits. |
21:14 | RSVD | R = 0 | Reserved |
13 | CLA | R | CLA is present when this bit is set. |
12:7 | RSVD | R = 0 | Reserved |
6 | L3 | R | L3 is present when this bit is set. |
5 | L2 | R | L2 is present when this bit is set. |
4 | L1 | R | L1 is present when this bit is set. |
3 | L0 | R | L0 is present when this bit is set. |
2 | RSVD | R = 0 | Reserved |
1:0 | RSVD | R = 0 | Reserved |
BIT(1) | FIELD | TYPE | DESCRIPTION |
---|---|---|---|
31:28 | RSVD | R = 0 | Reserved |
27 | eCAN-A | R | eCAN-A is present when this bit is set. |
26:17 | RSVD | R = 0 | Reserved |
16 | EQEP-1 | R | eQEP-1 is present when this bit is set. |
15:13 | RSVD | R = 0 | Reserved |
12 | ECAP-1 | R | eCAP-1 is present when this bit is set. |
11:9 | RSVD | R = 0 | Reserved |
8 | I2C-A | R | I2C-A is present when this bit is set. |
7:5 | RSVD | R = 0 | Reserved |
4 | SPI-A | R | SPI-A is present when this bit is set. |
3 | RSVD | R = 0 | Reserved |
2 | SCI-C | R | SCI-C is present when this bit is set. |
1 | SCI-B | R | SCI-B is present when this bit is set. |
0 | SCI-A | R | SCI-A is present when this bit is set. |
BIT(1) | FIELD | TYPE | DESCRIPTION |
---|---|---|---|
31:20 | RSVD | R = 0 | Reserved |
19 | CTRIPFIL7 | R | CTRIPFIL7(B7) is present when this bit is set. |
18 | CTRIPFIL6 | R | CTRIPFIL6(B6) is present when this bit is set. |
17 | CTRIPFIL5 | R | CTRIPFIL5(B4) is present when this bit is set. |
16 | CTRIPFIL4 | R | CTRIPFIL4(A6) is present when this bit is set. |
15 | CTRIPFIL3 | R | CTRIPFIL3(B1) is present when this bit is set. |
14 | CTRIPFIL2 | R | CTRIPFIL2(A3) is present when this bit is set. |
13 | CTRIPFIL1 | R | CTRIPFIL1(A1) is present when this bit is set. |
12:8 | RSVD | R = 0 | Reserved |
7 | RSVD | R = 0 | Reserved |
6 | ePWM7 | R | ePWM7 is present when this bit is set. |
5 | ePWM6 | R | ePWM6 is present when this bit is set. |
4 | ePWM5 | R | ePWM5 is present when this bit is set. |
3 | ePWM4 | R | ePWM4 is present when this bit is set. |
2 | ePWM3 | R | ePWM3 is present when this bit is set. |
1 | ePWM2 | R | ePWM2 is present when this bit is set. |
0 | ePWM1 | R | ePWM1 is present when this bit is set. |