JAJSGF4F November 2012 – September 2021 TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28052F , TMS320F28052M , TMS320F28053 , TMS320F28054 , TMS320F28054F , TMS320F28054M , TMS320F28055
PRODUCTION DATA
The device supports 42 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 8-51 provides the GPIO register mapping.
NAME | ADDRESS | SIZE (×16) | DESCRIPTION |
---|---|---|---|
GPIO CONTROL REGISTERS (EALLOW PROTECTED) | |||
GPACTRL | 0x6F80 | 2 | GPIO A Control register (GPIO0 to 31) |
GPAQSEL1 | 0x6F82 | 2 | GPIO A Qualifier Select 1 register (GPIO0 to 15) |
GPAQSEL2 | 0x6F84 | 2 | GPIO A Qualifier Select 2 register (GPIO16 to 31) |
GPAMUX1 | 0x6F86 | 2 | GPIO A MUX 1 register (GPIO0 to 15) |
GPAMUX2 | 0x6F88 | 2 | GPIO A MUX 2 register (GPIO16 to 31) |
GPADIR | 0x6F8A | 2 | GPIO A Direction register (GPIO0 to 31) |
GPAPUD | 0x6F8C | 2 | GPIO A Pull Up Disable register (GPIO0 to 31) |
GPBCTRL | 0x6F90 | 2 | GPIO B Control register (GPIO32 to 44) |
GPBQSEL1 | 0x6F92 | 2 | GPIO B Qualifier Select 1 register (GPIO32 to 44) |
GPBMUX1 | 0x6F96 | 2 | GPIO B MUX 1 register (GPIO32 to 44) |
GPBDIR | 0x6F9A | 2 | GPIO B Direction register (GPIO32 to 44) |
GPBPUD | 0x6F9C | 2 | GPIO B Pull Up Disable register (GPIO32 to 44) |
Reserved | 0x6FB6 | 2 | Reserved |
Reserved | 0x6FBA | 2 | Reserved |
GPIO DATA REGISTERS (NOT EALLOW PROTECTED) | |||
GPADAT | 0x6FC0 | 2 | GPIO A Data register (GPIO0 to 31) |
GPASET | 0x6FC2 | 2 | GPIO A Data Set register (GPIO0 to 31) |
GPACLEAR | 0x6FC4 | 2 | GPIO A Data Clear register (GPIO0 to 31) |
GPATOGGLE | 0x6FC6 | 2 | GPIO A Data Toggle register (GPIO0 to 31) |
GPBDAT | 0x6FC8 | 2 | GPIO B Data register (GPIO32 to 44) |
GPBSET | 0x6FCA | 2 | GPIO B Data Set register (GPIO32 to 44) |
GPBCLEAR | 0x6FCC | 2 | GPIO B Data Clear register (GPIO32 to 44) |
GPBTOGGLE | 0x6FCE | 2 | GPIO B Data Toggle register (GPIO32 to 44) |
Reserved | 0x6FD8 | 2 | Reserved |
Reserved | 0x6FDA | 2 | Reserved |
Reserved | 0x6FDC | 2 | Reserved |
Reserved | 0x6FDE | 2 | Reserved |
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED) | |||
GPIOXINT1SEL | 0x6FE0 | 1 | XINT1 GPIO Input Select register (GPIO0 to 31) |
GPIOXINT2SEL | 0x6FE1 | 1 | XINT2 GPIO Input Select register (GPIO0 to 31) |
GPIOXINT3SEL | 0x6FE2 | 1 | XINT3 GPIO Input Select register (GPIO0 to 31) |
GPIOLPMSEL | 0x6FE8 | 2 | LPM GPIO Select register (GPIO0 to 31) |
There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn registers occurs to when the action is valid.