JAJSGF4F November   2012  – September 2021 TMS320F28050 , TMS320F28051 , TMS320F28052 , TMS320F28052F , TMS320F28052M , TMS320F28053 , TMS320F28054 , TMS320F28054F , TMS320F28054M , TMS320F28055

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1. 3.1 機能ブロック図
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT
      2. 7.5.2 Reducing Current Consumption
      3. 7.5.3 Current Consumption Graphs (VREG Enabled)
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for PN Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  JTAG Debug Probe Connection Without Signal Buffering for the MCU
    10. 7.10 Parameter Information
      1. 7.10.1 Timing Parameter Symbology
      2. 7.10.2 General Notes on Timing Parameters
    11. 7.11 Test Load Circuit
    12. 7.12 Power Sequencing
      1. 7.12.1 Reset ( XRS) Timing Requirements
      2. 7.12.2 Reset ( XRS) Switching Characteristics
    13. 7.13 Clock Specifications
      1. 7.13.1 Device Clock Table
        1. 7.13.1.1 2805x Clock Table and Nomenclature (60-MHz Devices)
        2. 7.13.1.2 Device Clocking Requirements/Characteristics
        3. 7.13.1.3 Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics
      2. 7.13.2 Clock Requirements and Characteristics
        1. 7.13.2.1 XCLKIN Timing Requirements - PLL Enabled
        2. 7.13.2.2 XCLKIN Timing Requirements - PLL Disabled
        3. 7.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 7.14 Flash Timing
      1. 7.14.1 Flash/OTP Endurance for T Temperature Material
      2. 7.14.2 Flash/OTP Endurance for S Temperature Material
      3. 7.14.3 Flash/OTP Endurance for Q Temperature Material
      4. 7.14.4 Flash Parameters at 60-MHz SYSCLKOUT
      5. 7.14.5 Flash/OTP Access Timing
      6. 7.14.6 Flash Data Retention Duration
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1  CPU
      2. 8.1.2  Control Law Accelerator
      3. 8.1.3  Memory Bus (Harvard Bus Architecture)
      4. 8.1.4  Peripheral Bus
      5. 8.1.5  Real-Time JTAG and Analysis
      6. 8.1.6  Flash
      7. 8.1.7  M0, M1 SARAMs
      8. 8.1.8  L0 SARAM, and L1, L2, and L3 DPSARAMs
      9. 8.1.9  Boot ROM
        1. 8.1.9.1 Emulation Boot
        2. 8.1.9.2 GetMode
        3. 8.1.9.3 Peripheral Pins Used by the Bootloader
      10. 8.1.10 Security
      11. 8.1.11 Peripheral Interrupt Expansion Block
      12. 8.1.12 External Interrupts (XINT1 to XINT3)
      13. 8.1.13 Internal Zero-Pin Oscillators, Oscillator, and PLL
      14. 8.1.14 Watchdog
      15. 8.1.15 Peripheral Clocking
      16. 8.1.16 Low-power Modes
      17. 8.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 8.1.18 General-Purpose Input/Output Multiplexer
      19. 8.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 8.1.20 Control Peripherals
      21. 8.1.21 Serial Port Peripherals
    2. 8.2 Memory Maps
    3. 8.3 Register Map
    4. 8.4 Device Emulation Registers
    5. 8.5 VREG, BOR, POR
      1. 8.5.1 On-chip VREG
        1. 8.5.1.1 Using the On-chip VREG
        2. 8.5.1.2 Disabling the On-chip VREG
      2. 8.5.2 On-chip Power-On Reset and Brownout Reset Circuit
    6. 8.6 System Control
      1. 8.6.1 Internal Zero-Pin Oscillators
      2. 8.6.2 Crystal Oscillator Option
      3. 8.6.3 PLL-Based Clock Module
      4. 8.6.4 Loss of Input Clock (NMI-watchdog Function)
      5. 8.6.5 CPU-watchdog Module
    7. 8.7 Low-power Modes Block
    8. 8.8 Interrupts
      1. 8.8.1 External Interrupts
        1. 8.8.1.1 External Interrupt Electrical Data/Timing
          1. 8.8.1.1.1 External Interrupt Timing Requirements
          2. 8.8.1.1.2 External Interrupt Switching Characteristics
    9. 8.9 Peripherals
      1. 8.9.1  Control Law Accelerator
        1. 8.9.1.1 CLA Device-Specific Information
        2. 8.9.1.2 CLA Register Descriptions
      2. 8.9.2  Analog Block
        1. 8.9.2.1 Analog-to-Digital Converter
          1. 8.9.2.1.1 ADC Device-Specific Information
          2. 8.9.2.1.2 ADC Electrical Data/Timing
            1. 8.9.2.1.2.1 ADC Electrical Characteristics
            2. 8.9.2.1.2.2 ADC Power Modes
            3. 8.9.2.1.2.3 External ADC Start-of-Conversion Electrical Data/Timing
              1. 8.9.2.1.2.3.1 External ADC Start-of-Conversion Switching Characteristics
            4. 8.9.2.1.2.4 Internal Temperature Sensor
              1. 8.9.2.1.2.4.1 Temperature Sensor Coefficient
            5. 8.9.2.1.2.5 ADC Power-Up Control Bit Timing
              1. 8.9.2.1.2.5.1 ADC Power-Up Delays
            6. 8.9.2.1.2.6 ADC Sequential and Simultaneous Timings
        2. 8.9.2.2 Analog Front End
          1. 8.9.2.2.1 AFE Device-Specific Information
          2. 8.9.2.2.2 AFE Register Descriptions
          3. 8.9.2.2.3 PGA Electrical Data/Timing
          4. 8.9.2.2.4 Comparator Block Electrical Data/Timing
            1. 8.9.2.2.4.1 Electrical Characteristics of the Comparator/DAC
          5. 8.9.2.2.5 VREFOUT Buffered DAC Electrical Data
            1. 8.9.2.2.5.1 Electrical Characteristics of VREFOUT Buffered DAC
      3. 8.9.3  Detailed Descriptions
      4. 8.9.4  Serial Peripheral Interface
        1. 8.9.4.1 SPI Device-Specific Information
        2. 8.9.4.2 SPI Register Descriptions
        3. 8.9.4.3 SPI Master Mode Electrical Data/Timing
          1. 8.9.4.3.1 SPI Master Mode External Timing (Clock Phase = 0)
          2. 8.9.4.3.2 SPI Master Mode External Timing (Clock Phase = 1)
        4. 8.9.4.4 SPI Slave Mode Electrical Data/Timing
          1. 8.9.4.4.1 SPI Slave Mode External Timing (Clock Phase = 0)
          2. 8.9.4.4.2 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 8.9.5  Serial Communications Interface
        1. 8.9.5.1 SCI Device-Specific Information
        2. 8.9.5.2 SCI Register Descriptions
      6. 8.9.6  Enhanced Controller Area Network
        1. 8.9.6.1 eCAN Device-Specific Information
        2. 8.9.6.2 eCAN Register Descriptions
      7. 8.9.7  Inter-Integrated Circuit
        1. 8.9.7.1 I2C Device-Specific Information
        2. 8.9.7.2 I2C Register Descriptions
        3. 8.9.7.3 I2C Electrical Data/Timing
          1. 8.9.7.3.1 I2C Timing Requirements
          2. 8.9.7.3.2 I2C Switching Characteristics
      8. 8.9.8  Enhanced Pulse Width Modulator
        1. 8.9.8.1 ePWM Device-Specific Information
        2. 8.9.8.2 ePWM Register Descriptions
        3. 8.9.8.3 ePWM Electrical Data/Timing
          1. 8.9.8.3.1 ePWM Timing Requirements
          2. 8.9.8.3.2 ePWM Switching Characteristics
          3. 8.9.8.3.3 Trip-Zone Input Timing
            1. 8.9.8.3.3.1 Trip-Zone Input Timing Requirements
      9. 8.9.9  Enhanced Capture Module
        1. 8.9.9.1 eCAP Module Device-Specific Information
        2. 8.9.9.2 eCAP Module Register Descriptions
        3. 8.9.9.3 eCAP Module Electrical Data/Timing
          1. 8.9.9.3.1 eCAP Timing Requirement
          2. 8.9.9.3.2 eCAP Switching Characteristics
      10. 8.9.10 Enhanced Quadrature Encoder Pulse
        1. 8.9.10.1 eQEP Device-Specific Information
        2. 8.9.10.2 eQEP Register Descriptions
        3. 8.9.10.3 eQEP Electrical Data/Timing
          1. 8.9.10.3.1 eQEP Timing Requirements
          2. 8.9.10.3.2 eQEP Switching Characteristics
      11. 8.9.11 JTAG Port
        1. 8.9.11.1 JTAG Port Device-Specific Information
      12. 8.9.12 General-Purpose Input/Output
        1. 8.9.12.1 GPIO Device-Specific Information
        2. 8.9.12.2 GPIO Register Descriptions
        3. 8.9.12.3 GPIO Electrical Data/Timing
          1. 8.9.12.3.1 GPIO - Output Timing
            1. 8.9.12.3.1.1 General-Purpose Output Switching Characteristics
          2. 8.9.12.3.2 GPIO - Input Timing
            1. 8.9.12.3.2.1 General-Purpose Input Timing Requirements
          3. 8.9.12.3.3 Sampling Window Width for Input Signals
          4. 8.9.12.3.4 Low-Power Mode Wakeup Timing
            1. 8.9.12.3.4.1 IDLE Mode Timing Requirements
            2. 8.9.12.3.4.2 IDLE Mode Switching Characteristics
            3. 8.9.12.3.4.3 STANDBY Mode Timing Requirements
            4. 8.9.12.3.4.4 STANDBY Mode Switching Characteristics
            5. 8.9.12.3.4.5 HALT Mode Timing Requirements
            6. 8.9.12.3.4.6 HALT Mode Switching Characteristics
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 サポート・リソース
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.2.1 Signal Descriptions

TERMINAL I/O/Z(1) DESCRIPTION
NAME PN
PIN NO.
JTAG
TRST 9 I JTAG test reset with internal pulldown (PD). TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE:TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because the value of the resistor is application-specific, TI recommends that each target board be validated for proper operation of the debugger and the application. (↓)
TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup. (↑)
TMS See GPIO36 I See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK.. (↑)
TDI See GPIO35 I See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (↑)
TDO See GPIO37 O/Z See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA drive)
FLASH
TEST2 39 I/O Test Pin. Reserved for TI. Must be left unconnected.
CLOCK
XCLKOUT See GPIO18 O/Z See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. The value of XCLKOUT is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
XCLKIN See GPIO19 and GPIO38 I See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be disabled through bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register.
NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This action is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device.
X1 52 I On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, this pin must be tied to GND. (I)
X2 51 O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, X2 must be left unconnected. (O)
RESET
XRS 8 I/OD Device Reset (in) and Watchdog Reset (out). These devices have a built-in power-on reset (POR) and brownout reset (BOR) circuitry. During a power-on or brownout condition, this pin is driven low by the device. An external circuit may also drive this pin to assert a device reset. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and VDDIO. If a capacitor is placed between XRS and VSS for noise filtering, it should be 100 nF or smaller. These values will allow the watchdog to properly drive the XRS pin to VOL within 512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3F FFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. (↑) If this pin is driven by an external device, it should be done using an open-drain device.
ADC, COMPARATOR, ANALOG I/O
ADCINA7 24 I ADC Group A, Channel 7 input
ADCINA6
(op-amp)		 23 I ADC Group A, Channel 6 input
ADCINA5 10 I ADC Group A, Channel 5 input
ADCINA4 11 I ADC Group A, Channel 4 input
ADCINA3
(op-amp)		 12 I ADC Group A, Channel 3 input
ADCINA2 13 I ADC Group A, Channel 2 input
ADCINA1
(op-amp)		 14 I ADC Group A, Channel 1 input
ADCINA0 18 I ADC Group A, Channel 0 input
VREFOUT Voltage Reference out from buffered DAC
VREFHI 19 I ADC External Reference – used when in ADC external reference mode and used as VREFOUT reference
ADCINB7
(op-amp)		 31 I ADC Group B, Channel 7 input
ADCINB6
(op-amp)		 29 I ADC Group B, Channel 6 input
ADCINB5 28 I ADC Group B, Channel 5 input
ADCINB4
(op-amp)		 26 I ADC Group B, Channel 4 input
ADCINB3 25 I ADC Group B, Channel 3 input
ADCINB2 16 I ADC Group B, Channel 2 input
ADCINB1
(op-amp)		 17 I ADC Group B, Channel 1 input
ADCINB0 30 I ADC Group B, Channel 0 input
VREFLO 22 I ADC Low Reference (always tied to ground)
CPU AND I/O POWER
VDDA 20 Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.
VSSA 21 Analog Ground Pin
VDD 6 CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF capacitor between each VDD pin and ground. Higher value capacitors may be used.
54
73
VDDIO 38 Digital I/O Buffers and Flash Memory Power Pin. Single supply source when VREG is enabled. Place a decoupling capacitor on each pin. The exact value should be determined by the system voltage regulation solution.
70
VSS 7 Digital Ground Pins
37
53
72
M1GND 15 Ground pin for amplifier (channels A1, A3, B1)
M2GND 27 Ground pin for amplifier (channels A6, B4, B6)
PFCGND 32 Ground pin for amplifier (channel B7)
VOLTAGE REGULATOR CONTROL SIGNAL
VREGENZ 71 I Internal voltage regulator (VREG) enable with internal pulldown. Tie directly to VSS (low) to enable the internal 1.8-V VREG. Tie directly to VDDIO (high) to disable the VREG and use an external 1.8-V supply.
GPIO AND PERIPHERAL SIGNALS(2)
GPIO0 69 I/O/Z General-purpose input/output 0
EPWM1A O Enhanced PWM1 Output A
Reserved – Reserved
Reserved – Reserved
GPIO1 68 I/O/Z General-purpose input/output 1
EPWM1B O Enhanced PWM1 Output B
Reserved – Reserved
CTRIPM1OUT O CTRIPM1 CTRIPxx output
GPIO2 67 I/O/Z General-purpose input/output 2
EPWM2A O Enhanced PWM2 Output A
Reserved – Reserved
Reserved – Reserved
GPIO3 66 I/O/Z General-purpose input/output 3
EPWM2B O Enhanced PWM2 Output B
SPISOMIA I/O SPI-A slave out, master in
Reserved – Reserved
GPIO4 63 I/O/Z General-purpose input/output 4
EPWM3A O Enhanced PWM3 output A
Reserved – Reserved
Reserved – Reserved
GPIO5 62 I/O/Z General-purpose input/output 5
EPWM3B O Enhanced PWM3 output B
SPISIMOA I/O SPI-A slave in, master out
ECAP1 I/O Enhanced Capture input/output 1
GPIO6 50 I/O/Z General-purpose input/output 6
EPWM4A O Enhanced PWM4 output A
EPWMSYNCI I External ePWM sync pulse input
EPWMSYNCO O External ePWM sync pulse output
GPIO7 49 I/O/Z General-purpose input/output 7
EPWM4B O Enhanced PWM4 output B
SCIRXDA I SCI-A receive data
Reserved – Reserved
GPIO8 45 I/O/Z General-purpose input/output 8
EPWM5A O Enhanced PWM5 output A
Reserved – Reserved
ADCSOCAO O ADC start-of-conversion A
GPIO9 36 I/O/Z General-purpose input/output 9
EPWM5B O Enhanced PWM5 output B
SCITXDB O SCI-B transmit data
Reserved – Reserved
GPIO10 65 I/O/Z General-purpose input/output 10
EPWM6A O Enhanced PWM6 output A
Reserved – Reserved
ADCSOCBO O ADC start-of-conversion B
GPIO11 61 I/O/Z General-purpose input/output 11
EPWM6B O Enhanced PWM6 output B
SCIRXDB I SCI-B receive data
Reserved – Reserved
GPIO12 48 I/O/Z General-purpose input/output 12
TZ1 I Trip Zone input 1
CTRIPM1OUT O CTRIPM1 CTRIPxx output
SCITXDA O SCI-A transmit data
Reserved – Reserved
GPIO13 76 I/O/Z General-purpose input/output 13
TZ2 I Trip zone input 2
Reserved – Reserved
Reserved – Reserved
GPIO14 77 I/O/Z General-purpose input/output 14
TZ3 I Trip zone input 3
CTRIPPFCOUT O CTRIPPFC output
SCITXDB O SCI-B transmit data
Reserved – Reserved
GPIO15 75 I/O/Z General-purpose input/output 15
TZ1 I Trip zone input 1
CTRIPM1OUT O CTRIPM1 CTRIPxx output
SCIRXDB I SCI-B receive data
Reserved – Reserved
GPIO16 47 I/O/Z General-purpose input/output 16
SPISIMOA I/O SPI-A slave in, master out
EQEP1S I/O Enhanced QEP1 strobe
TZ2 I Trip Zone input 2
GPIO17 44 I/O/Z General-purpose input/output 17
SPISOMIA I/O SPI-A slave out, master in
EQEP1I I/O Enhanced QEP1 index
TZ3 I Trip zone input 3
CTRIPPFCOUT O CTRIPPFC output
GPIO18 43 I/O/Z General-purpose input/output 18
SPICLKA I/O SPI-A clock input/output
SCITXDB O SCI-B transmit data
XCLKOUT O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. The value of XCLKOUT is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.
GPIO19 55 I/O/Z General-purpose input/output 19
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken not to enable this path for clocking if this path is being used for the other periperhal functions
SPISTEA I/O SPI-A slave transmit enable input/output
SCIRXDB I SCI-B receive data
ECAP1 I/O Enhanced Capture input/output 1
GPIO20 78 I/O/Z General-purpose input/output 20. Internal pullup enabled by default.
EQEP1A I Enhanced QEP1 input A
EPWM7A O Enhanced PWM7 output A
CTRIPM1OUT O CTRIPM1 CTRIPxx output
GPIO21 79 I/O/Z General-purpose input/output 21. Internal pullup enabled by default.
EQEP1B I Enhanced QEP1 input B
EPWM7B O Enhanced PWM7 output B
Reserved – Reserved
GPIO22 1 I/O/Z General-purpose input/output 22
EQEP1S I/O Enhanced QEP1 strobe
Reserved – Reserved
SCITXDB O SCI-B transmit data
GPIO23 80 I/O/Z General-purpose input/output 23
EQEP1I I/O Enhanced QEP1 index
Reserved – Reserved
SCIRXDB I SCI-B receive data
GPIO24 4 I/O/Z General-purpose input/output 24. Internal pullup enabled by default.
ECAP1 I/O Enhanced Capture input/output 1
EPWM7A O Enhanced PWM7 output A
Reserved – Reserved
GPIO25 46 I/O/Z General-purpose input/output 25
Reserved – Reserved
Reserved – Reserved
Reserved – Reserved
GPIO26 40 I/O/Z General-purpose input/output 26
Reserved – Reserved
SCIRXDC I SCI-C receive data
Reserved – Reserved
GPIO27 33 I/O/Z General-purpose input/output 27
Reserved – Reserved
SCITXDC O SCI-C transmit data
Reserved – Reserved
GPIO28 42 I/O/Z General-purpose input/output 28
SCIRXDA I SCI-A receive data
SDAA I/OD I2C data open-drain bidirectional port
TZ2 I Trip zone input 2
GPIO29 41 I/O/Z General-purpose input/output 29
SCITXDA O SCI-A transmit data
SCLA I/OD I2C clock open-drain bidirectional port
TZ3 I Trip zone input 3
CTRIPPFCOUT O CTRIPPFC output
GPIO30 35 I/O/Z General-purpose input/output 30. Internal pullup enabled by default.
CANRXA I CAN receive
SCIRXDB I SCI-B receive data
EPWM7A O Enhanced PWM7 output A
GPIO31 34 I/O/Z General-purpose input/output 31. Internal pullup enabled by default.
CANTXA O CAN transmit
SCITXDB O SCI-B transmit data
EPWM7B O Enhanced PWM7 output B
GPIO32 2 I/O/Z General-purpose input/output 32
SDAA I/OD I2C data open-drain bidirectional port
EPWMSYNCI I Enhanced PWM external sync pulse input
EQEP1S I/O Enhanced QEP1 strobe
GPIO33 3 I/O/Z General-Purpose Input/Output 33
SCLA I/OD I2C clock open-drain bidirectional port
EPWMSYNCO O Enhanced PWM external synch pulse output
EQEP1I I/O Enhanced QEP1 index
GPIO34 74 I/O/Z General-Purpose Input/Output 34
Reserved – Reserved
Reserved – Reserved
CTRIPPFCOUT O CTRIPPFC output
GPIO35 59 I/O/Z General-Purpose Input/Output 35
TDI I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK
Reserved – Reserved
Reserved – Reserved
Reserved – Reserved
GPIO36 60 I/O/Z General-Purpose Input/Output 36
TMS I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK.
Reserved – Reserved
Reserved – Reserved
Reserved – Reserved
GPIO37 58 I/O/Z General-Purpose Input/Output 37
TDO O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive)
Reserved – Reserved
Reserved – Reserved
Reserved – Reserved
GPIO38 57 I/O/Z General-Purpose Input/Output 38
XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if this path is being used for the other functions.
TCK I JTAG test clock with internal pullup
Reserved – Reserved
Reserved – Reserved
Reserved – Reserved
GPIO39 56 I/O/Z General-Purpose Input/Output 39
Reserved – Reserved
SCIRXDC I SCI-C receive data
CTRIPPFCOUT O CTRIPPFC output
GPIO40 64 I/O/Z General-Purpose Input/Output 40. Internal pullup enabled by default.
EPWM7A O Enhanced PWM7 output A
Reserved – Reserved
Reserved – Reserved
GPIO42 5 I/O/Z General-Purpose Input/Output 42. Internal pullup enabled by default.
EPWM7B O Enhanced PWM7 output B
SCITXDC O SCI-C transmit data
CTRIPM1OUT O CTRIPM1 CTRIPxx output
(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown
(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal. For details, see the System Control and Interrupts chapter of the TMS320x2805x Real-Time Microcontrollers Technical Reference Manual.