JAJSFH1J November   2010  – September 2021 TMS320F28062 , TMS320F28062F , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28067 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069F , TMS320F28069M

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1. 3.1 機能ブロック図
    2. 3.2 システム・デバイス図
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 TMS320F2806x Current Consumption at 90-MHz SYSCLKOUT
      2. 7.5.2 Reducing Current Consumption
      3. 7.5.3 Current Consumption Graphs (VREG Enabled)
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics
      1. 7.7.1 PFP PowerPAD Package
      2. 7.7.2 PZP PowerPAD Package
      3. 7.7.3 PN Package
      4. 7.7.4 PZ Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Debug Probe Connection Without Signal Buffering for the MCU
    10. 7.10 Parameter Information
      1. 7.10.1 Timing Parameter Symbology
      2. 7.10.2 General Notes on Timing Parameters
    11. 7.11 Test Load Circuit
    12. 7.12 Power Sequencing
      1. 7.12.1 Reset ( XRS) Timing Requirements
      2. 7.12.2 Reset ( XRS) Switching Characteristics
    13. 7.13 Clock Specifications
      1. 7.13.1 Device Clock Table
        1. 7.13.1.1 2806x Clock Table and Nomenclature (90-MHz Devices)
        2. 7.13.1.2 Device Clocking Requirements/Characteristics
        3. 7.13.1.3 Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics
      2. 7.13.2 Clock Requirements and Characteristics
        1. 7.13.2.1 XCLKIN Timing Requirements – PLL Enabled
        2. 7.13.2.2 XCLKIN Timing Requirements – PLL Disabled
        3. 7.13.2.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
    14. 7.14 Flash Timing
      1. 7.14.1 Flash/OTP Endurance for T Temperature Material
      2. 7.14.2 Flash/OTP Endurance for S Temperature Material
      3. 7.14.3 Flash/OTP Endurance for Q Temperature Material
      4. 7.14.4 Flash Parameters at 90-MHz SYSCLKOUT
      5. 7.14.5 Flash/OTP Access Timing
      6. 7.14.6 Flash Data Retention Duration
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1  CPU
      2. 8.1.2  Control Law Accelerator (CLA)
      3. 8.1.3  Viterbi, Complex Math, CRC Unit (VCU)
      4. 8.1.4  Memory Bus (Harvard Bus Architecture)
      5. 8.1.5  Peripheral Bus
      6. 8.1.6  Real-Time JTAG and Analysis
      7. 8.1.7  Flash
      8. 8.1.8  M0, M1 SARAMs
      9. 8.1.9  L4 SARAM, and L0, L1, L2, L3, L5, L6, L7, and L8 DPSARAMs
      10. 8.1.10 Boot ROM
        1. 8.1.10.1 Debug Boot
        2. 8.1.10.2 GetMode
        3. 8.1.10.3 Peripheral Pins Used by the Bootloader
      11. 8.1.11 Security
      12. 8.1.12 Peripheral Interrupt Expansion (PIE) Block
      13. 8.1.13 External Interrupts (XINT1 to XINT3)
      14. 8.1.14 Internal Zero Pin Oscillators, Oscillator, and PLL
      15. 8.1.15 Watchdog
      16. 8.1.16 Peripheral Clocking
      17. 8.1.17 Low-power Modes
      18. 8.1.18 Peripheral Frames 0, 1, 2, 3 (PFn)
      19. 8.1.19 General-Purpose Input/Output (GPIO) Multiplexer
      20. 8.1.20 32-Bit CPU-Timers (0, 1, 2)
      21. 8.1.21 Control Peripherals
      22. 8.1.22 Serial Port Peripherals
    2. 8.2 Memory Maps
    3. 8.3 Register Maps
    4. 8.4 Device Debug Registers
    5. 8.5 VREG, BOR, POR
      1. 8.5.1 On-chip VREG
        1. 8.5.1.1 Using the On-chip VREG
        2. 8.5.1.2 Disabling the On-chip VREG
      2. 8.5.2 On-chip Power-On Reset (POR) and Brownout Reset (BOR) Circuit
    6. 8.6 System Control
      1. 8.6.1 Internal Zero Pin Oscillators
      2. 8.6.2 Crystal Oscillator Option
      3. 8.6.3 PLL-Based Clock Module
      4. 8.6.4 USB and HRCAP PLL Module (PLL2)
      5. 8.6.5 Loss of Input Clock (NMI Watchdog Function)
      6. 8.6.6 CPU Watchdog Module
    7. 8.7 Low-power Modes Block
    8. 8.8 Interrupts
      1. 8.8.1 External Interrupts
        1. 8.8.1.1 External Interrupt Electrical Data/Timing
          1. 8.8.1.1.1 External Interrupt Timing Requirements
          2. 8.8.1.1.2 External Interrupt Switching Characteristics
    9. 8.9 Peripherals
      1. 8.9.1  CLA Overview
      2. 8.9.2  Analog Block
        1. 8.9.2.1 Analog-to-Digital Converter (ADC)
          1. 8.9.2.1.1 Features
          2. 8.9.2.1.2 ADC Start-of-Conversion Electrical Data/Timing
            1. 8.9.2.1.2.1 External ADC Start-of-Conversion Switching Characteristics
          3. 8.9.2.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing
            1. 8.9.2.1.3.1 ADC Electrical Characteristics
            2. 8.9.2.1.3.2 ADC Power Modes
            3. 8.9.2.1.3.3 Internal Temperature Sensor
              1. 8.9.2.1.3.3.1 Temperature Sensor Coefficient
            4. 8.9.2.1.3.4 ADC Power-Up Control Bit Timing
              1. 8.9.2.1.3.4.1 ADC Power-Up Delays
            5. 8.9.2.1.3.5 ADC Sequential and Simultaneous Timings
        2. 8.9.2.2 ADC MUX
        3. 8.9.2.3 Comparator Block
          1. 8.9.2.3.1 On-Chip Comparator/DAC Electrical Data/Timing
            1. 8.9.2.3.1.1 Electrical Characteristics of the Comparator/DAC
      3. 8.9.3  Detailed Descriptions
      4. 8.9.4  Serial Peripheral Interface (SPI) Module
        1. 8.9.4.1 SPI Master Mode Electrical Data/Timing
          1. 8.9.4.1.1 SPI Master Mode External Timing (Clock Phase = 0)
          2. 8.9.4.1.2 SPI Master Mode External Timing (Clock Phase = 1)
        2. 8.9.4.2 SPI Slave Mode Electrical Data/Timing
          1. 8.9.4.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
          2. 8.9.4.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 8.9.5  Serial Communications Interface (SCI) Module
      6. 8.9.6  Multichannel Buffered Serial Port (McBSP) Module
        1. 8.9.6.1 McBSP Electrical Data/Timing
          1. 8.9.6.1.1 McBSP Transmit and Receive Timing
            1. 8.9.6.1.1.1 McBSP Timing Requirements
            2. 8.9.6.1.1.2 McBSP Switching Characteristics
          2. 8.9.6.1.2 McBSP as SPI Master or Slave Timing
            1. 8.9.6.1.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 8.9.6.1.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 8.9.6.1.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. 8.9.6.1.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 8.9.6.1.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. 8.9.6.1.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 8.9.6.1.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. 8.9.6.1.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      7. 8.9.7  Enhanced Controller Area Network (eCAN) Module
      8. 8.9.8  Inter-Integrated Circuit (I2C)
        1. 8.9.8.1 I2C Electrical Data/Timing
          1. 8.9.8.1.1 I2C Timing Requirements
          2. 8.9.8.1.2 I2C Switching Characteristics
      9. 8.9.9  Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1 to ePWM8)
        1. 8.9.9.1 ePWM Electrical Data/Timing
          1. 8.9.9.1.1 ePWM Timing Requirements
          2. 8.9.9.1.2 ePWM Switching Characteristics
        2. 8.9.9.2 Trip-Zone Input Timing
          1. 8.9.9.2.1 Trip-Zone Input Timing Requirements
      10. 8.9.10 High-Resolution PWM (HRPWM)
        1. 8.9.10.1 HRPWM Electrical Data/Timing
          1. 8.9.10.1.1 High-Resolution PWM Characteristics
      11. 8.9.11 Enhanced Capture Module (eCAP1)
        1. 8.9.11.1 eCAP Electrical Data/Timing
          1. 8.9.11.1.1 Enhanced Capture (eCAP) Timing Requirement
          2. 8.9.11.1.2 eCAP Switching Characteristics
      12. 8.9.12 High-Resolution Capture Modules (HRCAP1 to HRCAP4)
        1. 8.9.12.1 HRCAP Electrical Data/Timing
          1. 8.9.12.1.1 High-Resolution Capture (HRCAP) Timing Requirements
      13. 8.9.13 Enhanced Quadrature Encoder Modules (eQEP1, eQEP2)
        1. 8.9.13.1 eQEP Electrical Data/Timing
          1. 8.9.13.1.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
          2. 8.9.13.1.2 eQEP Switching Characteristics
      14. 8.9.14 JTAG Port
      15. 8.9.15 General-Purpose Input/Output (GPIO) MUX
        1. 8.9.15.1 GPIO Electrical Data/Timing
          1. 8.9.15.1.1 GPIO Output Timing
            1. 8.9.15.1.1.1 General-Purpose Output Switching Characteristics
          2. 8.9.15.1.2 GPIO Input Timing
            1. 8.9.15.1.2.1 General-Purpose Input Timing Requirements
          3. 8.9.15.1.3 Sampling Window Width for Input Signals
          4. 8.9.15.1.4 Low-Power Mode Wakeup Timing
            1. 8.9.15.1.4.1 IDLE Mode Timing Requirements
            2. 8.9.15.1.4.2 IDLE Mode Switching Characteristics
            3. 8.9.15.1.4.3 STANDBY Mode Timing Requirements
            4. 8.9.15.1.4.4 STANDBY Mode Switching Characteristics
            5. 8.9.15.1.4.5 HALT Mode Timing Requirements
            6. 8.9.15.1.4.6 HALT Mode Switching Characteristics
      16. 8.9.16 Universal Serial Bus (USB)
        1. 8.9.16.1 USB Electrical Data/Timing
          1. 8.9.16.1.1 USB Input Ports DP and DM Timing Requirements
          2. 8.9.16.1.2 USB Output Ports DP and DM Switching Characteristics
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.9.7 Enhanced Controller Area Network (eCAN) Module

The CAN module (eCAN-A) has the following features:

  • Fully compliant with CAN protocol, version 2.0B
  • Supports data rates up to 1 Mbps
  • Thirty-two mailboxes, each with the following properties:
    • Configurable as receive or transmit
    • Configurable with standard or extended identifier
    • Has a programmable receive mask
    • Supports data and remote frame
    • Composed of 0 to 8 bytes of data
    • Uses a 32-bit timestamp on receive and transmit message
    • Protects against reception of new message
    • Holds the dynamically programmable priority of transmit message
    • Employs a programmable interrupt scheme with two interrupt levels
    • Employs a programmable alarm on transmission or reception time-out
  • Low-power mode
  • Programmable wake-up on bus activity
  • Automatic reply to a remote request message
  • Automatic retransmission of a frame in case of loss of arbitration or error
  • 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16)
  • Self-test mode
    • Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby eliminating the need for another node to provide the acknowledge bit.

Note:

For a SYSCLKOUT of 90 MHz, the smallest bit rate possible is 6.25 kbps.

The F2806x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions.

GUID-CDC96828-4C65-47E9-8E67-C14EB9700E9F-low.gifFigure 8-45 eCAN Block Diagram and Interface Circuit
Table 8-30 3.3-V eCAN Transceivers
PART NUMBERSUPPLY
VOLTAGE		LOW-POWER
MODE		SLOPE
CONTROL		VREFOTHERTA
SN65HVD2303.3 VStandbyAdjustableYes––40°C to 85°C
SN65HVD230Q3.3 VStandbyAdjustableYes––40°C to 125°C
SN65HVD2313.3 VSleepAdjustableYes––40°C to 85°C
SN65HVD231Q3.3 VSleepAdjustableYes––40°C to 125°C
SN65HVD2323.3 VNoneNoneNone––40°C to 85°C
SN65HVD232Q3.3 VNoneNoneNone––40°C to 125°C
SN65HVD2333.3 VStandbyAdjustableNoneDiagnostic Loopback–40°C to 125°C
SN65HVD2343.3 VStandby and SleepAdjustableNone––40°C to 125°C
SN65HVD2353.3 VStandbyAdjustableNoneAutobaud Loopback–40°C to 125°C
ISO10503–5.5 VNoneNoneNoneBuilt-in Isolation
Low Prop Delay
Thermal Shutdown
Fail-safe Operation
Dominant Time-Out		–55°C to 105°C
GUID-C546C560-EB66-4837-83D8-8453AB7C1D0A-low.gifFigure 8-46 eCAN-A Memory Map
Note:

If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.

The CAN registers listed in Table 8-31 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. All 32-bit accesses are aligned to an even boundary.

Table 8-31 CAN Registers
REGISTER NAME(1)eCAN-A
ADDRESS		SIZE (×32)DESCRIPTION
CANME0x60001Mailbox enable
CANMD0x60021Mailbox direction
CANTRS0x60041Transmit request set
CANTRR0x60061Transmit request reset
CANTA0x60081Transmission acknowledge
CANAA0x600A1Abort acknowledge
CANRMP0x600C1Receive message pending
CANRML0x600E1Receive message lost
CANRFP0x60101Remote frame pending
CANGAM0x60121Global acceptance mask
CANMC0x60141Master control
CANBTC0x60161Bit-timing configuration
CANES0x60181Error and status
CANTEC0x601A1Transmit error counter
CANREC0x601C1Receive error counter
CANGIF00x601E1Global interrupt flag 0
CANGIM0x60201Global interrupt mask
CANGIF10x60221Global interrupt flag 1
CANMIM0x60241Mailbox interrupt mask
CANMIL0x60261Mailbox interrupt level
CANOPC0x60281Overwrite protection control
CANTIOC0x602A1TX I/O control
CANRIOC0x602C1RX I/O control
CANTSC0x602E1Timestamp counter (Reserved in SCC mode)
CANTOC0x60301Time-out control (Reserved in SCC mode)
CANTOS0x60321Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.