JAJSFH1J November 2010 – September 2021
PRODUCTION DATA
The device contains one I2C Serial Port. Figure 8-47 shows how the I2C peripheral module interfaces within the device.
The I2C module has the following features:
The registers in Table 8-32 configure and control the I2C port operation.
NAME | ADDRESS | EALLOW PROTECTED | DESCRIPTION |
---|---|---|---|
I2COAR | 0x7900 | No | I2C own address register |
I2CIER | 0x7901 | No | I2C interrupt enable register |
I2CSTR | 0x7902 | No | I2C status register |
I2CCLKL | 0x7903 | No | I2C clock low-time divider register |
I2CCLKH | 0x7904 | No | I2C clock high-time divider register |
I2CCNT | 0x7905 | No | I2C data count register |
I2CDRR | 0x7906 | No | I2C data receive register |
I2CSAR | 0x7907 | No | I2C slave address register |
I2CDXR | 0x7908 | No | I2C data transmit register |
I2CMDR | 0x7909 | No | I2C mode register |
I2CISRC | 0x790A | No | I2C interrupt source register |
I2CPSC | 0x790C | No | I2C prescaler register |
I2CFFTX | 0x7920 | No | I2C FIFO transmit register |
I2CFFRX | 0x7921 | No | I2C FIFO receive register |
I2CRSR | – | No | I2C receive shift register (not accessible to the CPU) |
I2CXSR | – | No | I2C transmit shift register (not accessible to the CPU) |