JAJS280O October   2003  – March 2019 TMS320F2801 , TMS320F28015 , TMS320F28016 , TMS320F2802 , TMS320F2806 , TMS320F2808 , TMS320F2809

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Automotive
    3. 5.3  ESD Ratings – Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F2809, TMS320F2808 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      2. Table 5-2 TMS320F2806 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      3. Table 5-3 TMS320F2802, TMS320F2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      4. Table 5-4 TMS320C2802, TMS320C2801 Current Consumption by Power-Supply Pins at 100-MHz SYSCLKOUT
      5. 5.5.1     Reducing Current Consumption
      6. 5.5.2     Current Consumption Graphs
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics for F280x 100-Ball GGM Package
    8. 5.8  Thermal Resistance Characteristics for F280x 100-Pin PZ Package
    9. 5.9  Thermal Resistance Characteristics for C280x 100-Ball GGM Package
    10. 5.10 Thermal Resistance Characteristics for C280x 100-Pin PZ Package
    11. 5.11 Thermal Resistance Characteristics for F2809 100-Ball GGM Package
    12. 5.12 Thermal Resistance Characteristics for F2809 100-Pin PZ Package
    13. 5.13 Thermal Design Considerations
    14. 5.14 Timing and Switching Characteristics
      1. 5.14.1 Timing Parameter Symbology
        1. 5.14.1.1 General Notes on Timing Parameters
        2. 5.14.1.2 Test Load Circuit
        3. 5.14.1.3 Device Clock Table
          1. Table 5-6 TMS320x280x Clock Table and Nomenclature (100-MHz Devices)
          2. Table 5-7 TMS320x280x/2801x Clock Table and Nomenclature (60-MHz Devices)
      2. 5.14.2 Power Sequencing
        1. Table 5-8 Reset (XRS) Timing Requirements
      3. 5.14.3 Clock Requirements and Characteristics
        1. Table 5-9  Input Clock Frequency
        2. Table 5-10 XCLKIN Timing Requirements - PLL Enabled
        3. Table 5-11 XCLKIN Timing Requirements - PLL Disabled
        4. Table 5-12 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.14.4 Peripherals
        1. 5.14.4.1 General-Purpose Input/Output (GPIO)
          1. 5.14.4.1.1 GPIO - Output Timing
            1. Table 5-13 General-Purpose Output Switching Characteristics
          2. 5.14.4.1.2 GPIO - Input Timing
            1. Table 5-14 General-Purpose Input Timing Requirements
          3. 5.14.4.1.3 Sampling Window Width for Input Signals
          4. 5.14.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-15 IDLE Mode Timing Requirements
            2. Table 5-16 IDLE Mode Switching Characteristics
            3. Table 5-17 STANDBY Mode Timing Requirements
            4. Table 5-18 STANDBY Mode Switching Characteristics
            5. Table 5-19 HALT Mode Timing Requirements
            6. Table 5-20 HALT Mode Switching Characteristics
        2. 5.14.4.2 Enhanced Control Peripherals
          1. 5.14.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-21 ePWM Timing Requirements
            2. Table 5-22 ePWM Switching Characteristics
          2. 5.14.4.2.2 Trip-Zone Input Timing
            1. Table 5-23 Trip-Zone input Timing Requirements
          3. 5.14.4.2.3 High-Resolution PWM Timing
            1. Table 5-24 High-Resolution PWM Characteristics at SYSCLKOUT = 60–100 MHz
          4. 5.14.4.2.4 Enhanced Capture (eCAP) Timing
            1. Table 5-25 Enhanced Capture (eCAP) Timing Requirement
            2. Table 5-26 eCAP Switching Characteristics
          5. 5.14.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. Table 5-27 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. Table 5-28 eQEP Switching Characteristics
          6. 5.14.4.2.6 ADC Start-of-Conversion Timing
            1. Table 5-29 External ADC Start-of-Conversion Switching Characteristics
        3. 5.14.4.3 External Interrupt Timing
          1. Table 5-30 External Interrupt Timing Requirements
          2. Table 5-31 External Interrupt Switching Characteristics
        4. 5.14.4.4 I2C Electrical Specification and Timing
          1. Table 5-32 I2C Timing
        5. 5.14.4.5 Serial Peripheral Interface (SPI) Timing
          1. 5.14.4.5.1 SPI Master Mode Timing
            1. Table 5-33 SPI Master Mode External Timing (Clock Phase = 0)
            2. Table 5-34 SPI Master Mode External Timing (Clock Phase = 1)
          2. 5.14.4.5.2 SPI Slave Mode Timing
            1. Table 5-35 SPI Slave Mode External Timing (Clock Phase = 0)
            2. Table 5-36 SPI Slave Mode External Timing (Clock Phase = 1)
      5. 5.14.5 Emulator Connection Without Signal Buffering for the DSP
      6. 5.14.6 Flash Timing
        1. Table 5-37 Flash Endurance for A and S Temperature Material
        2. Table 5-38 Flash Endurance for Q Temperature Material
        3. Table 5-39 Flash Parameters at 100-MHz SYSCLKOUT
        4. Table 5-40 Flash/OTP Access Timing
        5. Table 5-41 Flash Data Retention Duration
    15. 5.15 On-Chip Analog-to-Digital Converter
      1. Table 5-43 ADC Electrical Characteristics
      2. 5.15.1     ADC Power-Up Control Bit Timing
        1. Table 5-44 ADC Power-Up Delays
        2. Table 5-45 Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK)
      3. 5.15.2     Definitions
      4. 5.15.3     Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. Table 5-46 Sequential Sampling Mode Timing
      5. 5.15.4     Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. Table 5-47 Simultaneous Sampling Mode Timing
      6. 5.15.5     Detailed Descriptions
    16. 5.16 Migrating From F280x Devices to C280x Devices
      1. 5.16.1 Migration Issues
    17. 5.17 ROM Timing (C280x only)
      1. Table 5-48 ROM/OTP Access Timing
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  Flash
      6. 6.1.6  ROM
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0, L1, H0 SARAMs
      9. 6.1.9  Boot ROM
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12 External Interrupts (XINT1, XINT2, XNMI)
      13. 6.1.13 Oscillator and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-Power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2 (PFn)
      18. 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1  32-Bit CPU-Timers 0/1/2
      2. 6.2.2  Enhanced PWM Modules (ePWM1/2/3/4/5/6)
      3. 6.2.3  Hi-Resolution PWM (HRPWM)
      4. 6.2.4  Enhanced CAP Modules (eCAP1/2/3/4)
      5. 6.2.5  Enhanced QEP Modules (eQEP1/2)
      6. 6.2.6  Enhanced Analog-to-Digital Converter (ADC) Module
        1. 6.2.6.1 ADC Connections if the ADC Is Not Used
        2. 6.2.6.2 ADC Registers
      7. 6.2.7  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      8. 6.2.8  Serial Communications Interface (SCI) Modules (SCI-A, SCI-B)
      9. 6.2.9  Serial Peripheral Interface (SPI) Modules (SPI-A, SPI-B, SPI-C, SPI-D)
      10. 6.2.10 Inter-Integrated Circuit (I2C)
      11. 6.2.11 GPIO MUX
    3. 6.3 Memory Maps
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスおよび開発ツールの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PZ|100
  • GBA|100
  • NMF|100
サーマルパッド・メカニカル・データ
発注情報

6.2.11 GPIO MUX

On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin is shown in Figure 6-16. Because of the open-drain capabilities of the I2C pins, the GPIO MUX block diagram for these pins differ. See the TMS320x280x, 2801x, 2804x DSP system control and interrupts reference guide for details.

TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 gpiomux_prs230.gif
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
Figure 6-16 GPIO MUX Block Diagram

The 280x supports 34 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-16 shows the GPIO register mapping.

Table 6-16 GPIO Registers

NAME ADDRESS SIZE (x16) DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31)
GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31)
GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31)
Reserved 0x6F8E –
0x6F8F		 2 Reserved
GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 35)
GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 35)
GPBQSEL2 0x6F94 2 Reserved
GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 35)
GPBMUX2 0x6F98 2 Reserved
GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 35)
GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 35)
Reserved 0x6F9E –
0x6F9F		 2 Reserved
Reserved 0x6FA0 –
0x6FBF		 32 Reserved
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT 0x6FC0 2 GPIO Data Register (GPIO0 to 31)
GPASET 0x6FC2 2 GPIO Data Set Register (GPIO0 to 31)
GPACLEAR 0x6FC4 2 GPIO Data Clear Register (GPIO0 to 31)
GPATOGGLE 0x6FC6 2 GPIO Data Toggle Register (GPIO0 to 31)
GPBDAT 0x6FC8 2 GPIO Data Register (GPIO32 to 35)
GPBSET 0x6FCA 2 GPIO Data Set Register (GPIO32 to 35)
GPBCLEAR 0x6FCC 2 GPIO Data Clear Register (GPIO32 to 35)
GPBTOGGLE 0x6FCE 2 GPIO Data Toggle Register (GPIO32 to 35)
Reserved 0x6FD0 –
0x6FDF		 16 Reserved
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXNMISEL 0x6FE2 1 XNMI GPIO Input Select Register (GPIO0 to 31)
Reserved 0x6FE3 –
0x6FE7		 5 Reserved
GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31)
Reserved 0x6FEA –
0x6FFF		 22 Reserved

Table 6-17 F2808 GPIO MUX Table

GPAMUX1/2(3)
REGISTER BITS		 DEFAULT AT RESET
PRIMARY I/O
FUNCTION
(GPxMUX1/2
BITS = 0,0)		 PERIPHERAL
SELECTION 1(1)
(GPxMUX1/2 BITS = 0,1)		 PERIPHERAL
SELECTION 2
(GPxMUX1/2 BITS = 1,0)		 PERIPHERAL
SELECTION 3
(GPxMUX1/2 BITS = 1,1)
GPAMUX1
1–0 GPIO0 EPWM1A (O) Reserved(2) Reserved(2)
3–2 GPIO1 EPWM1B (O) SPISIMOD (I/O) Reserved(2)
5–4 GPIO2 EPWM2A (O) Reserved(2) Reserved(2)
7–6 GPIO3 EPWM2B (O) SPISOMID (I/O) Reserved(2)
9–8 GPIO4 EPWM3A (O) Reserved(2) Reserved(2)
11–10 GPIO5 EPWM3B (O) SPICLKD (I/O) ECAP1 (I/O)
13–12 GPIO6 EPWM4A (O) EPWMSYNCI (I) EPWMSYNCO (O)
15–14 GPIO7 EPWM4B (O) SPISTED (I/O) ECAP2 (I/O)
17–16 GPIO8 EPWM5A (O) CANTXB (O) ADCSOCAO (O)
19–18 GPIO9 EPWM5B (O) SCITXDB (O) ECAP3 (I/O)
21–20 GPIO10 EPWM6A (O) CANRXB (I) ADCSOCBO (O)
23–22 GPIO11 EPWM6B (O) SCIRXDB (I) ECAP4 (I/O)
25–24 GPIO12 TZ1 (I) CANTXB (O) SPISIMOB (I/O)
27–26 GPIO13 TZ2 (I) CANRXB (I) SPISOMIB (I/O)
29–28 GPIO14 TZ3 (I) SCITXDB (O) SPICLKB (I/O)
31–30 GPIO15 TZ4 (I) SCIRXDB (I) SPISTEB (I/O)
GPAMUX2
1–0 GPIO16 SPISIMOA (I/O) CANTXB (O) TZ5 (I)
3–2 GPIO17 SPISOMIA (I/O) CANRXB (I) TZ6 (I)
5–4 GPIO18 SPICLKA (I/O) SCITXDB (O) Reserved(2)
7–6 GPIO19 SPISTEA (I/O) SCIRXDB (I) Reserved(2)
9–8 GPIO20 EQEP1A (I) SPISIMOC (I/O) CANTXB (O)
11–10 GPIO21 EQEP1B (I) SPISOMIC (I/O) CANRXB (I)
13–12 GPIO22 EQEP1S (I/O) SPICLKC (I/O) SCITXDB (O)
15–14 GPIO23 EQEP1I (I/O) SPISTEC (I/O) SCIRXDB (I)
17–16 GPIO24 ECAP1 (I/O) EQEP2A (I) SPISIMOB (I/O)
19–18 GPIO25 ECAP2 (I/O) EQEP2B (I) SPISOMIB (I/O)
21–20 GPIO26 ECAP3 (I/O) EQEP2I (I/O) SPICLKB (I/O)
23–22 GPIO27 ECAP4 (I/O) EQEP2S (I/O) SPISTEB (I/O)
25–24 GPIO28 SCIRXDA (I) Reserved(2) TZ5 (I)
27–26 GPIO29 SCITXDA (O) Reserved(2) TZ6 (I)
29–28 GPIO30 CANRXA (I) Reserved(2) Reserved(2)
31–30 GPIO31 CANTXA (O) Reserved(2) Reserved(2)
GPBMUX1
1–0 GPIO32 SDAA (I/OC) EPWMSYNCI (I) ADCSOCAO (O)
3–2 GPIO33 SCLA (I/OC) EPWMSYNCO (O) ADCSOCBO (O)
5–4 GPIO34 Reserved(2) Reserved(2) Reserved(2)
(1) This table pertains to the 2808 device. Some peripherals may not be available in the 2809, 2806, 2802, or 2801 devices. See the pin descriptions for more detail.
(2) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.
(3) GPxMUX1/2 refers to the appropriate MUX register for the pin; GPAMUX1, GPAMUX2 or GPBMUX1.

The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices:

  • Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0,0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
  • Qualification Using Sampling Window (GPxQSEL1/2 = 0,1 and 1,0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change.
    • TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 qual_samp_prs230.gifFigure 6-17 Qualification Using Sampling Window
  • The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 5-11 (for 6-sample mode).
  • No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral).

Due to the multi-level multiplexing that is required on the 280x device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral.