JAJSHM4U April   2001  – July 2019 TMS320F2810 , TMS320F2811 , TMS320F2812

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT
      2. 5.5.1     Current Consumption Graphs
      3. 5.5.2     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics for 179-Ball ZHH Package
    8. 5.8  Thermal Resistance Characteristics for 179-Ball GHH Package
    9. 5.9  Thermal Resistance Characteristics for 176-Pin PGF Package
    10. 5.10 Thermal Resistance Characteristics for 128-Pin PBK Package
    11. 5.11 Thermal Design Considerations
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1 Timing Parameter Symbology
        1. 5.12.1.1 General Notes on Timing Parameters
        2. 5.12.1.2 Test Load Circuit
        3. 5.12.1.3 Signal Transition Levels
      2. 5.12.2 Power Supply Sequencing
      3. 5.12.3 Reset Timing
        1. Table 5-3 Reset (XRS) Timing Requirements
      4. 5.12.4 Clock Specifications
        1. 5.12.4.1 Device Clock Table
          1. Table 5-4 Clock Table and Nomenclature
        2. 5.12.4.2 Clock Requirements and Characteristics
          1. 5.12.4.2.1 Input Clock Requirements
            1. Table 5-5 Input Clock Frequency
            2. Table 5-6 XCLKIN Timing Requirements – PLL Bypassed or Enabled
            3. Table 5-7 XCLKIN Timing Requirements – PLL Disabled
          2. 5.12.4.2.2 Output Clock Characteristics
            1. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      5. 5.12.5 Peripherals
        1. 5.12.5.1  General-Purpose Input/Output (GPIO) – Output Timing
          1. Table 5-10 General-Purpose Output Switching Characteristics
        2. 5.12.5.2  General-Purpose Input/Output (GPIO) – Input Timing
          1. Table 5-11 General-Purpose Input Timing Requirements
        3. 5.12.5.3  Event Manager Interface
          1. 5.12.5.3.1 PWM Timing
            1. Table 5-12 PWM Switching Characteristics
            2. Table 5-13 Timer and Capture Unit Timing Requirements
            3. Table 5-14 External ADC Start-of-Conversion – EVA – Switching Characteristics
            4. Table 5-15 External ADC Start-of-Conversion – EVB – Switching Characteristics
        4. 5.12.5.4  Low-Power Mode Wakeup Timing
          1. Table 5-16 IDLE Mode Timing Requirements
          2. Table 5-17 IDLE Mode Switching Characteristics
          3. Table 5-18 STANDBY Mode Timing Requirements
          4. Table 5-19 STANDBY Mode Switching Characteristics
          5. Table 5-20 HALT Mode Timing Requirements
          6. Table 5-21 HALT Mode Switching Characteristics
        5. 5.12.5.5  Serial Peripheral Interface (SPI) Master Mode Timing
          1. Table 5-22 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 5-23 SPI Master Mode External Timing (Clock Phase = 1)
        6. 5.12.5.6  Serial Peripheral Interface (SPI) Slave Mode Timing
          1. Table 5-24 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 5-25 SPI Slave Mode External Timing (Clock Phase = 1)
        7. 5.12.5.7  External Interface (XINTF) Timing
          1. 5.12.5.7.1 USEREADY = 0
          2. 5.12.5.7.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
          3. 5.12.5.7.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        8. 5.12.5.8  XINTF Signal Alignment to XCLKOUT
        9. 5.12.5.9  External Interface Read Timing
          1. Table 5-28 External Memory Interface Read Switching Characteristics
          2. Table 5-29 External Memory Interface Read Timing Requirements
        10. 5.12.5.10 External Interface Write Timing
          1. Table 5-30 External Memory Interface Write Switching Characteristics
        11. 5.12.5.11 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-31 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
          2. Table 5-32 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
          3. Table 5-33 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
          4. Table 5-34 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
        12. 5.12.5.12 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-35 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
          2. Table 5-36 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
          3. Table 5-37 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
        13. 5.12.5.13 XHOLD and XHOLDA
        14. 5.12.5.14 XHOLD/XHOLDA Timing
          1. Table 5-38 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
          2. Table 5-39 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
        15. 5.12.5.15 On-Chip Analog-to-Digital Converter
          1. Table 5-40  ADC Absolute Maximum Ratings Over Recommended Operating Conditions (Unless Otherwise Noted)
          2. Table 5-41  ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—AC Specifications
          3. Table 5-42  ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—DC Specifications
          4. 5.12.5.15.1 Current Consumption for Different ADC Configurations
            1. Table 5-43 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
          5. 5.12.5.15.2 ADC Power-Up Control Bit Timing
            1. Table 5-44 ADC Power-Up Delays
          6. 5.12.5.15.3 Detailed Description
            1. 5.12.5.15.3.1 Reference Voltage
            2. 5.12.5.15.3.2 Analog Inputs
            3. 5.12.5.15.3.3 Converter
            4. 5.12.5.15.3.4 Conversion Modes
          7. 5.12.5.15.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
            1. Table 5-45 Sequential Sampling Mode Timing
          8. 5.12.5.15.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
            1. Table 5-46 Simultaneous Sampling Mode Timing
          9. 5.12.5.15.6 Definitions of Specifications and Terminology
        16. 5.12.5.16 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.12.5.16.1 McBSP Transmit and Receive Timing
            1. Table 5-47 McBSP Timing Requirements
            2. Table 5-48 McBSP Switching Characteristics
          2. 5.12.5.16.2 McBSP as SPI Master or Slave Timing
            1. Table 5-49 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-50 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-51 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-52 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-53 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-54 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-55 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-56 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      6. 5.12.6 Emulator Connection Without Signal Buffering for the DSP
      7. 5.12.7 Interrupt Timing
        1. Table 5-57 Interrupt Switching Characteristics
        2. Table 5-58 Interrupt Timing Requirements
      8. 5.12.8 Flash Timing
        1. Table 5-59 Flash Endurance for A and S Temperature Material
        2. Table 5-60 Flash Endurance for Q Temperature Material
        3. Table 5-61 Flash Parameters at 150-MHz SYSCLKOUT
        4. Table 5-62 Flash/OTP Access Timing
        5. Table 5-63 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1  Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF) (F2812 Only)
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0, L1, H0 SARAMs
      9. 6.1.9  Boot ROM
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12 External Interrupts (XINT1, XINT2, XINT13, XNMI)
      13. 6.1.13 Oscillator and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-Power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2 (PFn)
      18. 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2  Peripherals
      1. 6.2.1 32-Bit CPU-Timers 0/1/2
      2. 6.2.2 Event Manager Modules (EVA, EVB)
        1. 6.2.2.1 General-Purpose (GP) Timers
        2. 6.2.2.2 Full-Compare Units
        3. 6.2.2.3 Programmable Deadband Generator
        4. 6.2.2.4 PWM Waveform Generation
        5. 6.2.2.5 Double Update PWM Mode
        6. 6.2.2.6 PWM Characteristics
        7. 6.2.2.7 Capture Unit
        8. 6.2.2.8 Quadrature-Encoder Pulse (QEP) Circuit
        9. 6.2.2.9 External ADC Start-of-Conversion
      3. 6.2.3 Enhanced Analog-to-Digital Converter (ADC) Module
      4. 6.2.4 Enhanced Controller Area Network (eCAN) Module
      5. 6.2.5 Multichannel Buffered Serial Port (McBSP) Module
      6. 6.2.6 Serial Communications Interface (SCI) Module
      7. 6.2.7 Serial Peripheral Interface (SPI) Module
      8. 6.2.8 GPIO MUX
    3. 6.3  Memory Maps
    4. 6.4  Register Map
    5. 6.5  Device Emulation Registers
    6. 6.6  External Interface, XINTF (F2812 Only)
      1. 6.6.1 Timing Registers
      2. 6.6.2 XREVISION Register
    7. 6.7  Interrupts
      1. 6.7.1 External Interrupts
    8. 6.8  System Control
    9. 6.9  OSC and PLL Block
      1. 6.9.1 Loss of Input Clock
    10. 6.10 PLL-Based Clock Module
    11. 6.11 External Reference Oscillator Clock Option
    12. 6.12 Watchdog Block
    13. 6.13 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスおよび開発ツールの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PBK|128
サーマルパッド・メカニカル・データ
発注情報

2 改訂履歴

Changes from May 31, 2012 to July 12, 2019 (from T Revision (May 2012) to U Revision)

  • グローバル：ROM デバイス (TMS320C2810、TMS320C2811、TMS320C2812) を削除。C281x/ROM データを削除。Go
  • グローバル：ドキュメントを再構成。Go
  • グローバル：「Q100」を「AEC-Q100」に変更。Go
  • Section 1.1 (特長)：「クロックとシステム制御」の特長を更新。Go
  • Section 1.1：Q 温度オプションを更新。「[Q100 認定]」を「(車載アプリケーション用に AEC-Q100 認定)」に変更。Go
  • Section 1.2 (アプリケーション)：セクションを追加。Go
  • Section 1.3 (概要)：製品情報の表を追加。Go
  • Section 1.4 (機能ブロック図)：セクション・タイトルを追加。Go
  • Figure 1-1 (機能ブロック図)：ROM を削除。脚注を更新。Go
  • Section 3 (Device Comparison): Changed section title from "Device Summary" to "Device Comparison". Go
  • Table 3-1 (Device Comparison): Changed table title from "Hardware Features" to "Device Comparison".Go
  • Table 3-1: Removed C2810, C2811, and C2812 data.Go
  • Table 3-1: Removed "Product Status" row and its associated footnote. Go
  • Section 3.1 (Related Products): Added section.Go
  • Section 4 (Terminal Configuration and Functions): Changed section title from "Introduction" to "Terminal Configuration and Functions".Go
  • Section 4.1 (Pin Diagrams): Changed section title from "Pin Assignments" to "Pin Diagrams".Go
  • Table 4-1 (Signal Descriptions): Updated DESCRIPTION of XRS.Go
  • Table 4-1: Removed C281x/ROM data from DESCRIPTION of TEST1, TEST2, and VDD3VFL.Go
  • Section 5 (Specifications): Changed section title from "Electrical Specifications" to "Specifications". Go
  • Section 5.1 (Absolute Maximum Ratings): Updated "Long-term high-temperature storage ..." footnote. Go
  • Section 5.2 (ESD Ratings – Commercial): Added section. Go
  • Section 5.3 (ESD Ratings – Automotive): Added section. Go
  • Section 5.5 (Power Consumption Summary): Changed section title from "Current Consumption" to "Power Consumption Summary". Go
  • Table 5-2 (Typical Current Consumption by Various Peripherals (at 150 MHz)): Added footnote about achieving power savings. Go
  • Section 5.6 (Electrical Characteristics): Removed IIL for C281x devices. Go
  • Section 5.7 (Thermal Resistance Characteristics for 179-Ball ZHH Package): Added section. Go
  • Section 5.8 (Thermal Resistance Characteristics for 179-Ball GHH): Added section. Go
  • Section 5.9 (Thermal Resistance Characteristics for 176-Pin PGF Package): Added section. Go
  • Section 5.10 (Thermal Resistance Characteristics for 128-Pin PBK Package): Added section. Go
  • Section 5.11 (Thermal Design Considerations): Added section. Go
  • Section 5.12.2 (Power Supply Sequencing): Changed section title from "Power Sequencing Requirements" to "Power Supply Sequencing". Updated section. Removed "Recommended “Low-Dropout Regulators”" table. Removed C281x data.Go
  • Section 5.12.4 (Clock Specifications): Added section title. Go
  • Section 5.12.5 (Peripherals): Added section title. Go
  • Figure 5-14 (General-Purpose Input Timing): Replaced "XCLKOUT" with "SYSCLK".Go
  • Section 5.12.5.5 (Serial Peripheral Interface (SPI) Master Mode Timing): Updated section. Go
  • Section 5.12.5.6 (Serial Peripheral Interface (SPI) Slave Mode Timing): Updated section. Go
  • Section 5.12.5.7.2 (Synchronous Mode (USEREADY = 1, READYMODE = 0)): Updated "XTIMING register configuration restrictions" table by changing XRDACTIVE value from "≥ 1" to "≥ 2" and XWRACTIVE value from "≥ 1" to "≥ 2".Go
  • Section 5.12.5.7.2 (Synchronous Mode (USEREADY = 1, READYMODE = 0)): Updated "Examples of valid and invalid timing" table by changing Valid XRDACTIVE value from "1" to "2" and Valid XWRACTIVE value from "1" to "2".Go
  • Section 5.12.5.7.3 (Asynchronous Mode (USEREADY = 1, READYMODE = 1)): Updated second "XTIMING register configuration restrictions" table by changing XRDACTIVE value from "≥ 1" to "≥ 2" and XWRACTIVE value from "≥ 1" to "≥ 2".Go
  • Section 5.12.5.7.3 (Asynchronous Mode (USEREADY = 1, READYMODE = 1)): Updated "Examples of valid and invalid timing" table by changing Valid XRDACTIVE value from "1" to "2" and Valid XWRACTIVE value from "1" to "2".Go
  • Table 5-40 (ADC Absolute Maximum Ratings Over Recommended Operating Conditions (Unless Otherwise Noted)): Updated table. Go
  • Table 5-41 (ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—AC Specifications): Changed table title from "AC Specifications" to "ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—AC Specifications". Go
  • Table 5-42 (ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—DC Specifications): Changed table title from "DC Specifications" to "ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—DC Specifications". Go
  • Table 5-42: Removed C281x data. Go
  • Table 5-49 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)): Updated footnotes. Go
  • Table 5-50 (McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)): Updated footnote. Go
  • Table 5-51 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)): Updated footnotes. Go
  • Table 5-52 (McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)): Updated footnote. Go
  • Table 5-53 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)): Updated footnotes. Go
  • Table 5-54 (McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)): Updated footnote. Go
  • Table 5-55 (McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)): Updated footnotes. Go
  • Table 5-56 (McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)): Updated footnote. Go
  • Table 5-61 (Flash Parameters at 150-MHz SYSCLKOUT): Updated "Typical parameters as seen at room temperature ..." footnote. Go
  • Table 5-63 (Flash Data Retention Duration): Added table. Go
  • Section 6 (Detailed Description): Changed section title from "Functional Overview" to "Detailed Description".Go
  • Section 6.1.21 (Serial Port Peripherals): Updated description of eCAN. Go
  • Section 6.2.3 (Enhanced Analog-to-Digital Converter (ADC) Module): Updated equations by which the digital value of the input analog voltage is derived. Go
  • Section 6.2.4 (Enhanced Controller Area Network (eCAN) Module): Updated feature about CAN 2.0B. Go
  • Section 6.2.7 (Serial Peripheral Interface (SPI) Module): Updated "Rising edge with phase delay" clocking scheme.Go
  • Figure 6-22 (Watchdog Module): Updated figure. Go
  • Section 7 (Applications, Implementation, and Layout): Added section.Go
  • Section 8 (デバイスおよびドキュメントのサポート)：タイトルを「開発サポート」から「デバイスおよびドキュメントのサポート」に変更。Go
  • Section 8.1 (はじめに)：セクションを更新。Go
  • Figure 8-1 (TMS320F281x デバイスの項目表記)：Q 温度範囲の説明を更新。Go
  • Section 8.3 (ツールとソフトウェア)：セクションを追加。Go
  • Section 8.4 (ドキュメントのサポート)：セクションを更新。Go
  • Section 8.5 (関連リンク)：セクションを追加。Go
  • Section 9 (メカニカル、パッケージ、および注文情報)：「メカニカル・データ」セクションを「メカニカル、パッケージ、および注文情報」セクションに置き換え。Go