JAJSHM4U April   2001  – July 2019 TMS320F2810 , TMS320F2811 , TMS320F2812

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT
      2. 5.5.1     Current Consumption Graphs
      3. 5.5.2     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics for 179-Ball ZHH Package
    8. 5.8  Thermal Resistance Characteristics for 179-Ball GHH Package
    9. 5.9  Thermal Resistance Characteristics for 176-Pin PGF Package
    10. 5.10 Thermal Resistance Characteristics for 128-Pin PBK Package
    11. 5.11 Thermal Design Considerations
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1 Timing Parameter Symbology
        1. 5.12.1.1 General Notes on Timing Parameters
        2. 5.12.1.2 Test Load Circuit
        3. 5.12.1.3 Signal Transition Levels
      2. 5.12.2 Power Supply Sequencing
      3. 5.12.3 Reset Timing
        1. Table 5-3 Reset (XRS) Timing Requirements
      4. 5.12.4 Clock Specifications
        1. 5.12.4.1 Device Clock Table
          1. Table 5-4 Clock Table and Nomenclature
        2. 5.12.4.2 Clock Requirements and Characteristics
          1. 5.12.4.2.1 Input Clock Requirements
            1. Table 5-5 Input Clock Frequency
            2. Table 5-6 XCLKIN Timing Requirements – PLL Bypassed or Enabled
            3. Table 5-7 XCLKIN Timing Requirements – PLL Disabled
          2. 5.12.4.2.2 Output Clock Characteristics
            1. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      5. 5.12.5 Peripherals
        1. 5.12.5.1  General-Purpose Input/Output (GPIO) – Output Timing
          1. Table 5-10 General-Purpose Output Switching Characteristics
        2. 5.12.5.2  General-Purpose Input/Output (GPIO) – Input Timing
          1. Table 5-11 General-Purpose Input Timing Requirements
        3. 5.12.5.3  Event Manager Interface
          1. 5.12.5.3.1 PWM Timing
            1. Table 5-12 PWM Switching Characteristics
            2. Table 5-13 Timer and Capture Unit Timing Requirements
            3. Table 5-14 External ADC Start-of-Conversion – EVA – Switching Characteristics
            4. Table 5-15 External ADC Start-of-Conversion – EVB – Switching Characteristics
        4. 5.12.5.4  Low-Power Mode Wakeup Timing
          1. Table 5-16 IDLE Mode Timing Requirements
          2. Table 5-17 IDLE Mode Switching Characteristics
          3. Table 5-18 STANDBY Mode Timing Requirements
          4. Table 5-19 STANDBY Mode Switching Characteristics
          5. Table 5-20 HALT Mode Timing Requirements
          6. Table 5-21 HALT Mode Switching Characteristics
        5. 5.12.5.5  Serial Peripheral Interface (SPI) Master Mode Timing
          1. Table 5-22 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 5-23 SPI Master Mode External Timing (Clock Phase = 1)
        6. 5.12.5.6  Serial Peripheral Interface (SPI) Slave Mode Timing
          1. Table 5-24 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 5-25 SPI Slave Mode External Timing (Clock Phase = 1)
        7. 5.12.5.7  External Interface (XINTF) Timing
          1. 5.12.5.7.1 USEREADY = 0
          2. 5.12.5.7.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
          3. 5.12.5.7.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        8. 5.12.5.8  XINTF Signal Alignment to XCLKOUT
        9. 5.12.5.9  External Interface Read Timing
          1. Table 5-28 External Memory Interface Read Switching Characteristics
          2. Table 5-29 External Memory Interface Read Timing Requirements
        10. 5.12.5.10 External Interface Write Timing
          1. Table 5-30 External Memory Interface Write Switching Characteristics
        11. 5.12.5.11 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-31 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
          2. Table 5-32 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
          3. Table 5-33 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
          4. Table 5-34 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
        12. 5.12.5.12 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-35 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
          2. Table 5-36 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
          3. Table 5-37 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
        13. 5.12.5.13 XHOLD and XHOLDA
        14. 5.12.5.14 XHOLD/XHOLDA Timing
          1. Table 5-38 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
          2. Table 5-39 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
        15. 5.12.5.15 On-Chip Analog-to-Digital Converter
          1. Table 5-40  ADC Absolute Maximum Ratings Over Recommended Operating Conditions (Unless Otherwise Noted)
          2. Table 5-41  ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—AC Specifications
          3. Table 5-42  ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—DC Specifications
          4. 5.12.5.15.1 Current Consumption for Different ADC Configurations
            1. Table 5-43 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
          5. 5.12.5.15.2 ADC Power-Up Control Bit Timing
            1. Table 5-44 ADC Power-Up Delays
          6. 5.12.5.15.3 Detailed Description
            1. 5.12.5.15.3.1 Reference Voltage
            2. 5.12.5.15.3.2 Analog Inputs
            3. 5.12.5.15.3.3 Converter
            4. 5.12.5.15.3.4 Conversion Modes
          7. 5.12.5.15.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
            1. Table 5-45 Sequential Sampling Mode Timing
          8. 5.12.5.15.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
            1. Table 5-46 Simultaneous Sampling Mode Timing
          9. 5.12.5.15.6 Definitions of Specifications and Terminology
        16. 5.12.5.16 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.12.5.16.1 McBSP Transmit and Receive Timing
            1. Table 5-47 McBSP Timing Requirements
            2. Table 5-48 McBSP Switching Characteristics
          2. 5.12.5.16.2 McBSP as SPI Master or Slave Timing
            1. Table 5-49 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-50 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-51 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-52 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-53 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-54 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-55 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-56 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      6. 5.12.6 Emulator Connection Without Signal Buffering for the DSP
      7. 5.12.7 Interrupt Timing
        1. Table 5-57 Interrupt Switching Characteristics
        2. Table 5-58 Interrupt Timing Requirements
      8. 5.12.8 Flash Timing
        1. Table 5-59 Flash Endurance for A and S Temperature Material
        2. Table 5-60 Flash Endurance for Q Temperature Material
        3. Table 5-61 Flash Parameters at 150-MHz SYSCLKOUT
        4. Table 5-62 Flash/OTP Access Timing
        5. Table 5-63 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1  Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF) (F2812 Only)
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0, L1, H0 SARAMs
      9. 6.1.9  Boot ROM
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12 External Interrupts (XINT1, XINT2, XINT13, XNMI)
      13. 6.1.13 Oscillator and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-Power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2 (PFn)
      18. 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2  Peripherals
      1. 6.2.1 32-Bit CPU-Timers 0/1/2
      2. 6.2.2 Event Manager Modules (EVA, EVB)
        1. 6.2.2.1 General-Purpose (GP) Timers
        2. 6.2.2.2 Full-Compare Units
        3. 6.2.2.3 Programmable Deadband Generator
        4. 6.2.2.4 PWM Waveform Generation
        5. 6.2.2.5 Double Update PWM Mode
        6. 6.2.2.6 PWM Characteristics
        7. 6.2.2.7 Capture Unit
        8. 6.2.2.8 Quadrature-Encoder Pulse (QEP) Circuit
        9. 6.2.2.9 External ADC Start-of-Conversion
      3. 6.2.3 Enhanced Analog-to-Digital Converter (ADC) Module
      4. 6.2.4 Enhanced Controller Area Network (eCAN) Module
      5. 6.2.5 Multichannel Buffered Serial Port (McBSP) Module
      6. 6.2.6 Serial Communications Interface (SCI) Module
      7. 6.2.7 Serial Peripheral Interface (SPI) Module
      8. 6.2.8 GPIO MUX
    3. 6.3  Memory Maps
    4. 6.4  Register Map
    5. 6.5  Device Emulation Registers
    6. 6.6  External Interface, XINTF (F2812 Only)
      1. 6.6.1 Timing Registers
      2. 6.6.2 XREVISION Register
    7. 6.7  Interrupts
      1. 6.7.1 External Interrupts
    8. 6.8  System Control
    9. 6.9  OSC and PLL Block
      1. 6.9.1 Loss of Input Clock
    10. 6.10 PLL-Based Clock Module
    11. 6.11 External Reference Oscillator Clock Option
    12. 6.12 Watchdog Block
    13. 6.13 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスおよび開発ツールの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PBK|128
サーマルパッド・メカニカル・データ
発注情報

4.2 Signal Descriptions

Table 4-1 specifies the signals on the F281x devices. All digital inputs are TTL-compatible. All outputs are 3.3 V with CMOS levels. Inputs are not 5-V tolerant. A 100-µA (or 20-µA) pullup/pulldown is used.

Table 4-1 Signal Descriptions(1)

NAME PIN NO. I/O/Z(2) PU/PD(3) DESCRIPTION
179-BALL
GHH/ZHH		 176-PIN
PGF		 128-PIN
PBK
XINTF SIGNALS (F2812 ONLY)
XA[18] D7 158 – O/Z – 19-bit XINTF Address Bus
XA[17] B7 156 – O/Z –
XA[16] A8 152 – O/Z –
XA[15] B9 148 – O/Z –
XA[14] A10 144 – O/Z –
XA[13] E10 141 – O/Z –
XA[12] C11 138 – O/Z –
XA[11] A14 132 – O/Z –
XA[10] C12 130 – O/Z –
XA[9] D14 125 – O/Z –
XA[8] E12 121 – O/Z –
XA[7] F12 118 – O/Z –
XA[6] G14 111 – O/Z –
XA[5] H13 108 – O/Z –
XA[4] J12 103 – O/Z –
XA[3] M11 85 – O/Z –
XA[2] N10 80 – O/Z –
XA[1] M2 43 – O/Z –
XA[0] G5 18 – O/Z –
XD[15] A9 147 – I/O/Z PU 16-bit XINTF Data Bus
XD[14] B11 139 – I/O/Z PU
XD[13] J10 97 – I/O/Z PU
XD[12] L14 96 – I/O/Z PU
XD[11] N9 74 – I/O/Z PU
XD[10] L9 73 – I/O/Z PU
XD[9] M8 68 – I/O/Z PU
XD[8] P7 65 – I/O/Z PU
XD[7] L5 54 – I/O/Z PU
XD[6] L3 39 – I/O/Z PU
XD[5] J5 36 – I/O/Z PU
XD[4] K3 33 – I/O/Z PU
XD[3] J3 30 – I/O/Z PU
XD[2] H5 27 – I/O/Z PU
XD[1] H3 24 – I/O/Z PU
XD[0] G3 21 – I/O/Z PU
XMP/MC F1 17 – I PD Microprocessor/Microcomputer Mode Select. Switches between microprocessor and microcomputer mode. When high, Zone 7 is enabled on the external interface. When low, Zone 7 is disabled from the external interface, and on-chip boot ROM may be accessed instead. This signal is latched into the XINTCNF2 register on a reset and the user can modify this bit in software. The state of the XMP/MC pin is ignored after reset.
XHOLD E7 159 – I PU External Hold Request. XHOLD, when active (low), requests the XINTF to release the external bus and place all buses and strobes into a high-impedance state. The XINTF will release the bus when any current access is complete and there are no pending accesses on the XINTF.
XHOLDA K10 82 – O/Z – External Hold Acknowledge. XHOLDA is driven active (low) when the XINTF has granted a XHOLD request. All XINTF buses and strobe signals will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low).
XZCS0AND1 P1 44 – O/Z – XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active (low) when an access to the XINTF Zone 0 or Zone 1 is performed.
XZCS2 P13 88 – O/Z – XINTF Zone 2 Chip Select. XZCS2 is active (low) when an access to the XINTF Zone 2 is performed.
XZCS6AND7 B13 133 – O/Z – XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active (low) when an access to the XINTF Zone 6 or Zone 7 is performed.
XWE N11 84 – O/Z – Write Enable. Active-low write strobe. The write strobe waveform is specified, per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers.
XRD M3 42 – O/Z – Read Enable. Active-low read strobe. The read strobe waveform is specified, per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers. NOTE: The XRD and XWE signals are mutually exclusive.
XR/W N4 51 – O/Z – Read Not Write Strobe. Normally held high. When low, XR/W indicates write cycle is active; when high, XR/W indicates read cycle is active.
XREADY B6 161 – I PU Ready Signal. Indicates peripheral is ready to complete the access when asserted to 1. XREADY can be configured to be a synchronous or an asynchronous input. See the timing diagrams for more details.
JTAG AND MISCELLANEOUS SIGNALS
X1/XCLKIN K9 77 58 I – Oscillator Input – input to the internal oscillator. This pin is also used to feed an external clock. The 28x can be operated with an external clock source, provided that the proper voltage levels be driven on the X1/XCLKIN pin. It should be noted that the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core digital power supply (VDD), rather than the 3.3-V I/O supply (VDDIO). A clamping diode may be used to clamp a buffered clock signal to ensure that the logic-high level does not exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator may be used.
X2 M9 76 57 O – Oscillator Output
XCLKOUT F11 119 87 O – Output clock derived from SYSCLKOUT to be used for external wait-state generation and as a general-purpose clock source. XCLKOUT is either the same frequency, 1/2 the frequency, or 1/4 the frequency of SYSCLKOUT. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in a high-impedance state during reset.
TESTSEL A13 134 97 I PD Test Pin. Reserved for TI. Must be connected to ground.
XRS D6 160 113 I/O PU Device Reset (in) and Watchdog Reset (out).

Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the XRS pin will be driven low for the watchdog reset duration of 512 XCLKIN cycles.

The output buffer of this pin is an open-drain with an internal pullup (100 µA, typical). If this pin is driven by an external device, it should be done using an open-drain device.
TEST1 M7 67 51 I/O – Test Pin. Reserved for TI. On F281x devices, TEST1 must be left unconnected.
TEST2 N7 66 50 I/O – Test Pin. Reserved for TI. On F281x devices, TEST2 must be left unconnected.
JTAG
TRST B12 135 98 I PD JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.

NOTE: Do not use pullup resistors on TRST; it has an internal pulldown device. TRST is an active-high test pin and must be maintained low at all times during normal device operation. In a low-noise environment, TRST may be left floating. In other instances, an external pulldown resistor is highly recommended. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.
TCK A12 136 99 I PU JTAG test clock with internal pullup
TMS D13 126 92 I PU JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK.
TDI C13 131 96 I PU JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK.
TDO D12 127 93 O/Z – JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK.
EMU0 D11 137 100 I/O/Z PU Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.
EMU1 C9 146 105 I/O/Z PU Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.

NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application.
ADC ANALOG INPUT SIGNALS
ADCINA7 B5 167 119 I – 8-channel analog inputs for
Sample-and-Hold A. The ADC pins should not be driven before the VDDA1, VDDA2, and VDDAIO pins have been fully powered up.
ADCINA6 D5 168 120 I –
ADCINA5 E5 169 121 I –
ADCINA4 A4 170 122 I –
ADCINA3 B4 171 123 I –
ADCINA2 C4 172 124 I –
ADCINA1 D4 173 125 I –
ADCINA0 A3 174 126 I –
ADCINB7 F5 9 9 I – 8-channel analog inputs for
Sample-and-Hold B. The ADC pins should not be driven before the VDDA1, VDDA2, and VDDAIO pins have been fully powered up.
ADCINB6 D1 8 8 I –
ADCINB5 D2 7 7 I –
ADCINB4 D3 6 6 I –
ADCINB3 C1 5 5 I –
ADCINB2 B1 4 4 I –
ADCINB1 C3 3 3 I –
ADCINB0 C2 2 2 I –
ADCREFP E2 11 11 I/O – ADC Voltage Reference Output (2 V). Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of 10 µF to analog ground.
[Can accept external reference input (2 V) if the software bit is enabled for this mode. 1–10 µF low ESR capacitor can be used in the external reference mode.]
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system.
ADCREFM E4 10 10 I/O – ADC Voltage Reference Output (1 V). Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of 10 µF to analog ground.
[Can accept external reference input (1 V) if the software bit is enabled for this mode. 1–10 µF low ESR capacitor can be used in the external reference mode.]
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system.
ADCRESEXT F2 16 16 O – ADC External Current Bias Resistor.

Use 24.9 kΩ ± 5% for ADC clock range 1–18.75 MHz; use 20 kΩ ± 5% for ADC clock range 18.75 MHz–25 MHz.
ADCBGREFIN E6 164 116 – – Test Pin. Reserved for TI. Must be left unconnected.
AVSSREFBG E3 12 12 – – ADC Analog GND
AVDDREFBG E1 13 13 – – ADC Analog Power (3.3-V)
ADCLO B3 175 127 – – Common Low Side Analog Input. Connect to analog ground.
VSSA1 F3 15 15 – – ADC Analog GND
VSSA2 C5 165 117 – – ADC Analog GND
VDDA1 F4 14 14 – – ADC Analog 3.3-V Supply
VDDA2 A5 166 118 – – ADC Analog 3.3-V Supply
VSS1 C6 163 115 – – ADC Digital GND
VDD1 A6 162 114 – – ADC Digital 1.8-V (or 1.9-V) Supply
VDDAIO B2 1 1 – – 3.3-V Analog I/O Power Pin
VSSAIO A2 176 128 – – Analog I/O Ground Pin
POWER SIGNALS
VDD H1 23 20 – – 1.8-V or 1.9-V Core Digital Power Pins. See Section 5.4, Recommended Operating Conditions, for voltage requirements.
VDD L1 37 29 – –
VDD P5 56 42 – –
VDD P9 75 56 – –
VDD P12 – 63 – –
VDD K12 100 74 – –
VDD G12 112 82 – –
VDD C14 128 94 – –
VDD B10 143 102 – –
VDD C8 154 110 – –
VSS G4 19 17 – – Core and Digital I/O Ground Pins
VSS K1 32 26 – –
VSS L2 38 30 – –
VSS P4 52 39 – –
VSS K6 58 – – –
VSS P8 70 53 – –
VSS M10 78 59 – –
VSS L11 86 62 – –
VSS K13 99 73 – –
VSS J14 105 – – –
VSS G13 113 – – –
VSS E14 120 88 – –
VSS B14 129 95 – –
VSS D10 142 – – –
VSS C10 – 103 – –
VSS B8 153 109 – –
VDDIO J4 31 25 – – 3 3-V I/O Digital Power Pins
VDDIO L7 64 49 – –
VDDIO L10 81 – – –
VDDIO N14 – – – –
VDDIO G11 114 83 – –
VDDIO E9 145 104 – –
VDD3VFL N8 69 52 – – 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times after power-up sequence requirements have been met.
GPIO OR PERIPHERAL SIGNALS
GPIOA OR EVA SIGNALS
GPIOA0 - PWM1 (O) M12 92 68 I/O PU GPIO or PWM Output Pin #1
GPIOA1 - PWM2 (O) M14 93 69 I/O PU GPIO or PWM Output Pin #2
GPIOA2 - PWM3 (O) L12 94 70 I/O PU GPIO or PWM Output Pin #3
GPIOA3 - PWM4 (O) L13 95 71 I/O PU GPIO or PWM Output Pin #4
GPIOA4 - PWM5 (O) K11 98 72 I/O PU GPIO or PWM Output Pin #5
GPIOA5 - PWM6 (O) K14 101 75 I/O PU GPIO or PWM Output Pin #6
GPIOA6 - T1PWM_T1CMP (I) J11 102 76 I/O PU GPIO or Timer 1 Output
GPIOA7 - T2PWM_T2CMP (I) J13 104 77 I/O PU GPIO or Timer 2 Output
GPIOA8 - CAP1_QEP1 (I) H10 106 78 I/O PU GPIO or Capture Input #1
GPIOA9 - CAP2_QEP2 (I) H11 107 79 I/O PU GPIO or Capture Input #2
GPIOA10 - CAP3_QEPI1 (I) H12 109 80 I/O PU GPIO or Capture Input #3
GPIOA11 - TDIRA (I) F14 116 85 I/O PU GPIO or Timer Direction
GPIOA12 - TCLKINA (I) F13 117 86 I/O PU GPIO or Timer Clock Input
GPIOA13 - C1TRIP (I) E13 122 89 I/O PU GPIO or Compare 1 Output Trip
GPIOA14 - C2TRIP (I) E11 123 90 I/O PU GPIO or Compare 2 Output Trip
GPIOA15 - C3TRIP (I) F10 124 91 I/O PU GPIO or Compare 3 Output Trip
GPIOB OR EVB SIGNALS
GPIOB0 - PWM7 (O) N2 45 33 I/O PU GPIO or PWM Output Pin #7
GPIOB1 - PWM8 (O) P2 46 34 I/O PU GPIO or PWM Output Pin #8
GPIOB2 - PWM9 (O) N3 47 35 I/O PU GPIO or PWM Output Pin #9
GPIOB3 - PWM10 (O) P3 48 36 I/O PU GPIO or PWM Output Pin #10
GPIOB4 - PWM11 (O) L4 49 37 I/O PU GPIO or PWM Output Pin #11
GPIOB5 - PWM12 (O) M4 50 38 I/O PU GPIO or PWM Output Pin #12
GPIOB6 - T3PWM_T3CMP (I) K5 53 40 I/O PU GPIO or Timer 3 Output
GPIOB7 - T4PWM_T4CMP (I) N5 55 41 I/O PU GPIO or Timer 4 Output
GPIOB8 - CAP4_QEP3 (I) M5 57 43 I/O PU GPIO or Capture Input #4
GPIOB9 - CAP5_QEP4 (I) M6 59 44 I/O PU GPIO or Capture Input #5
GPIOB10 - CAP6_QEPI2 (I) P6 60 45 I/O PU GPIO or Capture Input #6
GPIOB11 - TDIRB (I) L8 71 54 I/O PU GPIO or Timer Direction
GPIOB12 - TCLKINB (I) K8 72 55 I/O PU GPIO or Timer Clock Input
GPIOB13 - C4TRIP (I) N6 61 46 I/O PU GPIO or Compare 4 Output Trip
GPIOB14 - C5TRIP (I) L6 62 47 I/O PU GPIO or Compare 5 Output Trip
GPIOB15 - C6TRIP (I) K7 63 48 I/O PU GPIO or Compare 6 Output Trip
GPIOD OR EVA SIGNALS
GPIOD0 - T1CTRIP_PDPINTA (I) H14 110 81 I/O PU GPIO or Timer 1 Compare Output Trip
GPIOD1 - T2CTRIP/EVASOC (I) G10 115 84 I/O PU GPIO or Timer 2 Compare Output Trip or External ADC Start-of-Conversion EV-A
GPIOD OR EVB SIGNALS
GPIOD5 - T3CTRIP_PDPINTB (I) P10 79 60 I/O PU GPIO or Timer 3 Compare Output Trip
GPIOD6 - T4CTRIP/EVBSOC (I) P11 83 61 I/O PU GPIO or Timer 4 Compare Output Trip or External ADC Start-of-Conversion EV-B
GPIOE OR INTERRUPT SIGNALS
GPIOE0 - XINT1_XBIO (I) D9 149 106 I/O/Z – GPIO or XINT1 or XBIO input
GPIOE1 - XINT2_ADCSOC (I) D8 151 108 I/O/Z – GPIO or XINT2 or ADC start-of-conversion
GPIOE2 - XNMI_XINT13 (I) E8 150 107 I/O PU GPIO or XNMI or XINT13
GPIOF OR SPI SIGNALS
GPIOF0 - SPISIMOA (O) M1 40 31 I/O/Z – GPIO or SPI slave in, master out
GPIOF1 - SPISOMIA (I) N1 41 32 I/O/Z – GPIO or SPI slave out, master in
GPIOF2 - SPICLKA (I/O) K2 34 27 I/O/Z – GPIO or SPI clock
GPIOF3 - SPISTEA (I/O) K4 35 28 I/O/Z – GPIO or SPI slave transmit enable
GPIOF OR SCI-A SIGNALS
GPIOF4 - SCITXDA (O) C7 155 111 I/O PU GPIO or SCI asynchronous serial port TX data
GPIOF5 - SCIRXDA (I) A7 157 112 I/O PU GPIO or SCI asynchronous serial port RX data
GPIOF OR CAN SIGNALS
GPIOF6 - CANTXA (O) N12 87 64 I/O PU GPIO or eCAN transmit data
GPIOF7 - CANRXA (I) N13 89 65 I/O PU GPIO or eCAN receive data
GPIOF OR McBSP SIGNALS
GPIOF8 - MCLKXA (I/O) J1 28 23 I/O PU GPIO or McBSP transmit clock
GPIOF9 - MCLKRA (I/O) H2 25 21 I/O PU GPIO or McBSP receive clock
GPIOF10 - MFSXA (I/O) H4 26 22 I/O PU GPIO or McBSP transmit frame synch
GPIOF11 - MFSRA (I/O) J2 29 24 I/O PU GPIO or McBSP receive frame synch
GPIOF12 - MDXA (O) G1 22 19 I/O – GPIO or McBSP transmitted serial data
GPIOF13 - MDRA (I) G2 20 18 I/O PU GPIO or McBSP received serial data
GPIOF OR XF CPU OUTPUT SIGNAL
GPIOF14 - XF_XPLLDIS (O) A11 140 101 I/O PU This pin has three functions:
  1. XF – General-purpose output pin.
  2. XPLLDIS – This pin is sampled during reset to check whether the PLL must be disabled. The PLL will be disabled if this pin is sensed low. HALT and STANDBY modes cannot be used when the PLL is disabled.
  3. GPIO – GPIO function
GPIOG OR SCI-B SIGNALS
GPIOG4 - SCITXDB (O) P14 90 66 I/O/Z – GPIO or SCI asynchronous serial port transmit data
GPIOG5 - SCIRXDB (I) M13 91 67 I/O/Z – GPIO or SCI asynchronous serial port receive data
(1) Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
(2) I = Input, O = Output, Z = High impedance
(3) PU = pin has internal pullup; PD = pin has internal pulldown. Pullup/pulldown strength is given in Section 5.6, Electrical Characteristics Over Recommended Operating Conditions. The pullups/pulldowns are enabled in boundary scan mode.

NOTE

Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached recommended operating conditions. However, it is acceptable for an I/O pin to ramp along with the 3.3-V supply.