JAJSHM4U April   2001  – July 2019 TMS320F2810 , TMS320F2811 , TMS320F2812

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F281x Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT
      2. 5.5.1     Current Consumption Graphs
      3. 5.5.2     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics for 179-Ball ZHH Package
    8. 5.8  Thermal Resistance Characteristics for 179-Ball GHH Package
    9. 5.9  Thermal Resistance Characteristics for 176-Pin PGF Package
    10. 5.10 Thermal Resistance Characteristics for 128-Pin PBK Package
    11. 5.11 Thermal Design Considerations
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1 Timing Parameter Symbology
        1. 5.12.1.1 General Notes on Timing Parameters
        2. 5.12.1.2 Test Load Circuit
        3. 5.12.1.3 Signal Transition Levels
      2. 5.12.2 Power Supply Sequencing
      3. 5.12.3 Reset Timing
        1. Table 5-3 Reset (XRS) Timing Requirements
      4. 5.12.4 Clock Specifications
        1. 5.12.4.1 Device Clock Table
          1. Table 5-4 Clock Table and Nomenclature
        2. 5.12.4.2 Clock Requirements and Characteristics
          1. 5.12.4.2.1 Input Clock Requirements
            1. Table 5-5 Input Clock Frequency
            2. Table 5-6 XCLKIN Timing Requirements – PLL Bypassed or Enabled
            3. Table 5-7 XCLKIN Timing Requirements – PLL Disabled
          2. 5.12.4.2.2 Output Clock Characteristics
            1. Table 5-9 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      5. 5.12.5 Peripherals
        1. 5.12.5.1  General-Purpose Input/Output (GPIO) – Output Timing
          1. Table 5-10 General-Purpose Output Switching Characteristics
        2. 5.12.5.2  General-Purpose Input/Output (GPIO) – Input Timing
          1. Table 5-11 General-Purpose Input Timing Requirements
        3. 5.12.5.3  Event Manager Interface
          1. 5.12.5.3.1 PWM Timing
            1. Table 5-12 PWM Switching Characteristics
            2. Table 5-13 Timer and Capture Unit Timing Requirements
            3. Table 5-14 External ADC Start-of-Conversion – EVA – Switching Characteristics
            4. Table 5-15 External ADC Start-of-Conversion – EVB – Switching Characteristics
        4. 5.12.5.4  Low-Power Mode Wakeup Timing
          1. Table 5-16 IDLE Mode Timing Requirements
          2. Table 5-17 IDLE Mode Switching Characteristics
          3. Table 5-18 STANDBY Mode Timing Requirements
          4. Table 5-19 STANDBY Mode Switching Characteristics
          5. Table 5-20 HALT Mode Timing Requirements
          6. Table 5-21 HALT Mode Switching Characteristics
        5. 5.12.5.5  Serial Peripheral Interface (SPI) Master Mode Timing
          1. Table 5-22 SPI Master Mode External Timing (Clock Phase = 0)
          2. Table 5-23 SPI Master Mode External Timing (Clock Phase = 1)
        6. 5.12.5.6  Serial Peripheral Interface (SPI) Slave Mode Timing
          1. Table 5-24 SPI Slave Mode External Timing (Clock Phase = 0)
          2. Table 5-25 SPI Slave Mode External Timing (Clock Phase = 1)
        7. 5.12.5.7  External Interface (XINTF) Timing
          1. 5.12.5.7.1 USEREADY = 0
          2. 5.12.5.7.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
          3. 5.12.5.7.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        8. 5.12.5.8  XINTF Signal Alignment to XCLKOUT
        9. 5.12.5.9  External Interface Read Timing
          1. Table 5-28 External Memory Interface Read Switching Characteristics
          2. Table 5-29 External Memory Interface Read Timing Requirements
        10. 5.12.5.10 External Interface Write Timing
          1. Table 5-30 External Memory Interface Write Switching Characteristics
        11. 5.12.5.11 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-31 External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)
          2. Table 5-32 External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)
          3. Table 5-33 Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
          4. Table 5-34 Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)
        12. 5.12.5.12 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-35 External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)
          2. Table 5-36 Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
          3. Table 5-37 Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)
        13. 5.12.5.13 XHOLD and XHOLDA
        14. 5.12.5.14 XHOLD/XHOLDA Timing
          1. Table 5-38 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
          2. Table 5-39 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
        15. 5.12.5.15 On-Chip Analog-to-Digital Converter
          1. Table 5-40  ADC Absolute Maximum Ratings Over Recommended Operating Conditions (Unless Otherwise Noted)
          2. Table 5-41  ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—AC Specifications
          3. Table 5-42  ADC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted)—DC Specifications
          4. 5.12.5.15.1 Current Consumption for Different ADC Configurations
            1. Table 5-43 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
          5. 5.12.5.15.2 ADC Power-Up Control Bit Timing
            1. Table 5-44 ADC Power-Up Delays
          6. 5.12.5.15.3 Detailed Description
            1. 5.12.5.15.3.1 Reference Voltage
            2. 5.12.5.15.3.2 Analog Inputs
            3. 5.12.5.15.3.3 Converter
            4. 5.12.5.15.3.4 Conversion Modes
          7. 5.12.5.15.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
            1. Table 5-45 Sequential Sampling Mode Timing
          8. 5.12.5.15.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
            1. Table 5-46 Simultaneous Sampling Mode Timing
          9. 5.12.5.15.6 Definitions of Specifications and Terminology
        16. 5.12.5.16 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.12.5.16.1 McBSP Transmit and Receive Timing
            1. Table 5-47 McBSP Timing Requirements
            2. Table 5-48 McBSP Switching Characteristics
          2. 5.12.5.16.2 McBSP as SPI Master or Slave Timing
            1. Table 5-49 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-50 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-51 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-52 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-53 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-54 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-55 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-56 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      6. 5.12.6 Emulator Connection Without Signal Buffering for the DSP
      7. 5.12.7 Interrupt Timing
        1. Table 5-57 Interrupt Switching Characteristics
        2. Table 5-58 Interrupt Timing Requirements
      8. 5.12.8 Flash Timing
        1. Table 5-59 Flash Endurance for A and S Temperature Material
        2. Table 5-60 Flash Endurance for Q Temperature Material
        3. Table 5-61 Flash Parameters at 150-MHz SYSCLKOUT
        4. Table 5-62 Flash/OTP Access Timing
        5. Table 5-63 Flash Data Retention Duration
  6. 6Detailed Description
    1. 6.1  Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF) (F2812 Only)
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0, L1, H0 SARAMs
      9. 6.1.9  Boot ROM
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12 External Interrupts (XINT1, XINT2, XINT13, XNMI)
      13. 6.1.13 Oscillator and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-Power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2 (PFn)
      18. 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2  Peripherals
      1. 6.2.1 32-Bit CPU-Timers 0/1/2
      2. 6.2.2 Event Manager Modules (EVA, EVB)
        1. 6.2.2.1 General-Purpose (GP) Timers
        2. 6.2.2.2 Full-Compare Units
        3. 6.2.2.3 Programmable Deadband Generator
        4. 6.2.2.4 PWM Waveform Generation
        5. 6.2.2.5 Double Update PWM Mode
        6. 6.2.2.6 PWM Characteristics
        7. 6.2.2.7 Capture Unit
        8. 6.2.2.8 Quadrature-Encoder Pulse (QEP) Circuit
        9. 6.2.2.9 External ADC Start-of-Conversion
      3. 6.2.3 Enhanced Analog-to-Digital Converter (ADC) Module
      4. 6.2.4 Enhanced Controller Area Network (eCAN) Module
      5. 6.2.5 Multichannel Buffered Serial Port (McBSP) Module
      6. 6.2.6 Serial Communications Interface (SCI) Module
      7. 6.2.7 Serial Peripheral Interface (SPI) Module
      8. 6.2.8 GPIO MUX
    3. 6.3  Memory Maps
    4. 6.4  Register Map
    5. 6.5  Device Emulation Registers
    6. 6.6  External Interface, XINTF (F2812 Only)
      1. 6.6.1 Timing Registers
      2. 6.6.2 XREVISION Register
    7. 6.7  Interrupts
      1. 6.7.1 External Interrupts
    8. 6.8  System Control
    9. 6.9  OSC and PLL Block
      1. 6.9.1 Loss of Input Clock
    10. 6.10 PLL-Based Clock Module
    11. 6.11 External Reference Oscillator Clock Option
    12. 6.12 Watchdog Block
    13. 6.13 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8デバイスおよびドキュメントのサポート
    1. 8.1 はじめに
    2. 8.2 デバイスおよび開発ツールの項目表記
    3. 8.3 ツールとソフトウェア
    4. 8.4 ドキュメントのサポート
    5. 8.5 関連リンク
    6. 8.6 Community Resources
    7. 8.7 商標
    8. 8.8 静電気放電に関する注意事項
    9. 8.9 Glossary
  9. 9メカニカル、パッケージ、および注文情報
    1. 9.1 パッケージ情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PBK|128
サーマルパッド・メカニカル・データ
発注情報

6.2.3 Enhanced Analog-to-Digital Converter (ADC) Module

A simplified functional block diagram of the ADC module is shown in Figure 6-4. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:

  • 12-bit ADC core with built-in S/H
  • Analog input: 0.0 V to 3.0 V (voltages above 3.0 V produce full-scale conversion results)
  • Fast conversion rate: 80 ns at 25-MHz ADC clock, 12.5 MSPS
  • 16-channel, MUXed inputs
  • Autosequencing capability provides up to 16 “autoconversions” in a single session. Each conversion can be programmed to select any 1 of 16 input channels
  • Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (that is, two cascaded 8-state sequencers)
  • Sixteen result registers (individually addressable) to store conversion values
    • The digital value of the input analog voltage is derived by:
      • TMS320F2810 TMS320F2811 TMS320F2812 q_adclo3_prs439.gif
  • Multiple triggers as sources for the start-of-conversion (SOC) sequence
    • S/W – software immediate start
    • EVA – Event manager A (multiple event sources within EVA)
    • EVB – Event manager B (multiple event sources within EVB)
  • Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
  • Sequencer can operate in “start/stop” mode, allowing multiple “time-sequenced triggers” to synchronize conversions
  • EVA and EVB triggers can operate independently in dual-sequencer mode
  • Sample-and-hold (S/H) acquisition time window has separate prescale control

The ADC module in the F281x has been enhanced to provide flexible interface to event managers A and B. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules to service event managers A and B. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 6-4 shows the block diagram of the F281x ADC module.

The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.

TMS320F2810 TMS320F2811 TMS320F2812 adcmod_prs174.gifFigure 6-4 Block Diagram of the F281x ADC Module

To obtain the specified accuracy of the ADC, proper board layout is critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins (VDDA1/VDDA2, AVDDREFBG) from the digital supply. For better accuracy and ESD protection, unused ADC inputs should be connected to analog ground.

Notes:

  1. The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is controlled by the high-speed peripheral clock (HSPCLK).
  2. The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:

    3. ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register will still function. This is necessary to make sure all registers and modes go into their default reset state. The analog module will, however, be in a low-power inactive state. As soon as reset goes high, then the clock to the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms range) before the ADC is stable and can be used.

    HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is powered. If high, the ADC module goes into low-power mode. The HALT mode will stop the clock to the CPU, which will stop the HSPCLK. Therefore the ADC register logic will be turned off indirectly.

Figure 6-5 shows the ADC pin-biasing for internal reference and Figure 6-6 shows the ADC pin-biasing for external reference.

TMS320F2810 TMS320F2811 TMS320F2812 adcpinint_prs174.gif
A. Provide access to this pin in PCB layouts. Intended for test purposes only.
B. Use 24.9 kΩ for ADC clock range 1–18.75 MHz; use 20 kΩ for ADC clock range 18.75–25 MHz.
C. TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent ceramic capacitor
D. External decoupling capacitors are recommended on all power pins.
E. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 6-5 ADC Pin Connections With Internal Reference

NOTE

The temperature rating of any recommended component must match the rating of the end product.
TMS320F2810 TMS320F2811 TMS320F2812 adcpinext_prs174.gif
A. External decoupling capacitors are recommended on all power pins.
B. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
C. Use 24.9 kΩ for ADC clock range 1–18.75 MHz; use 20 kΩ for ADC clock range 18.75–25 MHz.
D. It is recommended that buffered external references be provided with a voltage difference of (ADCREFP – ADCREFM) = 1 V ± 0.1% or better.
External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of external reference is critical for overall gain. The voltage ADCREFP – ADCREFM will determine the overall accuracy. Do not enable internal references when external references are connected to ADCREFP and ADCREFM. See the TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide for more information.
Figure 6-6 ADC Pin Connections With External Reference

The ADC operation is configured, controlled, and monitored by the registers listed in Table 6-6.

Table 6-6 ADC Registers(1)

NAME ADDRESS SIZE (x16) DESCRIPTION
ADCTRL1 0x00 7100 1 ADC Control Register 1
ADCTRL2 0x00 7101 1 ADC Control Register 2
ADCMAXCONV 0x00 7102 1 ADC Maximum Conversion Channels Register
ADCCHSELSEQ1 0x00 7103 1 ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2 0x00 7104 1 ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3 0x00 7105 1 ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4 0x00 7106 1 ADC Channel Select Sequencing Control Register 4
ADCASEQSR 0x00 7107 1 ADC Auto-Sequence Status Register
ADCRESULT0 0x00 7108 1 ADC Conversion Result Buffer Register 0
ADCRESULT1 0x00 7109 1 ADC Conversion Result Buffer Register 1
ADCRESULT2 0x00 710A 1 ADC Conversion Result Buffer Register 2
ADCRESULT3 0x00 710B 1 ADC Conversion Result Buffer Register 3
ADCRESULT4 0x00 710C 1 ADC Conversion Result Buffer Register 4
ADCRESULT5 0x00 710D 1 ADC Conversion Result Buffer Register 5
ADCRESULT6 0x00 710E 1 ADC Conversion Result Buffer Register 6
ADCRESULT7 0x00 710F 1 ADC Conversion Result Buffer Register 7
ADCRESULT8 0x00 7110 1 ADC Conversion Result Buffer Register 8
ADCRESULT9 0x00 7111 1 ADC Conversion Result Buffer Register 9
ADCRESULT10 0x00 7112 1 ADC Conversion Result Buffer Register 10
ADCRESULT11 0x00 7113 1 ADC Conversion Result Buffer Register 11
ADCRESULT12 0x00 7114 1 ADC Conversion Result Buffer Register 12
ADCRESULT13 0x00 7115 1 ADC Conversion Result Buffer Register 13
ADCRESULT14 0x00 7116 1 ADC Conversion Result Buffer Register 14
ADCRESULT15 0x00 7117 1 ADC Conversion Result Buffer Register 15
ADCTRL3 0x00 7118 1 ADC Control Register 3
ADCST 0x00 7119 1 ADC Status Register
Reserved 0x00 711C – 0x00 711F 4
(1) The above registers are Peripheral Frame 2 Registers.