JAJSEG7
December 2017
TMS320F28377D-EP
PRODUCTION DATA.
1
デバイスの概要
1.1
特長
1.2
アプリケーション
1.3
概要
1.4
機能ブロック図
2
改訂履歴
3
Terminal Configuration and Functions
3.1
Pin Diagrams
3.2
Signal Descriptions
Table 3-1
Signal Descriptions
3.3
Pins With Internal Pullup and Pulldown
3.4
Pin Multiplexing
3.4.1
GPIO Muxed Pins
3.4.2
Input X-BAR
3.4.3
Output X-BAR and ePWM X-BAR
3.4.4
USB Pin Muxing
3.4.5
High-Speed SPI Pin Muxing
3.5
Connections for Unused Pins
4
Specifications
4.1
Absolute Maximum Ratings
4.2
ESD Ratings
4.3
Recommended Operating Conditions
4.4
Power Consumption Summary
Table 4-1
Device Current Consumption at 200-MHz SYSCLK
4.4.1
Current Consumption Graphs
4.4.2
Reducing Current Consumption
4.5
Electrical Characteristics
4.6
Thermal Resistance Characteristics
4.6.1
GWT Package
4.6.2
PTP Package
4.7
System
4.7.1
Power Sequencing
Table 4-3
Supply Ramp Rate
4.7.2
Reset Timing
4.7.2.1
Reset Sources
4.7.2.2
Reset Electrical Data and Timing
Table 4-4
Reset (XRS) Timing Requirements
Table 4-5
Reset (XRS) Switching Characteristics
4.7.3
Clock Specifications
4.7.3.1
Clock Sources
4.7.3.2
Clock Frequencies, Requirements, and Characteristics
4.7.3.2.1
Input Clock Frequency and Timing Requirements, PLL Lock Times
Table 4-7
Input Clock Frequency
Table 4-8
X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
Table 4-9
X1 Timing Requirements
Table 4-10
AUXCLKIN Timing Requirements
Table 4-11
PLL Lock Times
4.7.3.2.2
Internal Clock Frequencies
Table 4-12
Internal Clock Frequencies
4.7.3.2.3
Output Clock Frequency and Switching Characteristics
Table 4-13
Output Clock Frequency
Table 4-14
XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
4.7.3.3
Input Clocks and PLLs
4.7.3.4
Crystal Oscillator
Table 4-15
Crystal Oscillator Parameters
Table 4-17
Crystal Oscillator Electrical Characteristics
4.7.3.5
Internal Oscillators
Table 4-18
Internal Oscillator Electrical Characteristics
4.7.4
Flash Parameters
Table 4-20
Flash Parameters
4.7.5
Emulation/JTAG
4.7.5.1
JTAG Electrical Data and Timing
Table 4-21
JTAG Timing Requirements
Table 4-22
JTAG Switching Characteristics
4.7.6
GPIO Electrical Data and Timing
4.7.6.1
GPIO - Output Timing
Table 4-23
General-Purpose Output Switching Characteristics
4.7.6.2
GPIO - Input Timing
Table 4-24
General-Purpose Input Timing Requirements
4.7.6.3
Sampling Window Width for Input Signals
4.7.7
Interrupts
4.7.7.1
External Interrupt (XINT) Electrical Data and Timing
Table 4-25
External Interrupt Timing Requirements
Table 4-26
External Interrupt Switching Characteristics
4.7.8
Low-Power Modes
4.7.8.1
Clock-Gating Low-Power Modes
4.7.8.2
Power-Gating Low-Power Modes
4.7.8.3
Low-Power Mode Wakeup Timing
Table 4-29
IDLE Mode Timing Requirements
Table 4-30
IDLE Mode Switching Characteristics
Table 4-31
STANDBY Mode Timing Requirements
Table 4-32
STANDBY Mode Switching Characteristics
Table 4-33
HALT Mode Timing Requirements
Table 4-34
HALT Mode Switching Characteristics
Table 4-35
HIBERNATE Mode Timing Requirements
Table 4-36
HIBERNATE Mode Switching Characteristics
4.7.9
External Memory Interface (EMIF)
4.7.9.1
Asynchronous Memory Support
4.7.9.2
Synchronous DRAM Support
4.7.9.3
EMIF Electrical Data and Timing
4.7.9.3.1
Asynchronous RAM
Table 4-37
EMIF Asynchronous Memory Timing Requirements
Table 4-38
EMIF Asynchronous Memory Switching Characteristics
4.7.9.3.2
Synchronous RAM
Table 4-39
EMIF Synchronous Memory Timing Requirements
Table 4-40
EMIF Synchronous Memory Switching Characteristics
4.8
Analog Peripherals
4.8.1
Analog-to-Digital Converter (ADC)
4.8.1.1
ADC Electrical Data and Timing
Table 4-41
ADC Operating Conditions (16-Bit Differential Mode)
Table 4-42
ADC Characteristics (16-Bit Differential Mode)
Table 4-43
ADC Operating Conditions (12-Bit Single-Ended Mode)
Table 4-44
ADC Characteristics (12-Bit Single-Ended Mode)
Table 4-45
ADCEXTSOC Timing Requirements
4.8.1.1.1
ADC Input Models
Table 4-46
Single-Ended Input Model Parameters
Table 4-47
Differential Input Model Parameters
4.8.1.1.2
ADC Timing Diagrams
Table 4-49
ADC Timings in 12-Bit Mode (SYSCLK Cycles)
Table 4-50
ADC Timings in 16-Bit Mode
4.8.1.2
Temperature Sensor Electrical Data and Timing
Table 4-51
Temperature Sensor Electrical Characteristics
4.8.2
Comparator Subsystem (CMPSS)
4.8.2.1
CMPSS Electrical Data and Timing
Table 4-52
Comparator Electrical Characteristics
Table 4-53
CMPSS DAC Static Electrical Characteristics
4.8.3
Buffered Digital-to-Analog Converter (DAC)
4.8.3.1
Buffered DAC Electrical Data and Timing
Table 4-54
Buffered DAC Electrical Characteristics
4.9
Control Peripherals
4.9.1
Enhanced Capture (eCAP)
4.9.1.1
eCAP Electrical Data and Timing
Table 4-55
eCAP Timing Requirement
Table 4-56
eCAP Switching Characteristics
4.9.2
Enhanced Pulse Width Modulator (ePWM)
4.9.2.1
Control Peripherals Synchronization
4.9.2.2
ePWM Electrical Data and Timing
Table 4-57
ePWM Timing Requirements
Table 4-58
ePWM Switching Characteristics
4.9.2.2.1
Trip-Zone Input Timing
Table 4-59
Trip-Zone Input Timing Requirements
4.9.2.3
External ADC Start-of-Conversion Electrical Data and Timing
Table 4-60
External ADC Start-of-Conversion Switching Characteristics
4.9.3
Enhanced Quadrature Encoder Pulse (eQEP)
4.9.3.1
eQEP Electrical Data and Timing
Table 4-61
eQEP Timing Requirements
Table 4-62
eQEP Switching Characteristics
4.9.4
High-Resolution Pulse Width Modulator (HRPWM)
4.9.4.1
HRPWM Electrical Data and Timing
Table 4-63
High-Resolution PWM Characteristics
4.9.5
Sigma-Delta Filter Module (SDFM)
4.9.5.1
SDFM Electrical Data and Timing
Table 4-64
SDFM Timing Requirements
4.10
Communications Peripherals
4.10.1
Controller Area Network (CAN)
4.10.2
Inter-Integrated Circuit (I2C)
4.10.2.1
I2C Electrical Data and Timing
Table 4-65
I2C Timing Requirements
Table 4-66
I2C Switching Characteristics
4.10.3
Multichannel Buffered Serial Port (McBSP)
4.10.3.1
McBSP Electrical Data and Timing
4.10.3.1.1
McBSP Transmit and Receive Timing
Table 4-67
McBSP Timing Requirements
Table 4-68
McBSP Switching Characteristics
4.10.3.1.2
McBSP as SPI Master or Slave Timing
Table 4-69
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
Table 4-70
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
Table 4-71
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
Table 4-72
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
Table 4-73
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
Table 4-74
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
Table 4-75
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
Table 4-76
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
4.10.4
Serial Communications Interface (SCI)
4.10.5
Serial Peripheral Interface (SPI)
4.10.5.1
SPI Electrical Data and Timing
4.10.5.1.1
Non-High-Speed Master Mode Timings
Table 4-77
SPI Master Mode Switching Characteristics (Clock Phase = 0)
Table 4-78
SPI Master Mode Switching Characteristics (Clock Phase = 1)
Table 4-79
SPI Master Mode Timing Requirements
4.10.5.1.2
Non-High-Speed Slave Mode Timings
Table 4-80
SPI Slave Mode Switching Characteristics
Table 4-81
SPI Slave Mode Timing Requirements
4.10.5.1.3
High-Speed Master Mode Timings
Table 4-82
SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
Table 4-83
SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
Table 4-84
SPI High-Speed Master Mode Timing Requirements
4.10.5.1.4
High-Speed Slave Mode Timings
Table 4-85
SPI High-Speed Slave Mode Switching Characteristics
Table 4-86
SPI High-Speed Slave Mode Timing Requirements
4.10.6
Universal Serial Bus (USB) Controller
4.10.6.1
USB Electrical Data and Timing
Table 4-87
USB Input Ports DP and DM Timing Requirements
Table 4-88
USB Output Ports DP and DM Switching Characteristics
4.10.7
Universal Parallel Port (uPP) Interface
4.10.7.1
uPP Electrical Data and Timing
Table 4-89
uPP Timing Requirements
Table 4-90
uPP Switching Characteristics
5
Detailed Description
5.1
Overview
5.2
Functional Block Diagram
5.3
Memory
5.3.1
C28x Memory Map
5.3.2
Flash Memory Map
5.3.3
EMIF Chip Select Memory Map
5.3.4
Peripheral Registers Memory Map
5.3.5
Memory Types
5.3.5.1
Dedicated RAM (Mx and Dx RAM)
5.3.5.2
Local Shared RAM (LSx RAM)
5.3.5.3
Global Shared RAM (GSx RAM)
5.3.5.4
CPU Message RAM (CPU MSGRAM)
5.3.5.5
CLA Message RAM (CLA MSGRAM)
5.4
Identification
5.5
Bus Architecture – Peripheral Connectivity
5.6
C28x Processor
5.6.1
Floating-Point Unit
5.6.2
Trigonometric Math Unit
5.6.3
Viterbi, Complex Math, and CRC Unit II (VCU-II)
5.7
Control Law Accelerator
5.8
Direct Memory Access
5.9
Interprocessor Communication Module
5.10
Boot ROM and Peripheral Booting
5.10.1
EMU Boot or Emulation Boot
5.10.2
WAIT Boot Mode
5.10.3
Get Mode
5.10.4
Peripheral Pins Used by Bootloaders
5.11
Dual Code Security Module
5.12
Timers
5.13
Nonmaskable Interrupt With Watchdog Timer (NMIWD)
5.14
Watchdog
5.15
Configurable Logic Block (CLB)
6
Applications, Implementation, and Layout
6.1
TI Design or Reference Design
7
デバイスおよびドキュメントのサポート
7.1
デバイスおよび開発ツールの項目表記
7.2
ツールとソフトウェア
7.3
デバイスの項目表記
7.4
ドキュメントのサポート
7.5
Community Resources
7.6
商標
7.7
静電気放電に関する注意事項
7.8
Export Control Notice
7.9
Glossary
8
メカニカル、パッケージ、および注文情報
8.1
ビア・チャネル
8.2
パッケージ情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
GWT|337
MPBGAY4
PTP|176
MPQF068B
サーマルパッド・メカニカル・データ
PTP|176
PPTD302A
発注情報
jajseg7_oa
jajseg7_pm
4.9
Control Peripherals