JAJSEG7 December   2017 TMS320F28377D-EP

PRODUCTION DATA.  

  1. 1デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 機能ブロック図
  2. 2改訂履歴
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagrams
    2. 3.2 Signal Descriptions
      1. Table 3-1 Signal Descriptions
    3. 3.3 Pins With Internal Pullup and Pulldown
    4. 3.4 Pin Multiplexing
      1. 3.4.1 GPIO Muxed Pins
      2. 3.4.2 Input X-BAR
      3. 3.4.3 Output X-BAR and ePWM X-BAR
      4. 3.4.4 USB Pin Muxing
      5. 3.4.5 High-Speed SPI Pin Muxing
    5. 3.5 Connections for Unused Pins
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Power Consumption Summary
      1. Table 4-1 Device Current Consumption at 200-MHz SYSCLK
      2. 4.4.1      Current Consumption Graphs
      3. 4.4.2      Reducing Current Consumption
    5. 4.5  Electrical Characteristics
    6. 4.6  Thermal Resistance Characteristics
      1. 4.6.1 GWT Package
      2. 4.6.2 PTP Package
    7. 4.7  System
      1. 4.7.1 Power Sequencing
        1. Table 4-3 Supply Ramp Rate
      2. 4.7.2 Reset Timing
        1. 4.7.2.1 Reset Sources
        2. 4.7.2.2 Reset Electrical Data and Timing
          1. Table 4-4 Reset (XRS) Timing Requirements
          2. Table 4-5 Reset (XRS) Switching Characteristics
      3. 4.7.3 Clock Specifications
        1. 4.7.3.1 Clock Sources
        2. 4.7.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 4.7.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 4-7   Input Clock Frequency
            2. Table 4-8   X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
            3. Table 4-9   X1 Timing Requirements
            4. Table 4-10 AUXCLKIN Timing Requirements
            5. Table 4-11 PLL Lock Times
          2. 4.7.3.2.2 Internal Clock Frequencies
            1. Table 4-12 Internal Clock Frequencies
          3. 4.7.3.2.3 Output Clock Frequency and Switching Characteristics
            1. Table 4-13 Output Clock Frequency
            2. Table 4-14 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 4.7.3.3 Input Clocks and PLLs
        4. 4.7.3.4 Crystal Oscillator
          1. Table 4-15 Crystal Oscillator Parameters
          2. Table 4-17 Crystal Oscillator Electrical Characteristics
        5. 4.7.3.5 Internal Oscillators
          1. Table 4-18 Internal Oscillator Electrical Characteristics
      4. 4.7.4 Flash Parameters
        1. Table 4-20 Flash Parameters
      5. 4.7.5 Emulation/JTAG
        1. 4.7.5.1 JTAG Electrical Data and Timing
          1. Table 4-21 JTAG Timing Requirements
          2. Table 4-22 JTAG Switching Characteristics
      6. 4.7.6 GPIO Electrical Data and Timing
        1. 4.7.6.1 GPIO - Output Timing
          1. Table 4-23 General-Purpose Output Switching Characteristics
        2. 4.7.6.2 GPIO - Input Timing
          1. Table 4-24 General-Purpose Input Timing Requirements
        3. 4.7.6.3 Sampling Window Width for Input Signals
      7. 4.7.7 Interrupts
        1. 4.7.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 4-25 External Interrupt Timing Requirements
          2. Table 4-26 External Interrupt Switching Characteristics
      8. 4.7.8 Low-Power Modes
        1. 4.7.8.1 Clock-Gating Low-Power Modes
        2. 4.7.8.2 Power-Gating Low-Power Modes
        3. 4.7.8.3 Low-Power Mode Wakeup Timing
          1. Table 4-29 IDLE Mode Timing Requirements
          2. Table 4-30 IDLE Mode Switching Characteristics
          3. Table 4-31 STANDBY Mode Timing Requirements
          4. Table 4-32 STANDBY Mode Switching Characteristics
          5. Table 4-33 HALT Mode Timing Requirements
          6. Table 4-34 HALT Mode Switching Characteristics
          7. Table 4-35 HIBERNATE Mode Timing Requirements
          8. Table 4-36 HIBERNATE Mode Switching Characteristics
      9. 4.7.9 External Memory Interface (EMIF)
        1. 4.7.9.1 Asynchronous Memory Support
        2. 4.7.9.2 Synchronous DRAM Support
        3. 4.7.9.3 EMIF Electrical Data and Timing
          1. 4.7.9.3.1 Asynchronous RAM
            1. Table 4-37 EMIF Asynchronous Memory Timing Requirements
            2. Table 4-38 EMIF Asynchronous Memory Switching Characteristics
          2. 4.7.9.3.2 Synchronous RAM
            1. Table 4-39 EMIF Synchronous Memory Timing Requirements
            2. Table 4-40 EMIF Synchronous Memory Switching Characteristics
    8. 4.8  Analog Peripherals
      1. 4.8.1 Analog-to-Digital Converter (ADC)
        1. 4.8.1.1 ADC Electrical Data and Timing
          1. Table 4-41 ADC Operating Conditions (16-Bit Differential Mode)
          2. Table 4-42 ADC Characteristics (16-Bit Differential Mode)
          3. Table 4-43 ADC Operating Conditions (12-Bit Single-Ended Mode)
          4. Table 4-44 ADC Characteristics (12-Bit Single-Ended Mode)
          5. Table 4-45 ADCEXTSOC Timing Requirements
          6. 4.8.1.1.1   ADC Input Models
            1. Table 4-46 Single-Ended Input Model Parameters
            2. Table 4-47 Differential Input Model Parameters
          7. 4.8.1.1.2   ADC Timing Diagrams
            1. Table 4-49 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. Table 4-50 ADC Timings in 16-Bit Mode
        2. 4.8.1.2 Temperature Sensor Electrical Data and Timing
          1. Table 4-51 Temperature Sensor Electrical Characteristics
      2. 4.8.2 Comparator Subsystem (CMPSS)
        1. 4.8.2.1 CMPSS Electrical Data and Timing
          1. Table 4-52 Comparator Electrical Characteristics
          2. Table 4-53 CMPSS DAC Static Electrical Characteristics
      3. 4.8.3 Buffered Digital-to-Analog Converter (DAC)
        1. 4.8.3.1 Buffered DAC Electrical Data and Timing
          1. Table 4-54 Buffered DAC Electrical Characteristics
    9. 4.9  Control Peripherals
      1. 4.9.1 Enhanced Capture (eCAP)
        1. 4.9.1.1 eCAP Electrical Data and Timing
          1. Table 4-55 eCAP Timing Requirement
          2. Table 4-56 eCAP Switching Characteristics
      2. 4.9.2 Enhanced Pulse Width Modulator (ePWM)
        1. 4.9.2.1 Control Peripherals Synchronization
        2. 4.9.2.2 ePWM Electrical Data and Timing
          1. Table 4-57 ePWM Timing Requirements
          2. Table 4-58 ePWM Switching Characteristics
          3. 4.9.2.2.1   Trip-Zone Input Timing
            1. Table 4-59 Trip-Zone Input Timing Requirements
        3. 4.9.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 4-60 External ADC Start-of-Conversion Switching Characteristics
      3. 4.9.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 4.9.3.1 eQEP Electrical Data and Timing
          1. Table 4-61 eQEP Timing Requirements
          2. Table 4-62 eQEP Switching Characteristics
      4. 4.9.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 4.9.4.1 HRPWM Electrical Data and Timing
          1. Table 4-63 High-Resolution PWM Characteristics
      5. 4.9.5 Sigma-Delta Filter Module (SDFM)
        1. 4.9.5.1 SDFM Electrical Data and Timing
          1. Table 4-64 SDFM Timing Requirements
    10. 4.10 Communications Peripherals
      1. 4.10.1 Controller Area Network (CAN)
      2. 4.10.2 Inter-Integrated Circuit (I2C)
        1. 4.10.2.1 I2C Electrical Data and Timing
          1. Table 4-65 I2C Timing Requirements
          2. Table 4-66 I2C Switching Characteristics
      3. 4.10.3 Multichannel Buffered Serial Port (McBSP)
        1. 4.10.3.1 McBSP Electrical Data and Timing
          1. 4.10.3.1.1 McBSP Transmit and Receive Timing
            1. Table 4-67 McBSP Timing Requirements
            2. Table 4-68 McBSP Switching Characteristics
          2. 4.10.3.1.2 McBSP as SPI Master or Slave Timing
            1. Table 4-69 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 4-70 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 4-71 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 4-72 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 4-73 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 4-74 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 4-75 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 4-76 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      4. 4.10.4 Serial Communications Interface (SCI)
      5. 4.10.5 Serial Peripheral Interface (SPI)
        1. 4.10.5.1 SPI Electrical Data and Timing
          1. 4.10.5.1.1 Non-High-Speed Master Mode Timings
            1. Table 4-77 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 4-78 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 4-79 SPI Master Mode Timing Requirements
          2. 4.10.5.1.2 Non-High-Speed Slave Mode Timings
            1. Table 4-80 SPI Slave Mode Switching Characteristics
            2. Table 4-81 SPI Slave Mode Timing Requirements
          3. 4.10.5.1.3 High-Speed Master Mode Timings
            1. Table 4-82 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 0)
            2. Table 4-83 SPI High-Speed Master Mode Switching Characteristics (Clock Phase = 1)
            3. Table 4-84 SPI High-Speed Master Mode Timing Requirements
          4. 4.10.5.1.4 High-Speed Slave Mode Timings
            1. Table 4-85 SPI High-Speed Slave Mode Switching Characteristics
            2. Table 4-86 SPI High-Speed Slave Mode Timing Requirements
      6. 4.10.6 Universal Serial Bus (USB) Controller
        1. 4.10.6.1 USB Electrical Data and Timing
          1. Table 4-87 USB Input Ports DP and DM Timing Requirements
          2. Table 4-88 USB Output Ports DP and DM Switching Characteristics
      7. 4.10.7 Universal Parallel Port (uPP) Interface
        1. 4.10.7.1 uPP Electrical Data and Timing
          1. Table 4-89 uPP Timing Requirements
          2. Table 4-90 uPP Switching Characteristics
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Memory
      1. 5.3.1 C28x Memory Map
      2. 5.3.2 Flash Memory Map
      3. 5.3.3 EMIF Chip Select Memory Map
      4. 5.3.4 Peripheral Registers Memory Map
      5. 5.3.5 Memory Types
        1. 5.3.5.1 Dedicated RAM (Mx and Dx RAM)
        2. 5.3.5.2 Local Shared RAM (LSx RAM)
        3. 5.3.5.3 Global Shared RAM (GSx RAM)
        4. 5.3.5.4 CPU Message RAM (CPU MSGRAM)
        5. 5.3.5.5 CLA Message RAM (CLA MSGRAM)
    4. 5.4  Identification
    5. 5.5  Bus Architecture – Peripheral Connectivity
    6. 5.6  C28x Processor
      1. 5.6.1 Floating-Point Unit
      2. 5.6.2 Trigonometric Math Unit
      3. 5.6.3 Viterbi, Complex Math, and CRC Unit II (VCU-II)
    7. 5.7  Control Law Accelerator
    8. 5.8  Direct Memory Access
    9. 5.9  Interprocessor Communication Module
    10. 5.10 Boot ROM and Peripheral Booting
      1. 5.10.1 EMU Boot or Emulation Boot
      2. 5.10.2 WAIT Boot Mode
      3. 5.10.3 Get Mode
      4. 5.10.4 Peripheral Pins Used by Bootloaders
    11. 5.11 Dual Code Security Module
    12. 5.12 Timers
    13. 5.13 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
    14. 5.14 Watchdog
    15. 5.15 Configurable Logic Block (CLB)
  6. 6Applications, Implementation, and Layout
    1. 6.1 TI Design or Reference Design
  7. 7デバイスおよびドキュメントのサポート
    1. 7.1 デバイスおよび開発ツールの項目表記
    2. 7.2 ツールとソフトウェア
    3. 7.3 デバイスの項目表記
    4. 7.4 ドキュメントのサポート
    5. 7.5 Community Resources
    6. 7.6 商標
    7. 7.7 静電気放電に関する注意事項
    8. 7.8 Export Control Notice
    9. 7.9 Glossary
  8. 8メカニカル、パッケージ、および注文情報
    1. 8.1 ビア・チャネル
    2. 8.2 パッケージ情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Table 4-1 Device Current Consumption at 200-MHz SYSCLK

MODE TEST CONDITIONS IDD IDDIO(1) IDDA IDD3VFL
TYP(5) MAX(4) TYP(5) MAX(4) TYP(5) MAX(4) TYP(5) MAX(4)
Operational
(RAM)
  • Code is running out of RAM.(6)
  • All I/O pins are left unconnected.
  • Peripherals not active have their clocks disabled.
  • FLASH is read and in active state.
  • XCLKOUT is enabled at SYSCLK/4.
 325 mA 440 mA 30 mA 13 mA 20 mA 33 mA 40 mA
IDLE
  • Both CPU1 and CPU2 are in IDLE mode.
  • Flash is powered down.
  • XCLKOUT is turned off.
 105 mA 210 mA 3 mA 10 mA 10 µA 150 µA 10 µA 150 µA
STANDBY
  • Both CPU1 and CPU2 are in STANDBY mode.
  • Flash is powered down.
  • XCLKOUT is turned off.
 30 mA 135 mA 3 mA 10 mA 5 µA 150 µA 10 µA 150 µA
HALT(2)
  • CPU1 watchdog is running.
  • Flash is powered down.
  • XCLKOUT is turned off.
 1.5 mA 110 mA 750 µA 2 mA 5 µA 150 µA 10 µA 150 µA
HIBERNATE(3)
  • CPU1.M0 and CPU1.M1 RAMs are in low-power data retention mode.
  • CPU2.M0 and CPU2.M1 RAMs are in low-power data retention mode.
 300 µA 4 mA 750 µA 2 mA 5 µA 75 µA 1 µA 50 µA
Flash
Erase/Program
  • CPU1 is running from RAM.
  • CPU2 is running from Flash.
  • All I/O pins are left unconnected.
  • Peripheral clocks are disabled.
  • CPU1 is performing Flash Erase and Programming.
  • CPU2 is accessing Flash locations to keep bank active.
  • XCLKOUT is turned off.
 242 mA 360 mA 3 mA 10 mA 10 µA 150 µA 53 mA 65 mA
(1) IDDIO current is dependent on the electrical loading on the I/O pins.
(2) CPU2 must go into IDLE mode before CPU1 enters HALT mode.
(3) CPU2 must go into reset/IDLE/STANDBY mode before CPU1 enters HIBERNATE mode.
(4) MAX: Vmax, 125°C
(5) TYP: Vnom, 30°C
(6) The following is executed in a loop on CPU1:
  • All of the communication peripherals are exercised in loop-back mode: CAN-A to CAN-B; SPI-A to SPI-C; SCI-A to SCI-D; I2C-A to I2C-B; McBSP-A to McBSP-B; USB
  • SDFM1 to SDFM4 active
  • ePWM1 to ePWM12 generate 400-kHz PWM output on 24 pins
  • CPU TIMERs active
  • DMA does 32-bit burst transfers
  • CLA1 does multiply-accumulate tasks
  • All ADCs perform continuous conversion
  • All DACs ramp voltage up/down at 150 kHz
  • CMPSS1 to CMPSS8 active

The following is executed in a loop on CPU2:
  • CPU TIMERs active
  • CLA1 does multiply-accumulate tasks
  • VCU does complex multiply/accumulate with parallel load
  • TMU calculates a cosine
  • FPU does multiply/accumulate with parallel load