SPRSP69B July   2023  – November 2023 TMS320F28P650DK , TMS320F28P659DK-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Analog Signals
      2. 5.3.2 Digital Signals
      3. 5.3.3 Power and Ground
      4. 5.3.4 Test, JTAG, and Reset
    4. 5.4 Pins With Internal Pullup and Pulldown
    5. 5.5 Pin Multiplexing
      1. 5.5.1 GPIO Muxed Pins
      2. 5.5.2 USB Pin Muxing
      3. 5.5.3 High-Speed SPI Pin Muxing
    6. 5.6 Connections for Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings – Commercial
    3. 6.3  ESD Ratings – Automotive
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Consumption Summary
      1. 6.5.1 System Current Consumption VREG Enabled
      2. 6.5.2 System Current Consumption VREG Disable - External Supply
      3. 6.5.3 Operating Mode Test Description
      4. 6.5.4 Current Consumption Graphs
      5. 6.5.5 Reducing Current Consumption
        1. 6.5.5.1 Typical Current Reduction per Disabled Peripheral
    6. 6.6  Electrical Characteristics
    7. 6.7  Thermal Resistance Characteristics for ZEJ Package
    8. 6.8  Thermal Resistance Characteristics for PTP Package
    9. 6.9  Thermal Resistance Characteristics for NMR Package
    10. 6.10 Thermal Resistance Characteristics for PZP Package
    11. 6.11 Thermal Design Considerations
    12. 6.12 System
      1. 6.12.1  Power Management Module (PMM)
        1. 6.12.1.1 Introduction
        2. 6.12.1.2 Overview
          1. 6.12.1.2.1 Power Rail Monitors
            1. 6.12.1.2.1.1 I/O POR (Power-On Reset) Monitor
            2. 6.12.1.2.1.2 I/O BOR (Brown-Out Reset) Monitor
            3. 6.12.1.2.1.3 VDD POR (Power-On Reset) Monitor
          2. 6.12.1.2.2 External Supervisor Usage
          3. 6.12.1.2.3 Delay Blocks
          4. 6.12.1.2.4 Internal 1.2-V LDO Voltage Regulator (VREG)
          5. 6.12.1.2.5 VREGENZ
        3. 6.12.1.3 External Components
          1. 6.12.1.3.1 Decoupling Capacitors
            1. 6.12.1.3.1.1 VDDIO Decoupling
            2. 6.12.1.3.1.2 VDD Decoupling
        4. 6.12.1.4 Power Sequencing
          1. 6.12.1.4.1 Supply Pins Ganging
          2. 6.12.1.4.2 Signal Pins Power Sequence
          3. 6.12.1.4.3 Supply Pins Power Sequence
            1. 6.12.1.4.3.1 External VREG/VDD Mode Sequence
            2. 6.12.1.4.3.2 Internal VREG/VDD Mode Sequence
            3. 6.12.1.4.3.3 Supply Sequencing Summary and Effects of Violations
            4. 6.12.1.4.3.4 Supply Slew Rate
        5. 6.12.1.5 Power Management Module Electrical Data and Timing
          1. 6.12.1.5.1 Power Management Module Operating Conditions
          2. 6.12.1.5.2 Power Management Module Characteristics
      2. 6.12.2  Reset Timing
        1. 6.12.2.1 Reset Sources
        2. 6.12.2.2 Reset Electrical Data and Timing
          1. 6.12.2.2.1 Reset XRSn Timing Requirements
          2. 6.12.2.2.2 Reset XRSn Switching Characteristics
          3. 6.12.2.2.3 Reset Timing Diagrams
      3. 6.12.3  Clock Specifications
        1. 6.12.3.1 Clock Sources
        2. 6.12.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 6.12.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 6.12.3.2.1.1 Input Clock Frequency
            2. 6.12.3.2.1.2 XTAL Oscillator Characteristics
            3. 6.12.3.2.1.3 X1 Input Level Characteristics When Using an External Clock Source Not a Crystal
            4. 6.12.3.2.1.4 X1 Timing Requirements
            5. 6.12.3.2.1.5 AUXCLKIN Timing Requirements
            6. 6.12.3.2.1.6 APLL Characteristics
            7. 6.12.3.2.1.7 XCLKOUT Switching Characteristics PLL Bypassed or Enabled
            8. 6.12.3.2.1.8 Internal Clock Frequencies
        3. 6.12.3.3 Input Clocks
        4. 6.12.3.4 XTAL Oscillator
          1. 6.12.3.4.1 Introduction
          2. 6.12.3.4.2 Overview
            1. 6.12.3.4.2.1 Electrical Oscillator
              1. 6.12.3.4.2.1.1 Modes of Operation
                1. 6.12.3.4.2.1.1.1 Crystal Mode of Operation
                2. 6.12.3.4.2.1.1.2 Single-Ended Mode of Operation
              2. 6.12.3.4.2.1.2 XTAL Output on XCLKOUT
            2. 6.12.3.4.2.2 Quartz Crystal
            3. 6.12.3.4.2.3 GPIO Modes of Operation
          3. 6.12.3.4.3 Functional Operation
            1. 6.12.3.4.3.1 ESR – Effective Series Resistance
            2. 6.12.3.4.3.2 Rneg – Negative Resistance
            3. 6.12.3.4.3.3 Start-up Time
            4. 6.12.3.4.3.4 DL – Drive Level
          4. 6.12.3.4.4 How to Choose a Crystal
          5. 6.12.3.4.5 Testing
          6. 6.12.3.4.6 Common Problems and Debug Tips
          7. 6.12.3.4.7 Crystal Oscillator Specifications
            1. 6.12.3.4.7.1 Crystal Oscillator Electrical Characteristics
            2. 6.12.3.4.7.2 Crystal Equivalent Series Resistance (ESR) Requirements
            3. 6.12.3.4.7.3 Crystal Oscillator Parameters
            4. 6.12.3.4.7.4 Crystal Oscillator Electrical Characteristics
        5. 6.12.3.5 Internal Oscillators
          1. 6.12.3.5.1 INTOSC Characteristics
      4. 6.12.4  Flash Parameters
        1. 6.12.4.1 Flash Parameters 
      5. 6.12.5  RAM Specifications
      6. 6.12.6  ROM Specifications
      7. 6.12.7  Emulation/JTAG
        1. 6.12.7.1 JTAG Electrical Data and Timing
          1. 6.12.7.1.1 JTAG Timing Requirements
          2. 6.12.7.1.2 JTAG Switching Characteristics
          3. 6.12.7.1.3 JTAG Timing Diagram
        2. 6.12.7.2 cJTAG Electrical Data and Timing
          1. 6.12.7.2.1 cJTAG Timing Requirements
          2. 6.12.7.2.2 cJTAG Switching Characteristics
          3. 6.12.7.2.3 cJTAG Timing Diagram
      8. 6.12.8  GPIO Electrical Data and Timing
        1. 6.12.8.1 GPIO – Output Timing
          1. 6.12.8.1.1 General-Purpose Output Switching Characteristics
          2. 6.12.8.1.2 General-Purpose Output Timing Diagram
        2. 6.12.8.2 GPIO – Input Timing
          1. 6.12.8.2.1 General-Purpose Input Timing Requirements
          2. 6.12.8.2.2 Sampling Mode
        3. 6.12.8.3 Sampling Window Width for Input Signals
      9. 6.12.9  Interrupts
        1. 6.12.9.1 External Interrupt (XINT) Electrical Data and Timing
          1. 6.12.9.1.1 External Interrupt Timing Requirements
          2. 6.12.9.1.2 External Interrupt Switching Characteristics
          3. 6.12.9.1.3 External Interrupt Timing
      10. 6.12.10 Low-Power Modes
        1. 6.12.10.1 Clock-Gating Low-Power Modes
        2. 6.12.10.2 Low-Power Mode Wake-up Timing
          1. 6.12.10.2.1 IDLE Mode Timing Requirements
          2. 6.12.10.2.2 IDLE Mode Switching Characteristics
          3. 6.12.10.2.3 IDLE Entry and Exit Timing Diagram
          4. 6.12.10.2.4 STANDBY Mode Timing Requirements
          5. 6.12.10.2.5 STANDBY Mode Switching Characteristics
          6. 6.12.10.2.6 STANDBY Entry and Exit Timing Diagram
          7. 6.12.10.2.7 HALT Mode Timing Requirements
          8. 6.12.10.2.8 HALT Mode Switching Characteristics
          9. 6.12.10.2.9 HALT Entry and Exit Timing Diagram
      11. 6.12.11 External Memory Interface (EMIF)
        1. 6.12.11.1 Asynchronous Memory Support
        2. 6.12.11.2 Synchronous DRAM Support
        3. 6.12.11.3 EMIF Electrical Data and Timing
          1. 6.12.11.3.1 EMIF Synchronous Memory Timing Requirements
          2. 6.12.11.3.2 EMIF Synchronous Memory Switching Characteristics
          3. 6.12.11.3.3 EMIF Synchronous Memory Timing Diagrams
          4. 6.12.11.3.4 EMIF Asynchronous Memory Timing Requirements
          5. 6.12.11.3.5 EMIF Asynchronous Memory Switching Characteristics
          6. 6.12.11.3.6 EMIF Asynchronous Memory Timing Diagrams
    13. 6.13 C28x Analog Peripherals
      1. 6.13.1 Analog Subsystem
        1. 6.13.1.1 Features
        2. 6.13.1.2 Block Diagram
      2. 6.13.2 Analog-to-Digital Converter (ADC)
        1. 6.13.2.1 ADC Configurability
          1. 6.13.2.1.1 Signal Mode
        2. 6.13.2.2 ADC Electrical Data and Timing
          1. 6.13.2.2.1  ADC Operating Conditions 12-bit Single-Ended
          2. 6.13.2.2.2  ADC Operating Conditions 12-bit Differential
          3. 6.13.2.2.3  ADC Operating Conditions 16-bit Single-Ended
          4. 6.13.2.2.4  ADC Operating Conditions 16-bit Differential
          5. 6.13.2.2.5  ADC Characteristics 12-bit Single-Ended
          6. 6.13.2.2.6  ADC Characteristics 12-bit Differential
          7. 6.13.2.2.7  ADC Characteristics 16-bit Single-Ended
          8. 6.13.2.2.8  ADC Characteristics 16-bit Differential
          9. 6.13.2.2.9  ADC Performance Per Pin
          10. 6.13.2.2.10 ADC Input Models
          11. 6.13.2.2.11 ADC Timing Diagrams
      3. 6.13.3 Temperature Sensor
        1. 6.13.3.1 Temperature Sensor Electrical Data and Timing
          1. 6.13.3.1.1 Temperature Sensor Characteristics
      4. 6.13.4 Comparator Subsystem (CMPSS)
        1. 6.13.4.1 CMPSS Connectivity Diagram
        2. 6.13.4.2 Block Diagram
        3. 6.13.4.3 CMPSS Electrical Data and Timing
          1. 6.13.4.3.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 6.13.4.3.2 CMPSS DAC Static Electrical Characteristics
          4. 6.13.4.3.3 CMPSS Illustrative Graphs
          5. 6.13.4.3.4 CMPSS DAC Dynamic Error
      5. 6.13.5 Buffered Digital-to-Analog Converter (DAC)
        1. 6.13.5.1 Buffered DAC Electrical Data and Timing
          1. 6.13.5.1.1 Buffered DAC Operating Conditions
          2. 6.13.5.1.2 Buffered DAC Electrical Characteristics
    14. 6.14 C28x Control Peripherals
      1. 6.14.1 Enhanced Capture (eCAP)
        1. 6.14.1.1 eCAP Block Diagram
        2. 6.14.1.2 eCAP Synchronization
        3. 6.14.1.3 eCAP Electrical Data and Timing
          1. 6.14.1.3.1 eCAP Timing Requirements
          2. 6.14.1.3.2 eCAP Switching Characteristics
      2. 6.14.2 High-Resolution Capture (HRCAP)
        1. 6.14.2.1 eCAP and HRCAP Block Diagram
        2. 6.14.2.2 HRCAP Electrical Data and Timing
          1. 6.14.2.2.1 HRCAP Switching Characteristics
          2. 6.14.2.2.2 HRCAP Figure and Graph
      3. 6.14.3 Enhanced Pulse Width Modulator (ePWM)
        1. 6.14.3.1 Control Peripherals Synchronization
        2. 6.14.3.2 ePWM Electrical Data and Timing
          1. 6.14.3.2.1 ePWM Timing Requirements
          2. 6.14.3.2.2 ePWM Switching Characteristics
          3. 6.14.3.2.3 Trip-Zone Input Timing
            1. 6.14.3.2.3.1 Trip-Zone Input Timing Requirements
            2. 6.14.3.2.3.2 PWM Hi-Z Characteristics Timing Diagram
      4. 6.14.4 External ADC Start-of-Conversion Electrical Data and Timing
        1. 6.14.4.1 External ADC Start-of-Conversion Switching Characteristics
        2. 6.14.4.2 ADCSOCAO or ADCSOCBO Timing Diagram
      5. 6.14.5 High-Resolution Pulse Width Modulator (HRPWM)
        1. 6.14.5.1 HRPWM Electrical Data and Timing
          1. 6.14.5.1.1 High-Resolution PWM Characteristics
      6. 6.14.6 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 6.14.6.1 eQEP Electrical Data and Timing
          1. 6.14.6.1.1 eQEP Timing Requirements
          2. 6.14.6.1.2 eQEP Switching Characteristics
      7. 6.14.7 Sigma-Delta Filter Module (SDFM)
        1. 6.14.7.1 SDFM Electrical Data and Timing
          1. 6.14.7.1.1 SDFM Timing Requirements When Using Asynchronous GPIO ASYNC Option
    15. 6.15 C28x Communications Peripherals
      1. 6.15.1  Controller Area Network (CAN)
      2. 6.15.2  Modular Controller Area Network (MCAN)
      3. 6.15.3  Fast Serial Interface (FSI)
        1. 6.15.3.1 FSI Transmitter
          1. 6.15.3.1.1 FSITX Electrical Data and Timing
            1. 6.15.3.1.1.1 FSITX Switching Characteristics
            2. 6.15.3.1.1.2 FSITX Timings
        2. 6.15.3.2 FSI Receiver
          1. 6.15.3.2.1 FSIRX Electrical Data and Timing
            1. 6.15.3.2.1.1 FSIRX Timing Requirements
            2. 6.15.3.2.1.2 FSIRX Switching Characteristics
            3. 6.15.3.2.1.3 FSIRX Timings
        3. 6.15.3.3 FSI SPI Compatibility Mode
          1. 6.15.3.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 6.15.3.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 6.15.3.3.1.2 FSITX SPI Signaling Mode Timings
      4. 6.15.4  Inter-Integrated Circuit (I2C)
        1. 6.15.4.1 I2C Electrical Data and Timing
          1. 6.15.4.1.1 I2C Timing Requirements
          2. 6.15.4.1.2 I2C Switching Characteristics
          3. 6.15.4.1.3 I2C Timing Diagram
      5. 6.15.5  Power Management Bus (PMBus) Interface
        1. 6.15.5.1 PMBus Electrical Data and Timing
          1. 6.15.5.1.1 PMBus Electrical Characteristics
          2. 6.15.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 6.15.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 6.15.6  Serial Communications Interface (SCI)
      7. 6.15.7  Serial Peripheral Interface (SPI)
        1. 6.15.7.1 SPI Controller Mode Timings
          1. 6.15.7.1.1 SPI Controller Mode Switching Characteristics Clock Phase 0
          2. 6.15.7.1.2 SPI Controller Mode Switching Characteristics Clock Phase 1
          3. 6.15.7.1.3 SPI Controller Mode Timing Requirements
          4. 6.15.7.1.4 SPI Controller Mode Timing Diagrams
        2. 6.15.7.2 SPI Peripheral Mode Timings
          1. 6.15.7.2.1 SPI Peripheral Mode Switching Characteristics
          2. 6.15.7.2.2 SPI Peripheral Mode Timing Requirements
          3. 6.15.7.2.3 SPI Peripheral Mode Timing Diagrams
      8. 6.15.8  Local Interconnect Network (LIN)
      9. 6.15.9  EtherCAT SubordinateDevice Controller (ESC)
        1. 6.15.9.1 ESC Features
        2. 6.15.9.2 ESC Subsystem Integrated Features
        3. 6.15.9.3 EtherCAT IP Block Diagram
        4. 6.15.9.4 EtherCAT Electrical Data and Timing
          1. 6.15.9.4.1 EtherCAT Timing Requirements
          2. 6.15.9.4.2 EtherCAT Switching Characteristics
          3. 6.15.9.4.3 EtherCAT Timing Diagrams
      10. 6.15.10 Universal Serial Bus (USB)
        1. 6.15.10.1 USB Electrical Data and Timing
          1. 6.15.10.1.1 USB Input Ports DP and DM Timing Requirements
          2. 6.15.10.1.2 USB Output Ports DP and DM Switching Characteristics
      11. 6.15.11 Universal Asynchronous Receiver-Transmitter (UART)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Memory
      1. 7.3.1 C28x Memory Map
      2. 7.3.2 Control Law Accelerator (CLA) Memory Map
      3. 7.3.3 Flash Memory Map
        1. 7.3.3.1 Addresses of Flash Sectors
      4. 7.3.4 EMIF Chip Select Memory Map
      5. 7.3.5 Peripheral Registers Memory Map
      6. 7.3.6 Memory Types
        1. 7.3.6.1 Dedicated RAM (Mx and Dx RAM)
        2. 7.3.6.2 Local Shared RAM (LSx RAM)
        3. 7.3.6.3 Global Shared RAM (GSx RAM)
        4. 7.3.6.4 CPU Message RAM (CPU MSGRAM)
        5. 7.3.6.5 CLA Message RAM (CLA MSGRAM)
        6. 7.3.6.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
    4. 7.4 Identification
    5. 7.5 Bus Architecture – Peripheral Connectivity
    6. 7.6 Boot ROM
      1. 7.6.1 Device Boot
      2. 7.6.2 Device Boot Modes
      3. 7.6.3 Device Boot Configurations
      4. 7.6.4 GPIO Assignments
    7. 7.7 Security
      1. 7.7.1 Securing the Boundary of the Chip
        1. 7.7.1.1 JTAGLOCK
        2. 7.7.1.2 Zero-pin Boot
      2. 7.7.2 Dual-Zone Security
      3. 7.7.3 Disclaimer
    8. 7.8 Advanced Encryption Standard (AES) Accelerator
    9. 7.9 C28x (CPU1/CPU2) Subsystem
      1. 7.9.1  C28x Processor
        1. 7.9.1.1 Floating-Point Unit (FPU)
        2. 7.9.1.2 Fast Integer Division Unit
        3. 7.9.1.3 Trigonometric Math Unit (TMU)
        4. 7.9.1.4 VCRC Unit
        5. 7.9.1.5 Lockstep Compare Module (LCM)
      2. 7.9.2  Control Law Accelerator (CLA)
      3. 7.9.3  Embedded Real-Time Analysis and Diagnostic (ERAD)
      4. 7.9.4  Background CRC-32 (BGCRC)
      5. 7.9.5  Direct Memory Access (DMA)
      6. 7.9.6  Interprocessor Communication (IPC) Module
      7. 7.9.7  C28x Timers
      8. 7.9.8  Dual-Clock Comparator (DCC)
        1. 7.9.8.1 Features
        2. 7.9.8.2 Mapping of DCCx Clock Source Inputs
      9. 7.9.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 7.9.10 Watchdog
      11. 7.9.11 Configurable Logic Block (CLB)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application and Implementation
    2. 8.2 Key Device Features
    3. 8.3 Application Information
      1. 8.3.1 Typical Application
        1. 8.3.1.1 Servo Drive Control Module
          1. 8.3.1.1.1 System Block Diagram
          2. 8.3.1.1.2 Servo Drive Control Module Resources
        2. 8.3.1.2 Solar Micro Inverter
          1. 8.3.1.2.1 System Block Diagram
          2. 8.3.1.2.2 Solar Micro Inverter Resources
        3. 8.3.1.3 EV Charging Station Power Module
          1. 8.3.1.3.1 System Block Diagram
          2. 8.3.1.3.2 EV Charging Station Power Module Resources
        4. 8.3.1.4 On-Board Charger (OBC)
          1. 8.3.1.4.1 System Block Diagram
          2. 8.3.1.4.2 OBC Resources
        5. 8.3.1.5 High-Voltage Traction Inverter
          1. 8.3.1.5.1 System Block Diagram
          2. 8.3.1.5.2 High-Voltage Traction Inverter Resources
  10. 9 Device and Documentation Support
    1. 9.1 Getting Started and Next Steps
    2. 9.2 Device Nomenclature
    3. 9.3 Markings
    4. 9.4 Tools and Software
    5. 9.5 Documentation Support
    6. 9.6 Support Resources
    7. 9.7 Trademarks
    8. 9.8 Electrostatic Discharge Caution
    9. 9.9 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PZP|100
  • ZEJ|256
  • PTP|176
  • NMR|169
サーマルパッド・メカニカル・データ
発注情報

7.3.5 Peripheral Registers Memory Map

Table 7-6 Peripheral Registers Memory Map
Structure DriverLib Name Base Address CPU1 CPU1.DMA CPU1.CLA1 CPU2 CPU2.DMA Pipeline Protected
Peripheral Frame 0 (PF0)
ADC_RESULT_REGS ADCARESULT_BASE 0x0000_0A00 YES YES YES YES YES -
ADC_RESULT_REGS ADCBRESULT_BASE 0x0000_0A80 YES YES YES YES YES -
ADC_RESULT_REGS ADCCRESULT_BASE 0x0000_0B00 YES YES YES YES YES -
CPUTIMER_REGS CPUTIMER0_BASE 0x0000_0C00 YES - - YES - -
CLA_ONLY_REGS CLA1_ONLY_BASE 0x0000_0C00 - - YES - - -
CPUTIMER_REGS CPUTIMER1_BASE 0x0000_0C08 YES - - YES - -
CPUTIMER_REGS CPUTIMER2_BASE 0x0000_0C10 YES - - YES - -
PIE_CTRL_REGS PIECTRL_BASE 0x0000_0CE0 YES - - YES - -
CLA_SOFTINT_REGS CLA1_SOFTINT_BASE 0x0000_0CE0 - - YES - - -
PIE_VECT_TABLE PIEVECTTABLEMAIN_BASE 0x0000_0D00 YES - - YES - -
PIE_VECT_TABLE PIEVECTTABLEEXTENSION_BASE 0x0000_0E00 YES - - YES - -
DMA_REGS DMA_BASE 0x0000_1000 YES - - YES - -
DMA_CH_REGS DMA_CH1_BASE 0x0000_1020 YES - - YES - -
DMA_CH_REGS DMA_CH2_BASE 0x0000_1040 YES - - YES - -
DMA_CH_REGS DMA_CH3_BASE 0x0000_1060 YES - - YES - -
DMA_CH_REGS DMA_CH4_BASE 0x0000_1080 YES - - YES - -
DMA_CH_REGS DMA_CH5_BASE 0x0000_10A0 YES - - YES - -
DMA_CH_REGS DMA_CH6_BASE 0x0000_10C0 YES - - YES - -
CLA_REGS CLA1_BASE 0x0000_1400 YES - - - - -
ESCSS_REGS ESC_SS_BASE 0x0005_7E00 YES - - YES - YES
ESCSS_CONFIG_REGS ESC_SS_CONFIG_BASE 0x0005_7F00 YES - - YES - YES
PCTRACE_BUFFER_REGS ERAD_PCTRACE_BUFFER_BASE 0x0005_FE00 YES - - YES - YES
UID_REGS UID_BASE 0x0007_2172 YES - - - - -
DCSM_Z1_OTP DCSM_Z1OTP_BASE 0x0007_8000 YES - - - - -
DCSM_Z2_OTP DCSM_Z2OTP_BASE 0x0007_8200 YES - - - - -
Peripheral Frame 1 (PF1)
EPWM_REGS EPWM17_BASE 0x0000_2C00 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM17XCMP_BASE 0x0000_2D00 YES YES YES YES YES YES
DE_REGS EPWM17DE_BASE 0x0000_2DC0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM17MINDBLUT_BASE 0x0000_2DE0 YES YES YES YES YES YES
EPWM_REGS EPWM18_BASE 0x0000_2E00 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM18XCMP_BASE 0x0000_2F00 YES YES YES YES YES YES
DE_REGS EPWM18DE_BASE 0x0000_2FC0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM18MINDBLUT_BASE 0x0000_2FE0 YES YES YES YES YES YES
EPWM_REGS EPWM1_BASE 0x0000_3000 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM1XCMP_BASE 0x0000_3100 YES YES YES YES YES YES
DE_REGS EPWM1DE_BASE 0x0000_31C0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM1MINDBLUT_BASE 0x0000_31E0 YES YES YES YES YES YES
EPWM_REGS EPWM2_BASE 0x0000_3200 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM2XCMP_BASE 0x0000_3300 YES YES YES YES YES YES
DE_REGS EPWM2DE_BASE 0x0000_33C0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM2MINDBLUT_BASE 0x0000_33E0 YES YES YES YES YES YES
EPWM_REGS EPWM3_BASE 0x0000_3400 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM3XCMP_BASE 0x0000_3500 YES YES YES YES YES YES
DE_REGS EPWM3DE_BASE 0x0000_35C0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM3MINDBLUT_BASE 0x0000_35E0 YES YES YES YES YES YES
EPWM_REGS EPWM4_BASE 0x0000_3600 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM4XCMP_BASE 0x0000_3700 YES YES YES YES YES YES
DE_REGS EPWM4DE_BASE 0x0000_37C0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM4MINDBLUT_BASE 0x0000_37E0 YES YES YES YES YES YES
EPWM_REGS EPWM5_BASE 0x0000_3800 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM5XCMP_BASE 0x0000_3900 YES YES YES YES YES YES
DE_REGS EPWM5DE_BASE 0x0000_39C0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM5MINDBLUT_BASE 0x0000_39E0 YES YES YES YES YES YES
EPWM_REGS EPWM6_BASE 0x0000_3A00 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM6XCMP_BASE 0x0000_3B00 YES YES YES YES YES YES
DE_REGS EPWM6DE_BASE 0x0000_3BC0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM6MINDBLUT_BASE 0x0000_3BE0 YES YES YES YES YES YES
EPWM_REGS EPWM7_BASE 0x0000_3C00 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM7XCMP_BASE 0x0000_3D00 YES YES YES YES YES YES
DE_REGS EPWM7DE_BASE 0x0000_3DC0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM7MINDBLUT_BASE 0x0000_3DE0 YES YES YES YES YES YES
EPWM_REGS EPWM8_BASE 0x0000_3E00 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM8XCMP_BASE 0x0000_3F00 YES YES YES YES YES YES
DE_REGS EPWM8DE_BASE 0x0000_3FC0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM8MINDBLUT_BASE 0x0000_3FE0 YES YES YES YES YES YES
EPWM_REGS EPWM9_BASE 0x0000_4000 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM9XCMP_BASE 0x0000_4100 YES YES YES YES YES YES
DE_REGS EPWM9DE_BASE 0x0000_41C0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM9MINDBLUT_BASE 0x0000_41E0 YES YES YES YES YES YES
EPWM_REGS EPWM10_BASE 0x0000_4200 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM10XCMP_BASE 0x0000_4300 YES YES YES YES YES YES
DE_REGS EPWM10DE_BASE 0x0000_43C0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM10MINDBLUT_BASE 0x0000_43E0 YES YES YES YES YES YES
EPWM_REGS EPWM11_BASE 0x0000_4400 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM11XCMP_BASE 0x0000_4500 YES YES YES YES YES YES
DE_REGS EPWM11DE_BASE 0x0000_45C0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM11MINDBLUT_BASE 0x0000_45E0 YES YES YES YES YES YES
EPWM_REGS EPWM12_BASE 0x0000_4600 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM12XCMP_BASE 0x0000_4700 YES YES YES YES YES YES
DE_REGS EPWM12DE_BASE 0x0000_47C0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM12MINDBLUT_BASE 0x0000_47E0 YES YES YES YES YES YES
EPWM_REGS EPWM13_BASE 0x0000_4800 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM13XCMP_BASE 0x0000_4900 YES YES YES YES YES YES
DE_REGS EPWM13DE_BASE 0x0000_49C0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM13MINDBLUT_BASE 0x0000_49E0 YES YES YES YES YES YES
EPWM_REGS EPWM14_BASE 0x0000_4A00 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM14XCMP_BASE 0x0000_4B00 YES YES YES YES YES YES
DE_REGS EPWM14DE_BASE 0x0000_4BC0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM14MINDBLUT_BASE 0x0000_4BE0 YES YES YES YES YES YES
EPWM_REGS EPWM15_BASE 0x0000_4C00 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM15XCMP_BASE 0x0000_4D00 YES YES YES YES YES YES
DE_REGS EPWM15DE_BASE 0x0000_4DC0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM15MINDBLUT_BASE 0x0000_4DE0 YES YES YES YES YES YES
EPWM_REGS EPWM16_BASE 0x0000_4E00 YES YES YES YES YES YES
EPWM_XCMP_REGS EPWM16XCMP_BASE 0x0000_4F00 YES YES YES YES YES YES
DE_REGS EPWM16DE_BASE 0x0000_4FC0 YES YES YES YES YES YES
MINDB_LUT_REGS EPWM16MINDBLUT_BASE 0x0000_4FE0 YES YES YES YES YES YES
EQEP_REGS EQEP1_BASE 0x0000_5080 YES YES YES YES YES YES
EQEP_REGS EQEP2_BASE 0x0000_50C0 YES YES YES YES YES YES
EQEP_REGS EQEP3_BASE 0x0000_5100 YES YES YES YES YES YES
EQEP_REGS EQEP4_BASE 0x0000_5140 YES YES YES YES YES YES
EQEP_REGS EQEP5_BASE 0x0000_5180 YES YES YES YES YES YES
EQEP_REGS EQEP6_BASE 0x0000_51C0 YES YES YES YES YES YES
ECAP_REGS ECAP1_BASE 0x0000_5200 YES YES YES YES YES YES
ECAP_SIGNAL_MONITORING ECAP1SIGNALMONITORING_BASE 0x0000_5240 YES YES YES YES YES YES
ECAP_REGS ECAP2_BASE 0x0000_5300 YES YES YES YES YES YES
ECAP_SIGNAL_MONITORING ECAP2SIGNALMONITORING_BASE 0x0000_5340 YES YES YES YES YES YES
ECAP_REGS ECAP3_BASE 0x0000_5400 YES YES YES YES YES YES
ECAP_SIGNAL_MONITORING ECAP3SIGNALMONITORING_BASE 0x0000_5440 YES YES YES YES YES YES
ECAP_REGS ECAP4_BASE 0x0000_5500 YES YES YES YES YES YES
ECAP_SIGNAL_MONITORING ECAP4SIGNALMONITORING_BASE 0x0000_5540 YES YES YES YES YES YES
ECAP_REGS ECAP5_BASE 0x0000_5600 YES YES YES YES YES YES
ECAP_SIGNAL_MONITORING ECAP5SIGNALMONITORING_BASE 0x0000_5640 YES YES YES YES YES YES
ECAP_REGS ECAP6_BASE 0x0000_5700 YES YES YES YES YES YES
HRCAP_REGS HRCAP6_BASE 0x0000_5720 YES YES YES YES YES YES
ECAP_SIGNAL_MONITORING ECAP6SIGNALMONITORING_BASE 0x0000_5740 YES YES YES YES YES YES
ECAP_REGS ECAP7_BASE 0x0000_5800 YES YES YES YES YES YES
HRCAP_REGS HRCAP7_BASE 0x0000_5820 YES YES YES YES YES YES
ECAP_SIGNAL_MONITORING ECAP7SIGNALMONITORING_BASE 0x0000_5840 YES YES YES YES YES YES
CMPSS_REGS CMPSS1_BASE 0x0000_5900 YES YES YES YES YES YES
CMPSS_REGS CMPSS2_BASE 0x0000_5940 YES YES YES YES YES YES
CMPSS_REGS CMPSS3_BASE 0x0000_5980 YES YES YES YES YES YES
CMPSS_REGS CMPSS4_BASE 0x0000_59C0 YES YES YES YES YES YES
CMPSS_REGS CMPSS5_BASE 0x0000_5A00 YES YES YES YES YES YES
CMPSS_REGS CMPSS6_BASE 0x0000_5A40 YES YES YES YES YES YES
CMPSS_REGS CMPSS7_BASE 0x0000_5A80 YES YES YES YES YES YES
CMPSS_REGS CMPSS8_BASE 0x0000_5AC0 YES YES YES YES YES YES
CMPSS_REGS CMPSS9_BASE 0x0000_5B00 YES YES YES YES YES YES
CMPSS_REGS CMPSS10_BASE 0x0000_5B40 YES YES YES YES YES YES
CMPSS_REGS CMPSS11_BASE 0x0000_5B80 YES YES YES YES YES YES
DAC_REGS DACA_BASE 0x0000_5C00 YES YES YES YES YES YES
DAC_REGS DACC_BASE 0x0000_5C20 YES YES YES YES YES YES
HRPWMCAL_REGS HRPWMCAL1_BASE 0x0000_5C80 YES YES YES YES YES YES
HRPWMCAL_REGS HRPWMCAL2_BASE 0x0000_5CC0 YES YES YES YES YES YES
HRPWMCAL_REGS HRPWMCAL3_BASE 0x0000_5D00 YES YES YES YES YES YES
SDFM_REGS SDFM1_BASE 0x0000_5E00 YES YES YES YES YES YES
SDFM_REGS SDFM2_BASE 0x0000_5E80 YES YES YES YES YES YES
SDFM_REGS SDFM3_BASE 0x0000_5F00 YES YES YES YES YES YES
SDFM_REGS SDFM4_BASE 0x0000_5F80 YES YES YES YES YES YES
Peripheral Frame 2 (PF2)
SPI_REGS SPIA_BASE 0x0000_6100 YES YES YES YES YES YES
SPI_REGS SPIB_BASE 0x0000_6110 YES YES YES YES YES YES
SPI_REGS SPIC_BASE 0x0000_6120 YES YES YES YES YES YES
SPI_REGS SPID_BASE 0x0000_6130 YES YES YES YES YES YES
BGCRC_REGS BGCRC_CPU_BASE 0x0000_6340 YES - - YES - YES
BGCRC_REGS BGCRC_CLA_BASE 0x0000_6380 YES - YES - - YES
PMBUS_REGS PMBUSA_BASE 0x0000_6400 YES YES YES YES YES YES
FSI_TX_REGS FSITXA_BASE 0x0000_6600 YES YES YES YES YES YES
FSI_RX_REGS FSIRXA_BASE 0x0000_6680 YES YES YES YES YES YES
FSI_TX_REGS FSITXB_BASE 0x0000_6700 YES YES YES YES YES YES
FSI_RX_REGS FSIRXB_BASE 0x0000_6780 YES YES YES YES YES YES
FSI_RX_REGS FSIRXC_BASE 0x0000_6880 YES YES YES YES YES YES
FSI_RX_REGS FSIRXD_BASE 0x0000_6980 YES YES YES YES YES YES
Peripheral Frame 3 (PF3)
ADC_REGS ADCA_BASE 0x0000_7400 YES - YES YES - YES
ADC_REGS ADCB_BASE 0x0000_7500 YES - YES YES - YES
ADC_REGS ADCC_BASE 0x0000_7600 YES - YES YES - YES
Peripheral Frame 4 (PF4)
EPWM_XBAR_REGS EPWMXBARB_BASE 0x0000_7800 YES - - - - YES
SYNC_SOC_REGS SYNCSOC_BASE 0x0000_78F8 YES - - - - YES
INPUT_XBAR_REGS INPUTXBAR_BASE 0x0000_7900 YES - - - - YES
XBAR_REGS XBAR_BASE 0x0000_7920 YES - - - - YES
INPUT_XBAR_REGS CLBINPUTXBAR_BASE 0x0000_7960 YES - - - - YES
CPU1_DMA_CLA_SRC_SEL_REGS, CPU2_DMA_CLA_SRC_SEL_REGS CPU1DMACLASRCSEL_BASE, CPU2DMACLASRCSEL_BASE 0x0000_7980 YES - - YES - YES
MINDB_XBAR_REGS MINDBXBAR_BASE 0x0000_79C0 YES - - - - YES
ICL_XBAR_REGS ICLXBAR_BASE 0x0000_79E0 YES - - - - YES
EPWM_XBAR_REGS EPWMXBARA_BASE 0x0000_7A00 YES - - - - YES
CLB_XBAR_REGS CLBXBAR_BASE 0x0000_7A80 YES - - - - YES
OUTPUT_XBAR_EXT64_REGS OUTPUTXBAR_BASE 0x0000_7B00 YES - - - - YES
OUTPUT_XBAR_REGS CLBOUTPUTXBAR_BASE 0x0000_7B80 YES - - - - YES
GPIO_CTRL_REGS GPIOCTRL_BASE 0x0000_7C00 YES - - - - YES
GPIO_DATA_REGS GPIODATA_BASE 0x0000_7F00 YES - YES YES - YES
GPIO_DATA_READ_REGS GPIODATAREAD_BASE 0x0000_7F80 YES - YES YES - YES
Peripheral Frame 5 (PF5)
EMIF_REGS EMIF1_BASE 0x0004_7000 YES - - YES - YES
CPU1TOCPU2_IPC_REGS_CPU2VIEW IPC_CPUXTOCPUX_BASE 0x0005_CE00 - - - YES - YES
CPU1TOCPU2_IPC_REGS_CPU1VIEW IPC_CPUXTOCPUX_BASE 0x0005_CE00 YES - - - - YES
DEV_CFG_REGS DEVCFG_BASE 0x0005_D000 YES - - YES - YES
CLK_CFG_REGS CLKCFG_BASE 0x0005_D200 YES - - YES - YES
CPU1_SYS_REGS, CPU2_SYS_REGS CPU1SYS_BASE, CPU2SYS_BASE 0x0005_D300 YES - - YES - YES
CPU1_SYS_STATUS_REGS, CPU2_SYS_STATUS_REGS CPU1SYSSTATUS_BASE, CPU2SYSSTATUS_BASE 0x0005_D400 YES - - YES - YES
CPU1_PERIPH_AC_REGS, CPU2_PERIPH_AC_REGS CPU1PERIPHAC_BASE, CPU2PERIPHAC_BASE 0x0005_D500 YES - - YES - YES
ANALOG_SUBSYS_REGS ANALOGSUBSYS_BASE 0x0005_D700 YES - - - - YES
ERAD_GLOBAL_REGS ERAD_GLOBAL_BASE 0x0005_E800 YES - - YES - YES
ERAD_HWBP_REGS ERAD_HWBP1_BASE 0x0005_E900 YES - - YES - YES
ERAD_HWBP_REGS ERAD_HWBP2_BASE 0x0005_E908 YES - - YES - YES
ERAD_HWBP_REGS ERAD_HWBP3_BASE 0x0005_E910 YES - - YES - YES
ERAD_HWBP_REGS ERAD_HWBP4_BASE 0x0005_E918 YES - - YES - YES
ERAD_HWBP_REGS ERAD_HWBP5_BASE 0x0005_E920 YES - - YES - YES
ERAD_HWBP_REGS ERAD_HWBP6_BASE 0x0005_E928 YES - - YES - YES
ERAD_HWBP_REGS ERAD_HWBP7_BASE 0x0005_E930 YES - - YES - YES
ERAD_HWBP_REGS ERAD_HWBP8_BASE 0x0005_E938 YES - - YES - YES
ERAD_COUNTER_REGS ERAD_COUNTER1_BASE 0x0005_E980 YES - - YES - YES
ERAD_COUNTER_REGS ERAD_COUNTER2_BASE 0x0005_E990 YES - - YES - YES
ERAD_COUNTER_REGS ERAD_COUNTER3_BASE 0x0005_E9A0 YES - - YES - YES
ERAD_COUNTER_REGS ERAD_COUNTER4_BASE 0x0005_E9B0 YES - - YES - YES
ERAD_CRC_GLOBAL_REGS ERAD_CRC_GLOBAL_BASE 0x0005_EA00 YES - - YES - YES
ERAD_CRC_REGS ERAD_CRC1_BASE 0x0005_EA10 YES - - YES - YES
ERAD_CRC_REGS ERAD_CRC2_BASE 0x0005_EA20 YES - - YES - YES
ERAD_CRC_REGS ERAD_CRC3_BASE 0x0005_EA30 YES - - YES - YES
ERAD_CRC_REGS ERAD_CRC4_BASE 0x0005_EA40 YES - - YES - YES
ERAD_CRC_REGS ERAD_CRC5_BASE 0x0005_EA50 YES - - YES - YES
ERAD_CRC_REGS ERAD_CRC6_BASE 0x0005_EA60 YES - - YES - YES
ERAD_CRC_REGS ERAD_CRC7_BASE 0x0005_EA70 YES - - YES - YES
ERAD_CRC_REGS ERAD_CRC8_BASE 0x0005_EA80 YES - - YES - YES
PCTRACE_REGS ERAD_PCTRACE_BASE 0x0005_EAD0 YES - - YES - YES
EPG_REGS EPG_BASE 0x0005_EC00 YES - - YES - YES
EPG_MUX_REGS EPGMUX_BASE 0x0005_ECD0 YES - - YES - YES
ADC_SAFECHECK_INTEVT_REGS ADCSAFETYINTEVTAGG1_BASE 0x0005_EE00 YES - - - - YES
ADC_SAFECHECK_INTEVT_REGS ADCSAFETYINTEVTAGG2_BASE 0x0005_EE40 - - - YES - YES
ADC_SAFECHECK_REGS ADCSAFETYCHK1_BASE 0x0005_EE80 YES - - YES - YES
ADC_SAFECHECK_REGS ADCSAFETYCHK2_BASE 0x0005_EE90 YES - - YES - YES
ADC_SAFECHECK_REGS ADCSAFETYCHK3_BASE 0x0005_EEA0 YES - - YES - YES
ADC_SAFECHECK_REGS ADCSAFETYCHK4_BASE 0x0005_EEB0 YES - - YES - YES
ADC_SAFECHECK_REGS ADCSAFETYCHK5_BASE 0x0005_EEC0 YES - - YES - YES
ADC_SAFECHECK_REGS ADCSAFETYCHK6_BASE 0x0005_EED0 YES - - YES - YES
ADC_SAFECHECK_REGS ADCSAFETYCHK7_BASE 0x0005_EEE0 YES - - YES - YES
ADC_SAFECHECK_REGS ADCSAFETYCHK8_BASE 0x0005_EEF0 YES - - YES - YES
DCSM_Z1_REGS DCSM_Z1_BASE 0x0005_F000 YES - - YES - YES
DCSM_Z2_REGS DCSM_Z2_BASE 0x0005_F080 YES - - YES - YES
DCSM_COMMON_REGS DCSMCOMMON_BASE 0x0005_F0C0 YES - - YES - YES
MEM_CFG_REGS MEMCFG_BASE 0x0005_F400 YES - - YES - YES
EMIF1_CONFIG_REGS EMIF1CONFIG_BASE 0x0005_F4C0 YES - - YES - YES
ACCESS_PROTECTION_REGS ACCESSPROTECTION_BASE 0x0005_F500 YES - - YES - YES
MEMORY_ERROR_REGS MEMORYERROR_BASE 0x0005_F540 YES - - YES - YES
ROM_WAIT_STATE_REGS ROMWAITSTATE_BASE 0x0005_F580 YES - - YES - YES
TEST_ERROR_REGS TESTERROR_BASE 0x0005_F590 YES - - YES - YES
FLASH_CTRL_REGS FLASH0CTRL_BASE 0x0005_F800 YES - - YES - YES
FLASH_ECC_REGS FLASH0ECC_BASE 0x0005_FB00 YES - - YES - YES
Peripheral Frame 7 (PF7)
CAN_REGS CANA_BASE 0x0004_8000 YES YES - YES YES YES
LCM_REGS LCM_CPU2_BASE 0x0004_C800 - - - YES - YES
LCM_REGS LCM_CPU2.DMA1_BASE 0x0004_E800 - - - YES - YES
MCANSS_REGS MCANASS_BASE 0x0005_A400 YES - - YES - YES
MCAN_REGS MCANA_BASE 0x0005_A600 YES - - YES - YES
MCAN_ERROR_REGS MCANA_ERROR_BASE 0x0005_A800 YES - - YES - YES
MCANSS_REGS MCANBSS_BASE 0x0005_C400 YES - - YES - YES
MCAN_REGS MCANB_BASE 0x0005_C600 YES - - YES - YES
MCAN_ERROR_REGS MCANB_ERROR_BASE 0x0005_C800 YES - - YES - YES
DCC_REGS DCC0_BASE 0x0005_E700 YES - - YES - YES
DCC_REGS DCC1_BASE 0x0005_E740 YES - - YES - YES
DCC_REGS DCC2_BASE 0x0005_E780 YES - - YES - YES
Peripheral Frame 8 (PF8)
LIN_REGS LINA_BASE 0x0000_6E00 YES YES YES YES YES YES
LIN_REGS LINB_BASE 0x0000_6F00 YES YES YES YES YES YES
Peripheral Frame 9 (PF9)
WD_REGS WD_BASE 0x0000_7000 YES - - YES - YES
NMI_INTRUPT_REGS NMI_BASE 0x0000_7060 YES - - YES - YES
XINT_REGS XINT_BASE 0x0000_7070 YES - - YES - YES
SCI_REGS SCIA_BASE 0x0000_7200 YES - - YES - YES
SCI_REGS SCIB_BASE 0x0000_7210 YES - - YES - YES
I2C_REGS I2CA_BASE 0x0000_7300 YES - - YES - YES
I2C_REGS I2CB_BASE 0x0000_7340 YES - - YES - YES
Peripheral Frame 10 (PF10)
CLB_LOGIC_CONFIG_REGS CLB1_LOGICCFG_BASE 0x0000_2000 YES - YES YES - YES
CLB_LOGIC_CONTROL_REGS CLB1_LOGICCTRL_BASE 0x0000_2100 YES - YES YES - YES
CLB_DATA_EXCHANGE_REGS CLB1_DATAEXCH_BASE 0x0000_2180 YES - YES YES - YES
CLB_LOGIC_CONFIG_REGS CLB2_LOGICCFG_BASE 0x0000_2200 YES - YES YES - YES
CLB_LOGIC_CONTROL_REGS CLB2_LOGICCTRL_BASE 0x0000_2300 YES - YES YES - YES
CLB_DATA_EXCHANGE_REGS CLB2_DATAEXCH_BASE 0x0000_2380 YES - YES YES - YES
CLB_LOGIC_CONFIG_REGS CLB3_LOGICCFG_BASE 0x0000_2400 YES - YES YES - YES
CLB_LOGIC_CONTROL_REGS CLB3_LOGICCTRL_BASE 0x0000_2500 YES - YES YES - YES
CLB_DATA_EXCHANGE_REGS CLB3_DATAEXCH_BASE 0x0000_2580 YES - YES YES - YES
CLB_LOGIC_CONFIG_REGS CLB4_LOGICCFG_BASE 0x0000_2600 YES - YES YES - YES
CLB_LOGIC_CONTROL_REGS CLB4_LOGICCTRL_BASE 0x0000_2700 YES - YES YES - YES
CLB_DATA_EXCHANGE_REGS CLB4_DATAEXCH_BASE 0x0000_2780 YES - YES YES - YES
CLB_LOGIC_CONFIG_REGS CLB5_LOGICCFG_BASE 0x0000_2800 YES - YES YES - YES
CLB_LOGIC_CONTROL_REGS CLB5_LOGICCTRL_BASE 0x0000_2900 YES - YES YES - YES
CLB_DATA_EXCHANGE_REGS CLB5_DATAEXCH_BASE 0x0000_2980 YES - YES YES - YES
CLB_LOGIC_CONFIG_REGS CLB6_LOGICCFG_BASE 0x0000_2A00 YES - YES YES - YES
CLB_LOGIC_CONTROL_REGS CLB6_LOGICCTRL_BASE 0x0000_2B00 YES - YES YES - YES
CLB_DATA_EXCHANGE_REGS CLB6_DATAEXCH_BASE 0x0000_2B80 YES - YES YES - YES
Peripheral Frame 11 (PF11)
USB_REGS USBA_BASE 0x0004_0000 YES YES - YES YES YES
AES_REGS AESA_BASE 0x0004_2000 YES YES - YES YES YES
AES_SS_REGS AESA_SS_BASE 0x0004_2C00 YES YES - YES YES YES
UART_REGS, UART_REGS_WRITE UARTA_BASE, UARTAWRITE_BASE 0x0006_A000 YES YES - YES YES YES
UART_REGS, UART_REGS_WRITE UARTB_BASE, UARTBWRITE_BASE 0x0006_A800 YES YES - YES YES YES
Peripheral Frame 12 (PF12)
CPU1_LFU_REGS, CPU2_LFU_REGS CPU1LFU_BASE, CPU2LFU_BASE 0x0000_7FE0 YES - YES YES - YES