SPRSP69 Data sheet

SPRSP69B July 2023 – November 2023 TMS320F28P650DK , TMS320F28P659DK-Q1

PRODMIX

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）

PZP|100
ZEJ|256
PTP|176
NMR|169

サーマルパッド・メカニカル・データ

発注情報

6.14.7 Sigma-Delta Filter Module (SDFM)

SDFM features include:

Eight external pins per SDFM module
- Four sigma-delta data input pins per SDFM module (SD-Dx, where x = 1 to 4)
- Four sigma-delta clock input pins per SDFM module (SD-Cx, where x = 1 to 4)
Different configurable modulator clock modes supported:
- Mode 0: Modulator clock rate equals the modulator data rate.
Four independent, configurable secondary filter (comparator) units per SDFM module:
- Four different filter type selection (Sinc1/Sinc2/SincFast/Sinc3) options available
- Ability to detect over-value condition, under-value condition, and Threshold-crossing conditions
  1. Two independent Higher Threshold comparators (used to detect over-value condition)
  2. Two independent Lower Threshold comparators (used to detect under-value condition)
  3. One independent Threshold-Crossing comparator (used to measure duty cycle/frequency with eCAP)
- OSR value for comparator filter unit (COSR) programmable from 1 to 32
Four independent configurable primary filter (data filter) units per SDFM module:
- Four different filter type selection (Sinc1/Sinc2/SincFast/Sinc3) options available
- OSR value for data filter unit (DOSR) programmable from 1 to 256
- Ability to enable or disable (or both) individual filter module
- Ability to synchronize all four independent filters of an SDFM module by using the Main Filter Enable (MFE) bit or by using PWM signals
Data filter output can be represented in either 16 bits or 32 bits.
Data filter unit has a programmable mode FIFO to reduce interrupt overhead. The FIFO has the following features:
- The primary filter (data filter) has a 16-deep x 32-bit FIFO.
- The FIFO can interrupt the CPU after programmable number of data-ready events.
- FIFO Wait-for-Sync feature: Ability to ignore data-ready events until the PWM synchronization signal (SDSYNC) is received. Once the SDSYNC event is received, the FIFO is populated on every data-ready event.
- Data filter output can be represented in either 16 bits or 32 bits.
PWMx.SOCA/SOCB can be configured to serve as SDSYNC source on a per-data-filter-channel basis.
PWMs can be used to generate a modulator clock for sigma-delta modulators.
Configurable Input Qualification available for both SD-Cx and SD-Dx
Ability to use one filter channel clock (SD-C1) to provide clock to other filter clock channels.
Configurable digital filter available on comparator filter events to blank out comparator events caused by spurious noise

Figure 6-82 shows the SDFM module block diagram.

Figure 6-82 Sigma Delta Filter Module (SDFM) Block Diagram