SPNS226E June   2013  – November 2016 TMS570LS0714

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. 4.1.1 PGE QFP Package Pinout (144-Pin)
      2. 4.1.2 PZ QFP Package Pinout (100-Pin)
    2. 4.2 Signal Descriptions
      1. 4.2.1 PGE Package Terminal Functions
        1. 4.2.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.2.1.2  Enhanced High-End Timer (N2HET) Modules
        3. 4.2.1.3  Enhanced Capture Modules (eCAP)
        4. 4.2.1.4  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        5. 4.2.1.5  Enhanced Pulse-Width Modulator Modules (ePWM)
        6. 4.2.1.6  General-Purpose Input/Output (GIO)
        7. 4.2.1.7  Controller Area Network Controllers (DCAN)
        8. 4.2.1.8  Local Interconnect Network Interface Module (LIN)
        9. 4.2.1.9  Standard Serial Communication Interface (SCI)
        10. 4.2.1.10 Inter-Integrated Circuit Interface Module (I2C)
        11. 4.2.1.11 Standard Serial Peripheral Interface (SPI)
        12. 4.2.1.12 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        13. 4.2.1.13 System Module Interface
        14. 4.2.1.14 Clock Inputs and Outputs
        15. 4.2.1.15 Test and Debug Modules Interface
        16. 4.2.1.16 Flash Supply and Test Pads
        17. 4.2.1.17 Supply for Core Logic: 1.2V nominal
        18. 4.2.1.18 Supply for I/O Cells: 3.3V nominal
        19. 4.2.1.19 Ground Reference for All Supplies Except VCCAD
      2. 4.2.2 PZ Package Terminal Functions
        1. 4.2.2.1  High-End Timer (N2HET) Modules
        2. 4.2.2.2  Enhanced Capture Modules (eCAP)
        3. 4.2.2.3  Enhanced Quadrature Encoder Pulse Modules (eQEP)
        4. 4.2.2.4  Enhanced Pulse-Width Modulator Modules (ePWM)
        5. 4.2.2.5  General-Purpose Input/Output (GIO)
        6. 4.2.2.6  Controller Area Network Interface Modules (DCAN1, DCAN2)
        7. 4.2.2.7  Standard Serial Peripheral Interfaces (SPI2 and SPI4)
        8. 4.2.2.8  Multibuffered Serial Peripheral Interface (MibSPI1 and MibSPI3)
        9. 4.2.2.9  Local Interconnect Network Controller (LIN)
        10. 4.2.2.10 Multibuffered Analog-to-Digital Converter (MibADC)
        11. 4.2.2.11 System Module Interface
        12. 4.2.2.12 Clock Inputs and Outputs
        13. 4.2.2.13 Test and Debug Modules Interface
        14. 4.2.2.14 Flash Supply and Test Pads
        15. 4.2.2.15 Supply for Core Logic: 1.2-V Nominal
        16. 4.2.2.16 Supply for I/O Cells: 3.3-V Nominal
        17. 4.2.2.17 Ground Reference for All Supplies Except VCCAD
    3. 4.3 Pin Multiplexing
      1. 4.3.1 Output Multiplexing
      2. 4.3.2 Multiplexing of Inputs
    4. 4.4 Buffer Type
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Input/Output Electrical Characteristics Over Recommended Operating Conditions
    6. 5.6 Power Consumption Over Recommended Operating Conditions
    7. 5.7 Thermal Resistance Characteristics
    8. 5.8 Timing and Switching Characteristics
      1. 5.8.1 SYSCLK (Frequencies)
        1. 5.8.1.1 Switching Characteristics over Recommended Operating Conditions for Clock Domains
        2. 5.8.1.2 Wait States Required - PGE and PZ Packages
  6. 6 System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power-On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase-Locked Loop (PLL) Clock Module
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Special Consideration for CPU Access Errors Resulting in Imprecise Aborts
      4. 6.9.4 Master/Slave Access Privileges
      5. 6.9.5 Special Notes on Accesses to Certain Slaves
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Program Flash
      6. 6.10.6 Data Flash
    11. 6.11 Tightly Coupled RAM Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAMW ECC Support
    12. 6.12 Parity Protection for Accesses to Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 Vectored Interrupt Manager
      1. 6.14.1 VIM Features
      2. 6.14.2 Interrupt Request Assignments
    15. 6.15 DMA Controller
      1. 6.15.1 DMA Features
      2. 6.15.2 Default DMA Request Map
    16. 6.16 Real-Time Interrupt Module
      1. 6.16.1 Features
      2. 6.16.2 Block Diagrams
      3. 6.16.3 Clock Source Options
      4. 6.16.4 Network Time Synchronization Inputs
    17. 6.17 Error Signaling Module
      1. 6.17.1 ESM Features
      2. 6.17.2 ESM Channel Assignments
    18. 6.18 Reset/Abort/Error Sources
    19. 6.19 Digital Windowed Watchdog
    20. 6.20 Debug Subsystem
      1. 6.20.1 Block Diagram
      2. 6.20.2 Debug Components Memory Map
      3. 6.20.3 JTAG Identification Code
      4. 6.20.4 Debug ROM
      5. 6.20.5 JTAG Scan Interface Timings
      6. 6.20.6 Advanced JTAG Security Module
      7. 6.20.7 Boundary Scan Chain
  7. 7 Peripheral Information and Electrical Specifications
    1. 7.1  I/O Timings
      1. 7.1.1 Input Timings
      2. 7.1.2 Output Timings
        1. 7.1.2.1 Low-EMI Output Buffers
    2. 7.2  Enhanced PWM Modules (ePWM)
      1. 7.2.1 ePWM Clocking and Reset
      2. 7.2.2 Synchronization of ePWMx Time-Base Counters
      3. 7.2.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base
      4. 7.2.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 7.2.5 ePWM Synchronization with External Devices
      6. 7.2.6 ePWM Trip Zones
        1. 7.2.6.1 Trip Zones TZ1n, TZ2n, TZ3n
        2. 7.2.6.2 Trip Zone TZ4n
        3. 7.2.6.3 Trip Zone TZ5n
        4. 7.2.6.4 Trip Zone TZ6n
      7. 7.2.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs
      8. 7.2.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings
    3. 7.3  Enhanced Capture Modules (eCAP)
      1. 7.3.1 Clock Enable Control for eCAPx Modules
      2. 7.3.2 PWM Output Capability of eCAPx
      3. 7.3.3 Input Connection to eCAPx Modules
      4. 7.3.4 Enhanced Capture Module (eCAP) Electrical Data/Timing
    4. 7.4  Enhanced Quadrature Encoder (eQEP)
      1. 7.4.1 Clock Enable Control for eQEPx Modules
      2. 7.4.2 Using eQEPx Phase Error to Trip ePWMx Outputs
      3. 7.4.3 Input Connections to eQEPx Modules
      4. 7.4.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing
    5. 7.5  12-Bit Multibuffered Analog-to-Digital Converter (MibADC)
      1. 7.5.1 Features
      2. 7.5.2 Event Trigger Options
        1. 7.5.2.1 MibADC1 Event Trigger Hookup
        2. 7.5.2.2 MibADC2 Event Trigger Hookup
        3. 7.5.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules
      3. 7.5.3 ADC Electrical and Timing Specifications
      4. 7.5.4 Performance (Accuracy) Specifications
        1. 7.5.4.1 MibADC Nonlinearity Errors
        2. 7.5.4.2 MibADC Total Error
    6. 7.6  General-Purpose Input/Output
      1. 7.6.1 Features
    7. 7.7  Enhanced High-End Timer (N2HET)
      1. 7.7.1 Features
      2. 7.7.2 N2HET RAM Organization
      3. 7.7.3 Input Timing Specifications
      4. 7.7.4 N2HET1 to N2HET2 Synchronization
      5. 7.7.5 N2HET Checking
        1. 7.7.5.1 Internal Monitoring
        2. 7.7.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.7.6 Disabling N2HET Outputs
      7. 7.7.7 High-End Timer Transfer Unit (HET)
        1. 7.7.7.1 Features
        2. 7.7.7.2 Trigger Connections
    8. 7.8  Controller Area Network (DCAN)
      1. 7.8.1 Features
      2. 7.8.2 Electrical and Timing Specifications
    9. 7.9  Local Interconnect Network Interface (LIN)
      1. 7.9.1 LIN Features
    10. 7.10 Serial Communication Interface (SCI)
      1. 7.10.1 Features
    11. 7.11 Inter-Integrated Circuit (I2C) Module
      1. 7.11.1 Features
      2. 7.11.2 I2C I/O Timing Specifications
    12. 7.12 Multibuffered / Standard Serial Peripheral Interface
      1. 7.12.1 Features
      2. 7.12.2 MibSPI Transmit and Receive RAM Organization
      3. 7.12.3 MibSPI Transmit Trigger Events
        1. 7.12.3.1 MibSPI1 Event Trigger Hookup
        2. 7.12.3.2 MibSPI3 Event Trigger Hookup
        3. 7.12.3.3 MibSPI5 Event Trigger Hookup
      4. 7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.12.5 SPI Slave Mode I/O Timings
  8. 8 Applications, Implementation, and Layout
    1. 8.1 TI Designs or Reference Designs
  9. 9 Device and Documentation Support
    1. 9.1  Getting Started and Next Steps
    2. 9.2  Device and Development-Support Tool Nomenclature
    3. 9.3  Tools and Software
      1. 9.3.1 Kits and Evaluation Modules for Hercules TMS570 MCUs
      2. 9.3.2 Development Tools
      3. 9.3.3 Software
    4. 9.4  Documentation Support
    5. 9.5  Community Resources
    6. 9.6  Trademarks
    7. 9.7  Electrostatic Discharge Caution
    8. 9.8  Glossary
    9. 9.9  Device Identification
      1. 9.9.1 Device Identification Code Register
      2. 9.9.2 Die Identification Registers
    10. 9.10 Module Certifications
      1. 9.10.1 DCAN Certification
      2. 9.10.2 LIN Certification
        1. 9.10.2.1 LIN Master Mode
        2. 9.10.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 9.10.2.3 LIN Slave Mode - Adaptive Baud Rate
  10. 10Mechanical Packaging and Orderable Information
    1. 10.1 Packaging Information

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発注情報

7 Peripheral Information and Electrical Specifications

7.1 I/O Timings

7.1.1 Input Timings

TMS570LS0714 ttl_inputs_pns160.gif Figure 7-1 TTL-Level Inputs

Table 7-1 Timing Requirements for Inputs(1)

MIN MAX UNIT
tpw Input minimum pulse width tc(VCLK) + 10(2) ns
tin_slew Time for input signal to go from VIL to VIH or from VIH to VIL 1 ns
(1) tc(VCLK) = peripheral VBUS clock cycle time = 1 / f(VCLK)
(2) The timing shown above is only valid for pin used in general-purpose input mode.

7.1.2 Output Timings

Table 7-2 Switching Characteristics for Output Timings versus Load Capacitance (CL)

PARAMETER MIN MAX UNIT
Rise time, tr 8 mA low-EMI pins
(see Table 4-40)		 CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Fall time, tf CL = 15 pF 2.5
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Rise time, tr 4 mA low-EMI pins
(see Table 4-40)		 CL = 15 pF 5.6 ns
CL = 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
Fall time, tf CL = 15 pF 5.6
CL= 50 pF 10.4
CL = 100 pF 16.8
CL = 150 pF 23.2
Rise time, tr 2 mA-z low-EMI pins
(see Table 4-40)		 CL = 15 pF 8 ns
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Fall time, tf CL = 15 pF 8
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Rise time, tr Selectable 8 mA / 2 mA-z pins
(see Table 4-40)		 8mA mode CL = 15 pF 2.5 ns
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Fall time, tf CL = 15 pF 2.5
CL = 50 pF 4
CL = 100 pF 7.2
CL = 150 pF 12.5
Rise time, tr 2mA-z mode CL = 15 pF 8
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
Fall time, tf CL = 15 pF 8
CL = 50 pF 15
CL = 100 pF 23
CL = 150 pF 33
TMS570LS0714 cmos_outputs_pns160.gif Figure 7-2 CMOS-Level Outputs

Table 7-3 Timing Requirements for Outputs(1)

MIN MAX UNIT
td(parallel_out) Delay between low-to-high, or high-to-low transition of general-purpose output signals that can be configured by an application in parallel, for example, all signals in a GIOA port, or all N2HET1 signals, and so forth 6 ns
(1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check Table 4-40 for output buffer drive strength information on each signal.

7.1.2.1 Low-EMI Output Buffers

The low-EMI output buffer has been designed explicitly to address the issue of decoupling sources of emissions from the pins which they drive. This is accomplished by adaptively controlling the output buffer impedance, and is particularly effective with capacitive loads.

This is not the default mode of operation of the low-EMI output buffers and must be enabled by setting the system module GPCR1 register for the desired module or signal, as shown in Table 7-4. The adaptive impedance control circuit monitors the DC bias point of the output signal. The buffer internally generates two reference levels, VREFLOW and VREFHIGH, which are set to approximately 10% and 90% of VCCIO, respectively.

Once the output buffer has driven the output to a low level, if the output voltage is below VREFLOW, then the impedance of the output buffer will increase to Hi-Z. A high degree of decoupling between the internal ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing, for example, the buffer is driving low on a resistive path to ground. Current loads on the buffer which try to pull the output voltage above VREFLOW will be opposed by the impedance of the output buffer so as to maintain the output voltage at or below VREFLOW.

Conversely, once the output buffer has driven the output to a high level, if the output voltage is above VREFHIGH then the output buffer impedance will again increase to Hi-Z. A high degree of decoupling between internal power bus ad output pin will occur with capacitive loads or any loads in which no current is flowing, for example, buffer is driving high on a resistive path to VCCIO. Current loads on the buffer which try to pull the output voltage below VREFHIGH will be opposed by the output buffer impedance so as to maintain the output voltage at or above VREFHIGH.

The bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance control mode cannot respond to high-frequency noise coupling into the power buses of the buffer. In this manner, internal bus noise approaching 20% peak-to-peak of VCCIO can be rejected.

Unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will allow a positive current load to pull the output voltage up to VCCIO + 0.6V without opposition. Also, a negative current load will pull the output voltage down to VSSIO – 0.6V without opposition. This is not an issue because the actual clamp current capability is always greater than the IOH / IOL specifications.

The low-EMI output buffers are automatically configured to be in the standard buffer mode when the device enters a low-power mode.

Table 7-4 Low-EMI Output Buffer Hookup

MODULE or SIGNAL NAME LOW-EMI OUTPUT BUFFER SIGNAL HOOKUP
LOW-POWER MODE (LPM) STANDARD BUFFER ENABLE (SBEN)
Module: MibSPI1 LPM signal from SYS module GPREG1.0
Reserved GPREG1.1
Module: MibSPI3 GPREG1.2
Reserved GPREG1.3
Module: MibSPI5 GPREG1.4
Reserved GPREG1.5
Reserved GPREG1.6
Reserved GPREG1.7
Signal: TMS GPREG1.8
Reserved GPREG1.9
Signal: TDO GPREG1.10
Signal: RTCK GPREG1.11
Reserved GPREG1.12
Signal: nERROR GPREG1.13
Reserved GPREG1.14

7.2 Enhanced PWM Modules (ePWM)

Figure 7-3 shows the connections between the seven ePWM modules (ePWM1–ePWM7) on the device.

TMS570LS0714 eTPWMx_interconnections_spns225.gif
A. For more detail on the input synchronization selection of the TZ1/TZ2/TZ3n pins to each ePWMx module, see Figure 7-4.
Figure 7-3 ePWMx Module InterconnectionsA

Figure 7-4 shows the detailed input synchronization selection (asynchronous, double-synchronous, or double-synchronous + filter width) for ePWMx.

TMS570LS0714 input_sync_selection_epwmx_detailed_spns225.gif Figure 7-4 ePWMx Input Synchronization Selection Detail

7.2.1 ePWM Clocking and Reset

Each ePWM module has a clock enable (EPWMxENCLK). When SYS_nRST is active-low, the clock enables are ignored and the ePWM logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the state of clock enable is respected.

Table 7-5 ePWMx Clock Enable Control

ePWM MODULE INSTANCE CONTROL REGISTER TO
ENABLE CLOCK		 DEFAULT VALUE
ePWM1 PINMMR37[8] 1
ePWM2 PINMMR37[16] 1
ePWM3 PINMMR37[24] 1
ePWM4 PINMMR38[0] 1
ePWM5 PINMMR38[8] 1
ePWM6 PINMMR38[16] 1
ePWM7 PINMMR38[24] 1

The default value of the control registers to enable the clocks to the ePWMx modules is 1. This means that the VCLK4 clock connections to the ePWMx modules are enabled by default. The application can choose to gate off the VCLK4 clock to any ePWMx module individually by clearing the respective control register bit.

7.2.2 Synchronization of ePWMx Time-Base Counters

A time-base synchronization scheme connects all of the ePWM modules on a device. Each ePWM module has a synchronization input (EPWMxSYNCI) and a synchronization output (EPWMxSYNCO). The input synchronization for the first instance (ePWM1) comes from an external pin. Figure 7-3 shows the synchronization connections for all the ePWMx modules. Each ePWM module can be configured to use or ignore the synchronization input. For more information, see the ePWM chapter in the device-specific Technical Reference Manual (TRM).

7.2.3 Synchronizing all ePWM Modules to the N2HET1 Module Time Base

The connection between the N2HET1_LOOP_SYNC and SYNCI input of ePWM1 module is implemented as shown in Figure 7-5.

TMS570LS0714 sychonizing_tpwmx_n2het_spns225.gif Figure 7-5 Synchronizing Time Bases Between N2HET1, N2HET2 and ePWMx Modules

7.2.4 Phase-Locking the Time-Base Clocks of Multiple ePWM Modules

The TBCLKSYNC bit can be used to globally synchronize the time-base clocks of all enabled ePWM modules on a device. This bit is implemented as PINMMR37 register bit 1.

When TBCLKSYNC = 0, the time-base clock of all ePWM modules is stopped. This is the default condition.

When TBCLKSYNC = 1, all ePWM time-base clocks are started with the rising edge of TBCLK aligned.

For perfectly synchronized TBCLKs, the prescaler bits in the TBCTL register of each ePWM module must be set identically. The proper procedure for enabling the ePWM clocks is as follows:

  1. Enable the individual ePWM module clocks (if disable) using the control registers shown in Table 7-5.
  2. Configure TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module.
  3. Configure the prescaler values and desired ePWM modes.
  4. Configure TBCLKSYNC = 1.

7.2.5 ePWM Synchronization with External Devices

The output sync from the ePWM1 module is also exported to a device output terminal so that multiple devices can be synchronized together. The signal pulse is stretched by eight VCLK4 cycles before being exported on the terminal as the EPWM1SYNCO signal.

7.2.6 ePWM Trip Zones

7.2.6.1 Trip Zones TZ1n, TZ2n, TZ3n

These three trip zone inputs are driven by external circuits and are connected to device-level inputs. These signals are either connected asynchronously to the ePWMx trip zone inputs, or double-synchronized with VCLK4, or double-synchronized and then filtered with a 6-cycle VCLK4-based counter before connecting to the ePWMx (see Figure 7-4). By default, the trip zone inputs are asynchronously connected to the ePWMx modules.

Table 7-6 Connection to ePWMx Modules for Device-Level Trip Zone Inputs

TRIP ZONE
INPUT		 CONTROL FOR
ASYNCHRONOUS
CONNECTION TO ePWMx		 CONTROL FOR
DOUBLE-SYNCHRONIZED
CONNECTION TO ePWMx		 CONTROL FOR
DOUBLE-SYNCHRONIZED AND
FILTERED CONNECTION TO ePWMx(1)
TZ1n PINMMR46[18:16] = 001 PINMMR46[18:16] = 010 PINMMR46[18:16] = 100
TZ2n PINMMR46[26:24] = 001 PINMMR46[26:24] = 010 PINMMR46[26:24] = 100
TZ3n PINMMR47[2:0] = 001 PINMMR47[2:0] = 010 PINMMR47[2:0] = 100
(1) The filter width is 6 VCLK4 cycles.

7.2.6.2 Trip Zone TZ4n

This trip zone input is dedicated to eQEPx error indications. There are two eQEP modules on this device. Each eQEP module indicates a phase error by driving its EQEPxERR output High. The following control registers allow the application to configure the trip zone input (TZ4n) to each ePWMx module based on the requirements of the application.

Table 7-7 TZ4n Connections for ePWMx Modules

ePWMx CONTROL FOR TZ4n =
NOT(EQEP1ERR OR EQEP2ERR)		 CONTROL FOR TZ4n =
NOT(EQEP1ERR)		 CONTROL FOR TZ4n =
NOT(EQEP2ERR)
ePWM1 PINMMR41[2:0] = 001 PINMMR41[2:0] = 010 PINMMR41[2:0] = 100
ePWM2 PINMMR41[10:8] = 001 PINMMR41[10:8] = 010 PINMMR41[10:8] = 100
ePWM3 PINMMR41[18:16] = 001 PINMMR41[18:16] = 010 PINMMR41[18:16] = 100
ePWM4 PINMMR41[26:24] = 001 PINMMR41[26:24] = 010 PINMMR41[26:24] = 100
ePWM5 PINMMR42[2:0] = 001 PINMMR42[2:0] = 010 PINMMR42[2:0] = 100
ePWM6 PINMMR42[10:8] = 001 PINMMR42[10:8] = 010 PINMMR42[10:8] = 100
ePWM7 PINMMR42[18:16] = 001 PINMMR42[18:16] = 010 PINMMR42[18:16] = 100

7.2.6.3 Trip Zone TZ5n

This trip zone input is dedicated to a clock failure on the device. That is, this trip zone input is asserted whenever an oscillator failure or a PLL slip is detected on the device. The application can use this trip zone input for each ePWMx module to prevent the external system from going out of control when the device clocks are not within expected range (system running at limp clock).

The oscillator failure and PLL slip signals used for this trip zone input are taken from the status flags in the system module. These level signals are set until cleared by the application.

7.2.6.4 Trip Zone TZ6n

This trip zone input to the ePWMx modules is dedicated to a debug mode entry of the CPU. If enabled, the user can force the PWM outputs to a known state when the emulator stops the CPU. This prevents the external system from going out of control when the CPU is stopped.

7.2.7 Triggering of ADC Start of Conversion Using ePWMx SOCA and SOCB Outputs

A special scheme is implemented to select the actual signal used for triggering the start of conversion on the two ADCs on this device. This scheme is defined in Section 7.5.2.3.

7.2.8 Enhanced Translator-Pulse Width Modulator (ePWMx) Timings

Table 7-8 ePWMx Timing Requirements

TEST CONDITIONS MIN MAX UNIT
tw(SYNCIN) Synchronization input pulse width Asynchronous 2 tc(VCLK4) cycles
Synchronous 2 tc(VCLK4)
Synchronous, with input filter 2 tc(VCLK4) + filter width(1)
(1) The filter width is 6 VCLK4 cycles

Table 7-9 ePWMx Switching Characteristics

PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(PWM) Pulse duration, ePWMx output high or low 33.33 ns
tw(SYNCOUT) Synchronization Output Pulse Width 8 tc(VCLK4) cycles
td(PWM)tza Delay time, trip input active to PWM forced high, or
Delay time, trip input active to PWM forced low		 No pin load 25 ns
td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z 20 ns

Table 7-10 ePWMx Trip-Zone Timing Requirements

TEST CONDITIONS MIN MAX UNIT
tw(TZ) Pulse duration, TZn input low Asynchronous 2 * HSPCLKDIV * CLKDIV * tc(VCLK4)(1) cycles
Synchronous 2 tc(VCLK4)
Synchronous, with input filter 2 tc(VCLK4) + filter width
(1) For more information on the clock divider fields: HSPCLKDIV and CLKDIV, see the ePWM chapter of the device-specific Technical Reference Manual (TRM).

7.3 Enhanced Capture Modules (eCAP)

Figure 7-6 shows how the eCAP modules are interconnected on this microcontroller.

TMS570LS0714 eCAP_connections_spns225.gif
A. For more detail on the input synchronization selection of the ECAPx pins to each eCAPx module, see Figure 7-7.
Figure 7-6 eCAPx Module Connections

Figure 7-7 shows the detailed input synchronization selection (asynchronous, double-synchronous, or double-synchronous + filter width) for eCAPx.

TMS570LS0714 input_sync_selection_ecapx_detailed_spns225.gif Figure 7-7 eCAPx Input Synchronization Selection Detail

7.3.1 Clock Enable Control for eCAPx Modules

Each of the eCAPx modules have a clock enable (ECAPxENCLK). These signals must be generated from a device-level control register. When SYS_nRST is active-low, the clock enables are ignored and the ECAPx logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the state of clock enable is respected.

Table 7-11 eCAPx Clock Enable Control

eCAP MODULE INSTANCE CONTROL REGISTER TO
ENABLE CLOCK		 DEFAULT VALUE
eCAP1 PINMMR39[0] 1
eCAP2 PINMMR39[8] 1
eCAP3 PINMMR39[16] 1
eCAP4 PINMMR39[24] 1
eCAP5 PINMMR40[0] 1
eCAP6 PINMMR40[8] 1

The default value of the control registers to enable the clocks to the eCAPx modules is 1. This means that the VCLK4 clock connections to the eCAPx modules are enabled by default. The application can choose to gate off the VCLK4 clock to any eCAPx module individually by clearing the respective control register bit.

7.3.2 PWM Output Capability of eCAPx

When not used in capture mode, each of the eCAPx modules can be used as a single-channel PWM output. This is called the Auxiliary PWM (APWM) mode of operation of the eCAPx modules. For more information, see the eCAP module chapter of the device-specific TRM.

7.3.3 Input Connection to eCAPx Modules

The input connection to each of the eCAPx modules can be selected between a double-VCLK4-synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-12.

Table 7-12 Device-Level Input Connection to eCAPx Modules

INPUT SIGNAL CONTROL FOR
DOUBLE-SYNCHRONIZED
CONNECTION TO eCAPx		 CONTROL FOR
DOUBLE-SYNCHRONIZED AND
FILTERED CONNECTION TO eCAPx(1)
eCAP1 PINMMR43[2:0] = 001 PINMMR43[2:0] = 010
eCAP2 PINMMR43[10:8] = 001 PINMMR43[10:8] = 010
eCAP3 PINMMR43[18:16] = 001 PINMMR43[18:16] = 010
eCAP4 PINMMR43[26:24] = 001 PINMMR43[26:24] = 010
eCAP5 PINMMR44[2:0] = 001 PINMMR44[2:0] = 010
eCAP6 PINMMR44[10:8] = 001 PINMMR44[10:8] = 010
(1) The filter width is 6 VCLK4 cycles.

7.3.4 Enhanced Capture Module (eCAP) Electrical Data/Timing

Table 7-13 eCAPx Timing Requirements

TEST CONDITIONS MIN MAX UNIT
tw(CAP) Pulse width, capture input Synchronous 2 tc(VCLK4) cycles
Synchronous with input filter 2 tc(VCLK4) + filter width(1)
(1) The filter width is 6 VCLK4 cycles.

Table 7-14 eCAPx Switching Characteristics

PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(APWM) Pulse duration, APWMx output high or low 20 ns

7.4 Enhanced Quadrature Encoder (eQEP)

Figure 7-8 shows the eQEP module interconnections on the device.

TMS570LS0714 eQEP_connections_spns225.gif
A. For more detail on the eQEP input synchronization selection of the EQEPxA/B pins to each eQEPx module, see Figure 7-9.
Figure 7-8 eQEP Module Interconnections

Figure 7-9 shows the detailed input synchronization selection (asynchronous, double-synchronous, or double-synchronous + filter width) for eQEPx.

TMS570LS0714 input_sync_selection_eqepx_detailed_spns225.gif Figure 7-9 eQEPx Input Synchronization Selection Detail

7.4.1 Clock Enable Control for eQEPx Modules

Device-level control registers are implemented to generate the EQEPxENCLK signals. When SYS_nRST is active-low, the clock enables are ignored and the eQEPx logic is clocked so that it can reset to a proper state. When SYS_nRST goes in-active high, the state of clock enable is respected.

The default value of the control registers to enable the clocks to the eQEPx modules is 1 (see Table 7-15). This means that the VCLK4 clock connections to the eQEPx modules are enabled by default. The application can choose to gate off the VCLK4 clock to any eQEPx module individually by clearing the respective control register bit.

Table 7-15 eQEPx Clock Enable Control

eQEP MODULE INSTANCE CONTROL REGISTER TO
ENABLE CLOCK		 DEFAULT VALUE
eQEP1 PINMMR40[16] 1
eQEP2 PINMMR40[24] 1

7.4.2 Using eQEPx Phase Error to Trip ePWMx Outputs

The eQEP module sets the EQEPERR signal output whenever a phase error is detected in its inputs EQEPxA and EQEPxB. This error signal from both the eQEP modules is input to the connection selection multiplexer. This multiplexer is defined in Table 7-7. As shown in Figure 7-3, the output of this selection multiplexer is inverted and connected to the TZ4n trip-zone input of all EPWMx modules. This connection allows the application to define the response of each ePWMx module on a phase error indicated by the eQEP modules.

7.4.3 Input Connections to eQEPx Modules

The input connections to each of the eQEP modules can be selected between a double-VCLK4-synchronized input or a double-VCLK4-synchronized and filtered input, as shown in Table 7-16.

Table 7-16 Device-Level Input Connection to eQEPx Modules

INPUT SIGNAL CONTROL FOR
DOUBLE-SYNCHRONIZED
CONNECTION TO eQEPx		 CONTROL FOR
DOUBLE-SYNCHRONIZED AND
FILTERED CONNECTION TO eQEPx(1)
eQEP1A PINMMR44[18:16] = 001 PINMMR44[18:16] = 010
eQEP1B PINMMR44[26:24] = 001 PINMMR44[26:24] = 010
eQEP1I PINMMR45[2:0] = 001 PINMMR45[2:0] = 010
eQEP1S PINMMR45[10:8] = 001 PINMMR45[10:8] = 010
eQEP2A PINMMR45[18:16] = 001 PINMMR45[18:16] = 010
eQEP2B PINMMR45[26:24] = 001 PINMMR45[26:24] = 010
eQEP2I PINMMR46[2:0] = 001 PINMMR46[2:0] = 010
eQEP2S PINMMR46[10:8] = 001 PINMMR46[10:8] = 010
(1) The filter width is 6 VCLK4 cycles.

7.4.4 Enhanced Quadrature Encoder Pulse (eQEPx) Timing

Table 7-17 eQEPx Timing Requirements(1)

TEST CONDITIONS MIN MAX UNIT
tw(QEPP) QEP input period Synchronous 2 tc(VCLK4) cycles
Synchronous with input filter 2 tc(VCLK4) + filter width
tw(INDEXH) QEP Index Input High Time Synchronous 2 tc(VCLK4) cycles
Synchronous with input filter 2 tc(VCLK4) + filter width
tw(INDEXL) QEP Index Input Low Time Synchronous 2 tc(VCLK4) cycles
Synchronous with input filter 2 tc(VCLK4) + filter width
tw(STROBH) QEP Strobe Input High Time Synchronous 2 tc(VCLK4) cycles
Synchronous with input filter 2 tc(VCLK4) + filter width
tw(STROBL) QEP Strobe Input Low Time Synchronous 2 tc(VCLK4) cycles
Synchronous with input filter 2 tc(VCLK4) + filter width
(1) The filter width is 6 VCLK4 cycles.

Table 7-18 eQEPx Switching Characteristics

PARAMETER MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 4 tc(VCLK4) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6 tc(VCLK4) cycles

7.5 12-Bit Multibuffered Analog-to-Digital Converter (MibADC)

The MibADC has a separate power bus for its analog circuitry that enhances the Analog-to-Digital (A-to-D) performance by preventing digital switching noise on the logic circuitry which could be present on VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to ADREFLO, unless otherwise noted.

Table 7-19 MibADC Overview

DESCRIPTION VALUE
Resolution 12 bits
Monotonic Assured
Output conversion code 00h to 3FFh [00 for VAI ≤ ADREFLO; 3FFh for VAI ≥ ADREFHI]

7.5.1 Features

  • 12-bit resolution
  • ADREFHI and ADREFLO pins (high and low reference voltages)
  • Total Sample/Hold/Convert time: 600 ns Minimum at 30 MHz ADCLK
  • One memory region per conversion group is available (Event Group, Group 1, and Group 2)
  • Allocation of channels to conversion groups is completely programmable
  • Supports flexible channel conversion order
  • Memory regions are serviced either by interrupt or by DMA
  • Programmable interrupt threshold counter is available for each group
  • Programmable magnitude threshold interrupt for each group for any one channel
  • Option to read either 8-, 10-, or 12-bit values from memory regions
  • Single or continuous conversion modes
  • Embedded self-test
  • Embedded calibration logic
  • Enhanced power-down mode
    • Optional feature to automatically power down ADC core when no conversion is in progress
  • External event pin (ADxEVT) programmable as general-purpose I/O

7.5.2 Event Trigger Options

The ADC module supports three conversion groups: Event Group, Group1, and Group2. Each of these three groups can be configured to be triggered by a hardware event. In that case, the application can select the trigger, from among eight event sources, to convert a group.

7.5.2.1 MibADC1 Event Trigger Hookup

Table 7-20 lists the event sources that can trigger the conversions for the MibADC1 groups.

Table 7-20 MibADC1 Event Trigger Hookup

GROUP SOURCE SELECT
(G1SRC, G2SRC, OR EVSRC)		 EVENT NO. TRIGGER EVENT SIGNAL
PINMMR30[0] = 1
(DEFAULT)		 PINMMR30[0] = 0 AND PINMMR30[1] = 1
OPTION A CONTROL FOR
OPTION A		 OPTION B CONTROL FOR
OPTION B
000 1 AD1EVT AD1EVT — AD1EVT —
001 2 N2HET1[8] N2HET2[5] PINMMR30[8] = 1 ePWM_B PINMMR30[8] = 0 and
PINMMR30[9] = 1
010 3 N2HET1[10] N2HET1[27] — N2HET1[27] —
011 4 RTI Compare 0 Interrupt RTI Compare 0 Interrupt PINMMR30[16] = 1 ePWM_A1 PINMMR30[16] = 0 and
PINMMR30[17] = 1
100 5 N2HET1[12] N2HET1[17] — N2HET1[17] —
101 6 N2HET1[14] N2HET1[19] PINMMR30[24] = 1 N2HET2[1] PINMMR30[24] = 0 and
PINMMR30[25] = 1
110 7 GIOB[0] N2HET1[11] PINMMR31[0] = 1 ePWM_A2 PINMMR31[0] = 0 and
PINMMR31[1] = 1
111 8 GIOB[1] N2HET2[13] PINMMR32[16] = 1 ePWM_AB PINMMR31[8] = 0 and
PINMMR31[9] = 1

NOTE

If ADEVT, N2HET1, or GIOB is used as a trigger source, the connection to the MibADC1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (through the mux control), or by driving the function from an external trigger source as input. If the mux control module is used to select different functionality instead of the ADEVT, N2HET1[x] or GIOB[x] signals, then care must be taken to disable these signals from triggering conversions; there is no multiplexing on the input connections.

If ePWM_B, ePWM_A2, ePWM_AB, N2HET2[1], N2HET2[5], N2HET2[13], N2HET1[11], N2HET1[17], or N2HET1[19] is used to trigger the ADC, the connection to the ADC is made directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered without having to enable the signal from being output on a device terminal.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU.

7.5.2.2 MibADC2 Event Trigger Hookup

Table 7-21 lists the event sources that can trigger the conversions for the MibADC2 groups.

Table 7-21 MibADC2 Event Trigger Hookup

GROUP SOURCE SELECT
(G1SRC, G2SRC, OR EVSRC)		 EVENT NO. TRIGGER EVENT SIGNAL
PINMMR30[0] = 1
(DEFAULT)		 PINMMR30[0] = 0 and PINMMR30[1] = 1
OPTION A CONTROL FOR
OPTION A		 OPTION B CONTROL FOR
OPTION B
000 1 AD2EVT AD2EVT — AD2EVT —
001 2 N2HET1[8] N2HET2[5] PINMMR31[16] = 1 ePWM_B PINMMR31[16] = 0 and
PINMMR31[17] = 1
010 3 N2HET1[10] N2HET1[27] — N2HET1[27] —
011 4 RTI Compare 0 Interrupt RTI Compare 0 Interrupt PINMMR31[24] = 1 ePWM_A1 PINMMR31[24] = 0 and
PINMMR31[25] = 1
100 5 N2HET1[12] N2HET1[17] — N2HET1[17] —
101 6 N2HET1[14] N2HET1[19] PINMMR32[0] = 1 N2HET2[1] PINMMR32[0] = 0 and
PINMMR32[1] = 1
110 7 GIOB[0] N2HET1[11] PINMMR32[8] = 1 ePWM_A2 PINMMR32[8] = 0 and
PINMMR32[9] = 1
111 8 GIOB[1] N2HET2[13] PINMMR32[16] = 1 ePWM_AB PINMMR32[16] = 0 and
PINMMR32[17] = 1

NOTES

If AD2EVT, N2HET1, or GIOB is used as a trigger source, the connection to the MibADC2 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by configuring the function as output onto the pad (through the mux control), or by driving the function from an external trigger source as input. If the mux control module is used to select different functionality instead of the AD2EVT, N2HET1[x] or GIOB[x] signals, then care must be taken to disable these signals from triggering conversions; there is no multiplexing on the input connections.

If ePWM_B, ePWM_A2, ePWM_AB, N2HET2[1], N2HET2[5], N2HET2[13], N2HET1[11], N2HET1[17], or N2HET1[19] is used to trigger the ADC, the connection to the ADC is made directly from the N2HET or ePWM module outputs. As a result, the ADC can be triggered without having to enable the signal from being output on a device terminal.

NOTE

For the RTI compare 0 interrupt source, the connection is made directly from the output of the RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU.

7.5.2.3 Controlling ADC1 and ADC2 Event Trigger Options Using SOC Output from ePWM Modules

As shown in Figure 7-10, the ePWMxSOCA and ePWMxSOCB outputs from each ePWM module are used to generate four signals – ePWM_B, ePWM_A1, ePWM_A2, and ePWM_AB, that are available to trigger the ADC based on the application requirement.

TMS570LS0714 ADC_trigger_from_eTPWM_spns225.gif Figure 7-10 ADC Trigger Source Generation from ePWMx

Table 7-22 Control Bit to SOC Output

CONTROL BIT SOC OUTPUT
PINMMR35[0] SOC1A_SEL
PINMMR35[8] SOC2A_SEL
PINMMR35[16] SOC3A_SEL
PINMMR35[24] SOC4A_SEL
PINMMR36[0] SOC5A_SEL
PINMMR36[8] SOC6A_SEL
PINMMR36[16] SOC7A_SEL

The SOCA output from each ePWM module is connected to a "switch" shown in Figure 7-10. This switch is implemented by using the control registers in the PINMMR module. Figure 7-11 shows an example of the implementation for the switch on SOC1A. The switches on the other SOCA signals are implemented in the same way.

TMS570LS0714 ePWM1SOCA_switch_spns195.gif Figure 7-11 ePWM1SOC1A Switch Implementation

The logic equations (Equation 1, Equation 2, Equation 3, and Equation 4) for the four outputs from the combinational logic shown in Figure 7-10 are:

ePWM_B = SOC1B or SOC2B or SOC3B or SOC4B or SOC5B or SOC6B or SOC7B (1)
ePWM_A1 = [ SOC1A and not(SOC1A_SEL) ] or [ SOC2A and not(SOC2A_SEL) ] or [ SOC3A and not(SOC3A_SEL) ] or
[ SOC4A and not(SOC4A_SEL) ] or [ SOC5A and not(SOC5A_SEL) ] or [ SOC6A and not(SOC6A_SEL) ] or
[ SOC7A and not(SOC7A_SEL) ] (2)
ePWM_A2 = [ SOC1A and SOC1A_SEL ] or [ SOC2A and SOC2A_SEL ] or [ SOC3A and SOC3A_SEL ] or
[ SOC4A and SOC4A_SEL ] or [ SOC5A and SOC5A_SEL ] or [ SOC6A and SOC6A_SEL ] or
[ SOC7A and SOC7A_SEL ] (3)
ePWM_AB = ePWM_B or ePWM_A2 (4)

7.5.3 ADC Electrical and Timing Specifications

Table 7-23 MibADC Recommended Operating Conditions

PARAMETER MIN MAX UNIT
ADREFHI A-to-D high-voltage reference source ADREFLO VCCAD(1) V
ADREFLO A-to-D low-voltage reference source VSSAD(1) ADREFHI V
VAI Analog input voltage ADREFLO ADREFHI V
IAIC Analog input clamp current(2) (VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3) –2 2 mA
(1) For VCCAD and VSSAD recommended operating conditions, see Section 5.4.
(2) Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.

Table 7-24 MibADC Electrical Characteristics Over Full Ranges of Recommended Operating Conditions

PARAMETER DESCRIPTION/CONDITIONS MIN MAX UNIT
Rmux Analog input mux on-resistance See Figure 7-12 250 Ω
Rsamp ADC sample switch on-resistance See Figure 7-12 250 Ω
Cmux Input mux capacitance See Figure 7-12 16 pF
Csamp ADC sample capacitance See Figure 7-12 13 pF
IAIL Analog off-state input leakage current VCCAD = 3.6 V maximum VSSAD ≤ VIN < VSSAD + 100 mV –300 200 nA
VSSAD + 100 mV ≤ VIN ≤ VCCAD – 200 mV –200 200
VCCAD – 200 mV < VIN ≤ VCCAD –200 500
IAIL Analog off-state input leakage current VCCAD = 5.25 V maximum VSSAD ≤ VIN < VSSAD + 300 mV –1000 250 nA
VSSAD + 300 mV ≤ VIN ≤ VCCAD – 300 mV –250 250
VCCAD – 300 mV < VIN ≤ VCCAD –250 1000
IAOSB1(1) ADC1 Analog on-state input bias current VCCAD = 3.6 V maximum VSSAD ≤ VIN < VSSAD + 100 mV –8 2 µA
VSSAD + 100 mV < VIN < VCCAD – 200 mV –4 2
VCCAD – 200 mV < VIN < VCCAD –4 12
IAOSB2(1) ADC2 Analog on-state input bias current VCCAD = 3.6 V maximum VSSAD ≤ VIN < VSSAD + 100 mV –7 2 µA
VSSAD + 100 mV ≤ VIN ≤ VCCAD – 200 mV –4 2
VCCAD - 200 mV < VIN ≤ VCCAD –4 10
IAOSB1(1) ADC1 Analog on-state input bias current VCCAD = 5.25 V maximum VSSAD ≤ VIN < VSSAD + 300 mV –10 3 µA
VSSAD + 300 mV ≤ VIN ≤ VCCAD – 300 mV –5 3
VCCAD – 300 mV < VIN ≤ VCCAD –5 14
IAOSB2(1) ADC2 Analog on-state input bias current VCCAD = 5.25 V maximum VSSAD ≤ VIN < VSSAD + 300 mV –8 3 µA
VSSAD + 300 mV ≤ VIN ≤ VCCAD – 300 mV –5 3
VCCAD – 300 mV < VIN ≤ VCCAD –5 12
IADREFHI ADREFHI input current ADREFHI = VCCAD, ADREFLO = VSSAD 3 mA
ICCAD Static supply current Normal operating mode 15 mA
ADC core in power down mode 5 µA
(1) If a shared channel is being converted by both ADC converters at the same time, the on-state leakage is equal to IAOSB1 + IAOSB2.
TMS570LS0714 mibadc_circuit_pns160.gif Figure 7-12 MibADC Input Equivalent Circuit

Table 7-25 MibADC Timing Specifications

PARAMETER MIN NOM MAX UNIT
tc(ADCLK)(2) Cycle time, MibADC clock 0.033 µs
td(SH)(3) Delay time, sample and hold time 0.2 µs
td(PU-ADV) Delay time from ADC power on until first input can be sampled 1 µs
12-BIT MODE
td(C) Delay time, conversion time 0.4 µs
td(SHC)(1) Delay time, total sample/hold and conversion time 0.6 µs
10-BIT MODE
td(C) Delay time, conversion time 0.33 µs
td(SHC)(1) Delay time, total sample/hold and conversion time 0.53 µs
(1) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors (for example, the prescale settings).
(2) The MibADC clock is the ADCLK, generated by dividing down the VCLK by a prescale factor defined by the ADCLOCKCR register bits 4:0.
(3) The sample and hold time for the ADC conversions is defined by the ADCLK frequency and the AD<GP>SAMP register for each conversion group. The sample time must be determined by accounting for the external impedance connected to the input channel as well as the internal impedance of the ADC.

Table 7-26 MibADC Operating Characteristics Over Full Ranges of Recommended Operating Conditions(1)(2)

PARAMETER DESCRIPTION/CONDITIONS MIN NOM MAX UNIT
CR Conversion range over which specified accuracy is maintained ADREFHI – ADREFLO 3 5.25 V
ZSET Zero Scale Offset Difference between the first ideal transition (from code 000h to 001h) and the actual transition 10-bit mode 1 LSB
12-bit mode 2
FSET Full Scale Offset Difference between the range of the measured code transitions (from first to last) and the range of the ideal code transitions 10-bit mode 2 LSB
12-bit mode 3
EDNL Differential nonlinearity error Difference between the actual step width and the ideal value (see Figure 7-13). 10-bit mode ± 1.5 LSB
12-bit mode ± 2
EINL Integral nonlinearity error Maximum deviation from the best straight line through the MibADC. MibADC transfer characteristics, excluding the quantization error. 10-bit mode ± 2 LSB
12-bit mode ± 2
ETOT Total unadjusted error Maximum value of the difference between an analog value and the ideal midstep value. 10-bit mode ± 2 LSB
12-bit mode ± 4
(1) 1 LSB = (ADREFHI – ADREFLO)/ 212 for 12-bit mode
(2) 1 LSB = (ADREFHI – ADREFLO)/ 210 for 10-bit mode

7.5.4 Performance (Accuracy) Specifications

7.5.4.1 MibADC Nonlinearity Errors

The differential nonlinearity error shown in Figure 7-13 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 LSB.

TMS570LS0714 dnl_error_pns160.gif
A. 1 LSB = (ADREFHI – ADREFLO)/212
Figure 7-13 Differential Nonlinearity (DNL) Error(A)

The integral nonlinearity error shown in Figure 7-14 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line.

TMS570LS0714 inl_error_pns160.gif
A. 1 LSB = (ADREFHI – ADREFLO)/212
Figure 7-14 Integral Nonlinearity (INL) Error(A)

7.5.4.2 MibADC Total Error

The absolute accuracy or total error of an MibADC as shown in Figure 7-15 is the maximum value of the difference between an analog value and the ideal midstep value.

TMS570LS0714 total_error_pns160.gif
A. 1 LSB = (ADREFHI – ADREFLO)/212
Figure 7-15 Absolute Accuracy (Total) Error(A)

7.6 General-Purpose Input/Output

The GPIO module on this device supports two ports, GIOA and GIOB. The I/O pins are bidirectional and bit-programmable. Both GIOA and GIOB support external interrupt capability.

7.6.1 Features

The GPIO module has the following features:

  • Each I/O pin can be configured as:
    • Input
    • Output
    • Open drain
  • The interrupts have the following characteristics:
    • Programmable interrupt detection either on both edges or on a single edge (set in GIOINTDET)
    • Programmable edge-detection polarity, either rising or falling edge (set in GIOPOL register)
    • Individual interrupt flags (set in GIOFLG register)
    • Individual interrupt enables, set and cleared through GIOENASET and GIOENACLR registers, respectively
    • Programmable interrupt priority, set through GIOLVLSET and GIOLVLCLR registers
  • Internal pullup/pulldown allows unused I/O pins to be left unconnected

For information on input and output timings see Section 7.1.1 and Section 7.1.2.

7.7 Enhanced High-End Timer (N2HET)

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose I/O. The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses.

7.7.1 Features

The N2HET module has the following features:

  • Programmable timer for input and output timing functions
  • Reduced instruction set (30 instructions) for dedicated time and angle functions
  • 160 words of instruction RAM protected by parity
  • User-defined number of 25-bit virtual counters for timer, event counters, and angle counters
  • 7-bit hardware counters for each pin allow up to 32-bit resolution in conjunction with the 25-bit virtual counters
  • Up to 32 pins usable for input signal measurements or output signal generation
  • Programmable suppression filter for each input pin with adjustable limiting frequency
  • Low CPU overhead and interrupt load
  • Efficient data transfer to or from the CPU memory with dedicated High-End-Timer Transfer Unit (HTU) or DMA
  • Diagnostic capabilities with different loopback mechanisms and pin status readback functionality

7.7.2 N2HET RAM Organization

The timer RAM uses four RAM banks, where each bank has two port access capability. This means that one RAM address may be written while another address is read. The RAM words are 96 bits wide, which are split into three 32-bit fields (program, control, and data).

7.7.3 Input Timing Specifications

The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals.

TMS570LS0714 nhet_input_timings_pns160.gif Figure 7-16 N2HET Input Capture Timings

Table 7-27 Dynamic Characteristics for the N2HET Input Capture Functionality

PARAMETER MIN MAX UNIT
1 Input signal period, PCNT or WCAP for rising edge to rising edge (HRP) (LRP) tc(VCLK2) + 2 225 (HRP) (LRP) tc(VCLK2) – 2 ns
2 Input signal period, PCNT or WCAP for falling edge to falling edge (HRP) (LRP) tc(VCLK2) + 2 225 (HRP) (LRP) tc(VCLK2) – 2 ns
3 Input signal high phase, PCNT or WCAP for rising edge to falling edge 2 (HRP) tc(VCLK2) + 2 225 (HRP) (LRP) tc(VCLK2) – 2 ns
4 Input signal low phase, PCNT or WCAP for falling edge to rising edge 2 (HRP) tc(VCLK2) + 2 225 (HRP) (LRP) tc(VCLK2) – 2 ns

7.7.4 N2HET1 to N2HET2 Synchronization

In some applications the N2HET resolutions must be synchronized. Some other applications require a single time base to be used for all PWM outputs and input timing captures.

The N2HET provides such a synchronization mechanism. The Clk_master/slave (HETGCR.16) configures the N2HET in master or slave mode (default is slave mode). An N2HET in master mode provides a signal to synchronize the prescalers of the slave N2HET. The slave N2HET synchronizes its loop resolution to the loop resolution signal sent by the master. The slave does not require this signal after it receives the first synchronization signal. However, anytime the slave receives the resynchronization signal from the master, the slave must synchronize itself again.

TMS570LS0714 nhet_interconnect_pns160.gif Figure 7-17 N2HET1 to N2HET2 Synchronization Hookup

7.7.5 N2HET Checking

7.7.5.1 Internal Monitoring

To assure correctness of the high-end timer operation and output signals, the two N2HET modules can be used to monitor each other’s signals, as shown in Figure 7-18. The direction of the monitoring is controlled by the I/O multiplexing control module.

TMS570LS0714 nhet_monitoring_pns160.gif Figure 7-18 N2HET Monitoring

7.7.5.2 Output Monitoring Using Dual Clock Comparator (DCC)

N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure the frequency of the PWM signal on N2HET1[31].

Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to measure the frequency of the PWM signal on N2HET2[0].

Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection to the DCC module is made directly from the output of the N2HETx module (from the input of the output buffer).

For more information on DCC, see Section 6.7.3.

7.7.6 Disabling N2HET Outputs

Some applications require disabling the N2HET outputs under some fault condition. The N2HET module provides this capability through the Pin Disable input signal. This signal, when driven low, causes the N2HET outputs identified by a programmable register (HETPINDIS) to be in a high-impedance (tri-state) state. For more details on the N2HET Pin Disable feature, see the device-specific Terminal Reference Manual.

GIOA[5] is connected to the Pin Disable input for N2HET1, and GIOB[2] is connected to the Pin Disable input for N2HET2.

7.7.7 High-End Timer Transfer Unit (HET)

A High-End Timer Transfer Unit (HTU) can perform DMA type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HET TU.

7.7.7.1 Features

  • CPU and DMA independent
  • Master port to access system memory
  • 8 control packets supporting dual buffer configuration
  • Control packet information is stored in RAM protected by parity
  • Event synchronization (HET transfer requests)
  • Supports 32- or 64-bit transactions
  • Addressing modes for HET address (8- or 16-byte) and system memory address (fixed, 32- or 64-bit)
  • One shot, circular, and auto-switch buffer transfer modes
  • Request lost detection

7.7.7.2 Trigger Connections

For the transfer request line trigger connections to the N2HET TU when an instruction-specific condition is true, see Table 7-28 and Table 7-29.

Table 7-28 HET TU1 Request Line Connection

MODULES REQUEST SOURCE HET TU1 REQUEST
N2HET1 HTUREQ[0] HET TU1 DCP[0]
N2HET1 HTUREQ[1] HET TU1 DCP[1]
N2HET1 HTUREQ[2] HET TU1 DCP[2]
N2HET1 HTUREQ[3] HET TU1 DCP[3]
N2HET1 HTUREQ[4] HET TU1 DCP[4]
N2HET1 HTUREQ[5] HET TU1 DCP[5]
N2HET1 HTUREQ[6] HET TU1 DCP[6]
N2HET1 HTUREQ[7] HET TU1 DCP[7]

Table 7-29 HET TU2 Request Line Connection

MODULES REQUEST SOURCE HET TU2 REQUEST
N2HET2 HTUREQ[0] HET TU2 DCP[0]
N2HET2 HTUREQ[1] HET TU2 DCP[1]
N2HET2 HTUREQ[2] HET TU2 DCP[2]
N2HET2 HTUREQ[3] HET TU2 DCP[3]
N2HET2 HTUREQ[4] HET TU2 DCP[4]
N2HET2 HTUREQ[5] HET TU2 DCP[5]
N2HET2 HTUREQ[6] HET TU2 DCP[6]
N2HET2 HTUREQ[7] HET TU2 DCP[7]

7.8 Controller Area Network (DCAN)

The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring.

7.8.1 Features

Features of the DCAN module include:

  • Supports CAN protocol version 2.0 part A, B
  • Bit rates up to 1 Mbps
  • The CAN kernel can be clocked by the oscillator for baud-rate generation.
  • 64 mailboxes on each DCAN
  • Individual identifier mask for each message object
  • Programmable FIFO mode for message objects
  • Programmable loop-back modes for self-test operation
  • Automatic bus on after Bus-Off state by a programmable 32-bit timer
  • Message RAM protected by parity
  • Direct access to message RAM during test mode
  • CAN RX and TX pins configurable as general-purpose I/O pins
  • Message RAM Auto Initialization
  • DMA support

For more information on the DCAN, see the device-specific TRM.

7.8.2 Electrical and Timing Specifications

Table 7-30 Dynamic Characteristics for the DCANx TX and RX Pins

PARAMETER MIN MAX UNIT
td(CANnTX) Delay time, transmit shift register to CANnTX pin(1) 15 ns
td(CANnRX) Delay time, CANnRX pin to receive shift register 5 ns
(1) These values do not include the rise and fall times of the output buffer.

7.9 Local Interconnect Network Interface (LIN)

The SCI/LIN module can be programmed to work either as an SCI or as a LIN. The core of the module is an SCI. The hardware features of the SCI are augmented to achieve LIN compatibility.

The SCI module is a universal asynchronous receiver-transmitter that implements the standard nonreturn to zero (NRZ) format. The SCI can be used to communicate, for example, through an RS-232 port or over a K-line.

The LIN standard is based on the SCI (Universal Asynchronous Receiver/Transmitter [UART]) serial data link format. The communication concept is single-master/multiple-slave with a message identification for multicast transmission between any network nodes.

7.9.1 LIN Features

The following are features of the LIN module:

  • Compatible to LIN 1.3, 2.0 and 2.1 protocols
  • Multibuffered receive and transmit units DMA capability for minimal CPU intervention
  • Identification masks for message filtering
  • Automatic Master Header Generation
    • Programmable Synch Break Field
    • Synch Field
    • Identifier Field
  • Slave Automatic Synchronization
    • Synch break detection
    • Optional baudrate update
    • Synchronization Validation
  • 231 programmable transmission rates with 7 fractional bits
  • Error detection
  • 2 interrupt lines with priority encoding

7.10 Serial Communication Interface (SCI)

7.10.1 Features

  • Standard UART communication
  • Supports full- or half-duplex operation
  • Standard NRZ format
  • Double-buffered receive and transmit functions
  • Configurable frame format of 3 to 13 bits per character based on the following:
    • Data word length programmable from 1 to 8 bits
    • Additional address bit in address-bit mode
    • Parity programmable for 0 or 1 parity bit, odd or even parity
    • Stop programmable for 1 or 2 stop bits
  • Asynchronous or isosynchronous communication modes
  • Two multiprocessor communication formats allow communication between more than two devices.
  • Sleep mode is available to free CPU resources during multiprocessor communication.
  • The 24-bit programmable baud rate supports 224 different baud rates provide high-accuracy baud rate selection.
  • Four error flags and five status flags provide detailed information regarding SCI events.
  • Capability to use DMA for transmit and receive data.

7.11 Inter-Integrated Circuit (I2C) Module

The I2C module is a multimaster communication module providing an interface between the microcontroller and devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by an I2C-bus. This module will support any slave or master I2C compatible device.

7.11.1 Features

The I2C module has the following features:

  • Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number 9398 393 40011)
    • Bit or Byte format transfer
    • 7- and 10-bit device addressing modes
    • General call
    • START byte
    • Multimaster transmitter or slave receiver mode
    • Multimaster receiver or slave transmitter mode
    • Combined master transmit or receive and receive or transmit mode
    • Transfer rates of 10 kbps up to 400 kbps (Phillips fast-mode rate)
  • Free data format
  • Two DMA events (transmit and receive)
  • DMA event enable or disable capability
  • Seven interrupts that can be used by the CPU
  • Module enable or disable capability
  • The SDA and SCL are optionally configurable as general-purpose I/O
  • Slew rate control of the outputs
  • Open-drain control of the outputs
  • Programmable pullup or pulldown capability on the inputs
  • Supports Ignore NACK mode

NOTE

This I2C module does not support:

  • High-speed (HS) mode
  • C-bus compatibility mode
  • The combined format in 10-bit address mode (the I2C module sends the slave address second byte every time it sends the slave address first byte)

7.11.2 I2C I/O Timing Specifications

Table 7-31 I2C Signals (SDA and SCL) Switching Characteristics(1)

PARAMETER STANDARD MODE FAST MODE UNIT
MIN MAX MIN MAX
tc(I2CCLK) Cycle time, internal module clock for I2C, prescaled from VCLK 75.2 149 75.2 149 ns
f(SCL) SCL clock frequency 0 100 0 400 kHz
tc(SCL) Cycle time, SCL 10 2.5 µs
tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.6 µs
th(SCLL-SDAL) Hold time, SCL low after SDA low (for a repeated START condition) 4 0.6 µs
tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
tw(SCLH) Pulse duration, SCL high 4 0.6 µs
tsu(SDA-SCLH) Setup time, SDA valid before SCL high 250 100 ns
th(SDA-SCLL) Hold time, SDA valid after SCL low (for I2C-bus devices) 0 3.45(2) 0 0.9 µs
tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs
tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4.0 0.6 µs
tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
Cb(3) Capacitive load for each bus line 400 400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
(2) The maximum th(SDA-SCLL) for I2C-bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal.
(3) Cb = The total capacitance of one bus line in pF.
TMS570LS0714 i2c_timing_pns160.gif Figure 7-19 I2C Timings

NOTE

  • A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
  • The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal.
  • A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal (tw(SCLL)). If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line within tr max + tsu(SDA-SCLH). For the rise time, tr max value per load capacitance on the SDA pin, see Table 7-2, Rise time, tr, 2-mA-z low-EMI pins MAX values.
  • Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.

7.12 Multibuffered / Standard Serial Peripheral Interface

The MibSPI is a high-speed synchronous serial I/O port that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. Typical applications for the SPI include interfacing to external peripherals, such as I/Os, memories, display drivers, and ADCs.

7.12.1 Features

Both standard and MibSPI modules have the following features:

  • 16-bit shift register
  • Receive buffer register
  • 11-bit baud clock generator
  • SPICLK can be internally generated (master mode) or received from an external clock source (slave mode)
  • Each word transferred can have a unique format
  • SPI I/Os not used in the communication can be used as digital I/O signals

Table 7-32 MibSPI/SPI Configurations

MibSPIx/SPIx I/Os
MibSPI1 MIBSPI1SIMO[1:0], MIBSPI1SOMI[1:0], MIBSPI1CLK, MIBSPI1nCS[5:4,2:0], MIBSPI1nENA
MibSPI3 MIBSPI3SIMO, MIBSPI3SOMI, MIBSPI3CLK, MIBSPI3nCS[5:0], MIBSPI3nENA
MibSPI5 MIBSPI5SIMO[0], MIBSPI5SOMI[2:0], MIBSPI5CLK, MIBSPI5nCS[0], MIBSPI5nENA
SPI2 SPI2SIMO, SPI2SOMI, SPI2CLK, SPI2nCS[1:0], SPI2nENA
SPI4 SPI4SIMO, SPI4SOMI, SPI4CLK, SPI4nCS[0], SPI4nENA

7.12.2 MibSPI Transmit and Receive RAM Organization

The multibuffer RAM is comprised of 128 buffers. Each entry in the multibuffer RAM consists of four parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit control field, and a 16-bit status field. The multibuffer RAM can be partitioned into multiple transfer group with variable number of buffers each. Each MibSPIx module supports eight transfer groups.

7.12.3 MibSPI Transmit Trigger Events

Each transfer group can be configured individually. For each transfer group, a trigger event and a trigger source can be chosen. A trigger event can be for example a rising edge or a permanent low level at a selectable trigger source. For example, up to 15 trigger sources are available which can be used by each transfer group. These trigger options are listed in Table 7-33 and Section 7.12.3.2 for MibSPI1 and MibSPI3, respectively.

7.12.3.1 MibSPI1 Event Trigger Hookup

Table 7-33 MibSPI1 Event Trigger Hookup

EVENT NO. TGxCTRL TRIGSRC[3:0] TRIGGER
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 N2HET1[8]
EVENT9 1010 N2HET1[10]
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Intern Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI1 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI1 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx from triggering MibSPI1 transfers; there is no multiplexing on the input connections.

7.12.3.2 MibSPI3 Event Trigger Hookup

Table 7-34 MibSPI3 Event Trigger Hookup

EVENT NO. TGxCTRL TRIGSRC[3:0] TRIGGER
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 N2HET1[8]
EVENT9 1010 N2HET1[10]
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Intern Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI3 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI3 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx from triggering MibSPI3 transfers; there is no multiplexing on the input connections.

7.12.3.3 MibSPI5 Event Trigger Hookup

Table 7-35 MibSPI5 Event Trigger Hookup

EVENT NO. TGxCTRL TRIGSRC[3:0] TRIGGER
Disabled 0000 No trigger source
EVENT0 0001 GIOA[0]
EVENT1 0010 GIOA[1]
EVENT2 0011 GIOA[2]
EVENT3 0100 GIOA[3]
EVENT4 0101 GIOA[4]
EVENT5 0110 GIOA[5]
EVENT6 0111 GIOA[6]
EVENT7 1000 GIOA[7]
EVENT8 1001 N2HET1[8]
EVENT9 1010 N2HET1[10]
EVENT10 1011 N2HET1[12]
EVENT11 1100 N2HET1[14]
EVENT12 1101 N2HET1[16]
EVENT13 1110 N2HET1[18]
EVENT14 1111 Intern Tick counter

NOTE

For N2HET1 trigger sources, the connection to the MibSPI5 module trigger input is made from the input side of the output buffer (at the N2HET1 module boundary). This way, a trigger condition can be generated even if the N2HET1 signal is not selected to be output on the pad.

NOTE

For GIOx trigger sources, the connection to the MibSPI5 module trigger input is made from the output side of the input buffer. This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin and selecting the pin to be a GIOx pin, or by driving the GIOx pin from an external trigger source. If the mux control module is used to select different functionality instead of the GIOx signal, then care must be taken to disable GIOx from triggering MibSPI5 transfers; there is no multiplexing on the input connections.

7.12.4 MibSPI/SPI Master Mode I/O Timing Specifications

Table 7-36 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)(2)(3)

NO. PARAMETER MIN MAX UNIT
1 tc(SPC)M Cycle time, SPICLK(4) 40 256tc(VCLK) ns
2(5) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
3(5) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
4(5) td(SPCH-SIMO)M Delay time, SPISIMO valid before SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 6 ns
td(SPCL-SIMO)M Delay time, SPISIMO valid before SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 6
5(5) tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC) – 4 ns
tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC) – 4
6(5) tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 0) tf(SPC) + 2.2 ns
tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 1) tr(SPC) + 2.2
7(5) th(SPCL-SOMI)M Hold time, SPISOMI data valid after SPICLK low (clock polarity = 0) 10 ns
th(SPCH-SOMI)M Hold time, SPISOMI data valid after SPICLK high (clock polarity = 1) 10
8(6) tC2TDELAY Setup time CS active until SPICLK high (clock polarity = 0) CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5 ns
CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tr(SPC) – 7 (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tr(SPC) + 5.5
Setup time CS active until SPICLK low (clock polarity = 1) CSHOLD = 0 C2TDELAY*tc(VCLK) + 2*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 (C2TDELAY+2) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5
CSHOLD = 1 C2TDELAY*tc(VCLK) + 3*tc(VCLK) - tf(SPICS) + tf(SPC) – 7 (C2TDELAY+3) * tc(VCLK) - tf(SPICS) + tf(SPC) + 5.5
9(6) tT2CDELAY Hold time SPICLK low until CS inactive (clock polarity = 0) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) - 7 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) + tr(SPICS) + 11 ns
Hold time SPICLK high until CS inactive (clock polarity = 1) 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) - 7 0.5*tc(SPC)M + T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) + tr(SPICS) + 11
10 tSPIENA SPIENAn Sample point (C2TDELAY+1) * tc(VCLK) - tf(SPICS) – 29 (C2TDELAY+1)*tc(VCLK) ns
11 tSPIENAW SPIENAn Sample point from write to buffer (C2TDELAY+2)*tc(VCLK) ns
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see Table 7-2.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.
TMS570LS0714 master_mode_external_timing_phase0_pns160.gif Figure 7-20 SPI Master Mode External Timing (CLOCK PHASE = 0)
TMS570LS0714 master_mode_chip_select_phase0_pns160.gif Figure 7-21 SPI Master Mode Chip-Select Timing (CLOCK PHASE = 0)

Table 7-37 SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)(2)(3)

NO. PARAMETER MIN MAX UNIT
1 tc(SPC)M Cycle time, SPICLK (4) 40 256tc(VCLK) ns
2(5) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3
3(5) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – tf(SPC)M – 3 0.5tc(SPC)M + 3 ns
tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – tr(SPC)M – 3 0.5tc(SPC)M + 3
4(5) tv(SIMO-SPCH)M Valid time, SPICLK high after SPISIMO data valid (clock polarity = 0) 0.5tc(SPC)M – 6 ns
tv(SIMO-SPCL)M Valid time, SPICLK low after SPISIMO data valid (clock polarity = 1) 0.5tc(SPC)M – 6
5(5) tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)M – tr(SPC) – 4 ns
tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)M – tf(SPC) – 4
6(5) tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 0) tr(SPC)+ 2.2 ns
tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 1) tf(SPC)+ 2.2
7(5) tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 10 ns
tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 10
8(6) tC2TDELAY Setup time CS active until SPICLK high (clock polarity = 0) CSHOLD = 0 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) -
tf(SPICS) + tr(SPC) – 7		 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) -
tf(SPICS) + tr(SPC) + 5.5		 ns
CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) -
tf(SPICS) + tr(SPC) – 7		 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) -
tf(SPICS) + tr(SPC) + 5.5
Setup time CS active until SPICLK low (clock polarity = 1) CSHOLD = 0 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) -
tf(SPICS) + tf(SPC) – 7		 0.5*tc(SPC)M + (C2TDELAY+2) * tc(VCLK) -
tf(SPICS) + tf(SPC) + 5.5
CSHOLD = 1 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) -
tf(SPICS) + tf(SPC) – 7		 0.5*tc(SPC)M + (C2TDELAY+3) * tc(VCLK) -
tf(SPICS) + tf(SPC) + 5.5
9(6) tT2CDELAY Hold time SPICLK low until CS inactive (clock polarity = 0) T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) +
tr(SPICS) - 7		 T2CDELAY*tc(VCLK) + tc(VCLK) - tf(SPC) +
tr(SPICS) + 11		 ns
Hold time SPICLK high until CS inactive (clock polarity = 1) T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) +
tr(SPICS) - 7		 T2CDELAY*tc(VCLK) + tc(VCLK) - tr(SPC) +
tr(SPICS) + 11
10 tSPIENA SPIENAn Sample Point (C2TDELAY+1)* tc(VCLK) - tf(SPICS) – 29 (C2TDELAY+1)*tc(VCLK) ns
11 tSPIENAW SPIENAn Sample point from write to buffer (C2TDELAY+2)*tc(VCLK) ns
(1) The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3) For rise and fall timings, see Table 7-2.
(4) When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40 ns.
The external load on the SPICLK pin must be less than 60 pF.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register.
TMS570LS0714 master_mode_external_timing_phase1_pns160.gif Figure 7-22 SPI Master Mode External Timing (CLOCK PHASE = 1)
TMS570LS0714 master_mode_chip_select_phase1_pns160.gif Figure 7-23 SPI Master Mode Chip-Select Timing (CLOCK PHASE = 1)

7.12.5 SPI Slave Mode I/O Timings

Table 7-38 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input,
SPISIMO = input, and SPISOMI = output)(1)(2)(3)(4)

NO. PARAMETER MIN MAX UNIT
1 tc(SPC)S Cycle time, SPICLK(5) 40 ns
2(6) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14 ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
3(6) tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
4(6) td(SPCH-SOMI)S Delay time, SPISOMI valid after SPICLK high (clock polarity = 0) trf(SOMI) + 20 ns
td(SPCL-SOMI)S Delay time, SPISOMI valid after SPICLK low (clock polarity = 1) trf(SOMI) + 20
5(6) th(SPCH-SOMI)S Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) 2 ns
th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) 2
6(6) tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 4 ns
tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 4
7(6) th(SPCL-SIMO)S Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0) 2 ns
th(SPCH-SIMO)S Hold time, SPISIMO data valid after S PICLK high (clock polarity = 1) 2
8 td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+22 ns
td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+22
9 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK)+tf(ENAn)+27 ns
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 7-2.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
TMS570LS0714 slave_mode_external_timing_phase0_pns160.gif Figure 7-24 SPI Slave Mode External Timing (CLOCK PHASE = 0)
TMS570LS0714 slave_mode_enable_timing_phase0_pns160.gif Figure 7-25 SPI Slave Mode Enable Timing (CLOCK PHASE = 0)

Table 7-39 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output)(1)(2)(3)(4)

NO. PARAMETER MIN MAX UNIT
1 tc(SPC)S Cycle time, SPICLK(5) 40 ns
2(6) tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 14 ns
tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 14
3(6) tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 14 ns
tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 14
4(6) td(SOMI-SPCL)S Delay time, SPISOMI data valid after SPICLK low (clock polarity = 0) trf(SOMI) + 20 ns
td(SOMI-SPCH)S Delay time, SPISOMI data valid after SPICLK high (clock polarity = 1) trf(SOMI) + 20
5(6) th(SPCL-SOMI)S Hold time, SPISOMI data valid after SPICLK high (clock polarity =0) 2 ns
th(SPCH-SOMI)S Hold time, SPISOMI data valid after SPICLK low (clock polarity =1) 2
6(6) tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 4 ns
tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 4
7(6) tv(SPCH-SIMO)S High time, SPISIMO data valid after SPICLK high (clock polarity = 0) 2 ns
tv(SPCL-SIMO)S High time, SPISIMO data valid after SPICLK low (clock polarity = 1) 2
8 td(SPCH-SENAH)S Delay time, SPIENAn high after last SPICLK high (clock polarity = 0) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+22 ns
td(SPCL-SENAH)S Delay time, SPIENAn high after last SPICLK low (clock polarity = 1) 1.5tc(VCLK) 2.5tc(VCLK)+tr(ENAn)+22
9 td(SCSL-SENAL)S Delay time, SPIENAn low after SPICSn low (if new data has been written to the SPI buffer) tf(ENAn) tc(VCLK)+tf(ENAn)
+27		 ns
10 td(SCSL-SOMI)S Delay time, SOMI valid after SPICSn low (if new data has been written to the SPI buffer) tc(VCLK) 2tc(VCLK)+trf(SOMI)+28 ns
(1) The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2) If the SPI is in slave mode, the following must be true: tc(SPC)S ≤ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3) For rise and fall timings, see Table 7-2.
(4) tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5) When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40 ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40 ns.
(6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
TMS570LS0714 slave_mode_external_timing_phase1_pns160.gif Figure 7-26 SPI Slave Mode External Timing (CLOCK PHASE = 1)
TMS570LS0714 slave_mode_enable_timing_phase1_pns160.gif Figure 7-27 SPI Slave Mode Enable Timing (CLOCK PHASE = 1)