SPNS226E June 2013 – November 2016 TMS570LS0714
PRODUCTION DATA.
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The device core logic is split up into multiple power domains to optimize the power for a given application use case. There are five core power domains: PD1, PD2, PD3, PD5, and RAM_PD1. See Section 1.4 for more information.
PD1 is an "always-ON" power domain, which cannot be turned off. Each of the other core power domains can be turned ON/OFF one time during device initialization as per the application requirement. Refer to the Power Management Module (PMM) chapter of the device technical reference manual for more details.
NOTE
The clocks to a module must be turned off before powering down the core domain that contains the module.
A voltage monitor is implemented on this device. The purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and I/O voltage supplies.
The voltage monitor generates the Power Good MCU signal (PGMCU) as well as the I/Os Power Good IO signal (PGIO) on the device. During power-up or power-down, the PGMCU and PGIO are driven low when the core or I/O supplies are lower than the specified minimum monitoring thresholds. The PGIO and PGMCU signals being low isolates the core logic as well as the I/O controls during power up or power down of the supplies. This allows the core and I/O supplies to be powered up or down in any order.
When the voltage monitor detects a low voltage on the I/O supply, it will assert a power-on reset. When the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. The voltage monitor is disabled when the device enters a low power mode.
The VMON also incorporates a glitch filter for the nPORRST input. Refer to Section 6.3.3.1 for the timing information on this glitch filter.
PARAMETER | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
VMON | Voltage monitoring thresholds | VCC low - VCC level below this threshold is detected as too low. | 0.75 | 0.9 | 1.13 | V |
VCC high - VCC level above this threshold is detected as too high. | 1.40 | 1.7 | 2.1 | |||
VCCIO low - VCCIO level below this threshold is detected as too low. | 1.85 | 2.4 | 2.9 |
The VMON has the capability to filter glitches on the VCC and VCCIO supplies.
The following table shows the characteristics of the supply filtering. Glitches in the supply larger than the maximum specification cannot be filtered.
PARAMETER | MIN | MAX | UNIT |
---|---|---|---|
Width of glitch on VCC that can be filtered | 250 | 1000 | ns |
Width of glitch on VCCIO that can be filtered | 250 | 1000 | ns |
There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage. The power-up sequence starts with the I/O voltage rising above the minimum I/O supply threshold, (see Table 6-4 for more details), core voltage rising above the minimum core supply threshold and the release of power-on reset. The high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. The oscillator start-up time is dependent on the type of oscillator and is provided by the oscillator vendor. The different supplies to the device can be powered up in any order.
The device goes through the following sequential phases during power up.
Oscillator start-up and validity check | 1032 oscillator cycles |
eFuse autoload | 1160 oscillator cycles |
Flash pump power-up | 688 oscillator cycles |
Flash bank power-up | 617 oscillator cycles |
Total | 3497 oscillator cycles |
The CPU reset is released at the end of the above sequence and fetches the first instruction from address 0x00000000.
The different supplies to the device can be powered down in any order.
This is the power-on reset. This reset must be asserted by an external circuitry whenever any power supply is outside the specified recommended range. This signal has a glitch filter on it. It also has an internal pulldown.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
VCCPORL | VCC low supply level when nPORRST must be active during power up | 0.5 | V | ||
VCCPORH | VCC high supply level when nPORRST must remain active during power up and become active during power down | 1.14 | V | ||
VCCIOPORL | VCCIO / VCCP low supply level when nPORRST must be active during power up | 1.1 | V | ||
VCCIOPORH | VCCIO / VCCP high supply level when nPORRST must remain active during power up and become active during power down | 3.0 | V | ||
VIL(PORRST) | Low-level input voltage of nPORRST VCCIO > 2.5 V | 0.2 * VCCIO | V | ||
Low-level input voltage of nPORRST VCCIO < 2.5 V | 0.5 | V | |||
3 | tsu(PORRST) | Setup time, nPORRST active before VCCIO and VCCP > VCCIOPORL during power up | 0 | ms | |
6 | th(PORRST) | Hold time, nPORRST active after VCC > VCCPORH | 1 | ms | |
7 | tsu(PORRST) | Setup time, nPORRST active before VCC < VCCPORH during power down | 2 | µs | |
8 | th(PORRST) | Hold time, nPORRST active after VCCIO and VCCP > VCCIOPORH | 1 | ms | |
9 | th(PORRST) | Hold time, nPORRST active after VCC < VCCPORL | 0 | ms | |
tf(nPORRST) |
Filter time nPORRST pin; |
475 | 2000 | ns |
This is a bidirectional reset signal. The internal circuitry drives the signal low on detecting any device reset condition. An external circuit can assert a device reset by forcing the signal low. On this terminal, the output buffer is implemented as an open drain (drives low only). To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. It also has an internal pullup
DEVICE EVENT | SYSTEM STATUS FLAG |
---|---|
Power-Up Reset | Exception Status Register, bit 15 |
Oscillator fail | Global Status Register, bit 0 |
PLL slip | Global Status Register, bits 8 and 9 |
Watchdog exception / Debugger reset | Exception Status Register, bit 13 |
CPU Reset (driven by the CPU STC) | Exception Status Register, bit 5 |
Software Reset | Exception Status Register, bit 4 |
External Reset | Exception Status Register, bit 3 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
tv(RST) | Valid time, nRST active after nPORRST inactive | 2256tc(OSC) | ns | |
Valid time, nRST active (all other System reset conditions) | 32tc(VCLK) | |||
tf(nRST) |
Filter time nRST pin; |
475 | 2000 | ns |
The features of the ARM Cortex-R4F CPU include:
For more information on the ARM Cortex-R4F CPU, see www.arm.com.
The following CPU features are disabled on reset and must be enabled by the application if required.
The device has two Cortex-R4F cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed by two clock cycles as shown in Figure 6-2.
The CPUs have a diverse CPU placement given by following requirements:
The CPU clock domain is split into two clock trees, one for each CPU, with the clock of the second CPU running at the same frequency and in phase to the clock of CPU1. See Figure 6-2.
This device has two ARM Cortex-R4F CPU cores, where the output signals of both CPUs are compared in the CCM-R4 unit. To avoid common mode impacts the signals of the CPUs to be compared are delayed in a different way as shown in Figure 6-2.
To avoid an erroneous CCM-R4 compare error, the application software must initialize the registers of both CPUs before the registers are used, including function calls where the register values are pushed onto the stack.
The CPU STC (Self-Test Controller) is used to test the two Cortex-R4F CPU Cores using the Deterministic Logic BIST Controller as the test engine.
The main features of the self-test controller are:
For more information see the device Technical Reference Manual.
The maximum clock rate for the self-test is HCLKmax/2. The STCCLK is divided down from the CPU clock. This divider is configured by the STCCLKDIV register at address 0xFFFFE108.
For more information see the device-specific Technical Reference Manual.
Table 6-7 lists the CPU self-test coverage achieved for each self-test interval. It also lists the cumulative test cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.
INTERVALS | TEST COVERAGE, % | STCCLK CYLCES |
---|---|---|
0 | 0 | 0 |
1 | 62.13 | 1365 |
2 | 70.09 | 2730 |
3 | 74.49 | 4095 |
4 | 77.28 | 5460 |
5 | 79.28 | 6825 |
6 | 80.90 | 8190 |
7 | 82.02 | 9555 |
8 | 83.10 | 10920 |
9 | 84.08 | 12285 |
10 | 84.87 | 13650 |
11 | 85.59 | 15015 |
12 | 86.11 | 16380 |
13 | 86.67 | 17745 |
14 | 87.16 | 19110 |
15 | 87.61 | 20475 |
16 | 87.98 | 21840 |
17 | 88.38 | 23205 |
18 | 88.69 | 24570 |
19 | 88.98 | 25935 |
20 | 89.28 | 27300 |
21 | 89.50 | 28665 |
22 | 89.76 | 30030 |
23 | 90.01 | 31395 |
24 | 90.21 | 32760 |
Table 6-8 lists the available clock sources on the device. Each clock source can be enabled or disabled using the CSDISx registers in the system module. The clock source number in the table corresponds to the control bit in the CSDISx register for that clock source.
Table 6-8 also shows the default state of each clock source.
CLOCK SOURCE NO. |
NAME | DESCRIPTION | DEFAULT STATE |
---|---|---|---|
0 | OSCIN | Main oscillator | Enabled |
1 | PLL1 | Output from PLL1 | Disabled |
2 | Reserved | Reserved | Disabled |
3 | EXTCLKIN1 | External clock input 1 | Disabled |
4 | LFLPO | Low-frequency output of internal reference oscillator | Enabled |
5 | HFLPO | High-frequency output of internal reference oscillator | Enabled |
6 | Reserved | Reserved | Disabled |
7 | EXTCLKIN2 | External clock input 2 | Disabled |
The oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6-4. The oscillator is a single-stage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and low power modes.
NOTE
TI strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. The vendors are equipped to determine which load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature and voltage extremes.
An external oscillator source can be used by connecting a 3.3-V clock signal to the OSCIN pin and leaving the OSCOUT pin unconnected (open) as shown in Figure 6-4.
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
tc(OSC) | Cycle time, OSCIN (when using a sine-wave input) | 50 | 200 | ns | |
tw(OSCIL) | Pulse duration, OSCIN low (when input to the OSCIN is a square wave) | 15 | ns | ||
tw(OSCIH) | Pulse duration, OSCIN high (when input to the OSCIN is a square wave) | 15 | ns |
The Low-Power Oscillator (LPO) is comprised of two oscillators — HF LPO and LF LPO, in a single macro.
The main features of the LPO are:
Figure 6-5 shows a block diagram of the internal reference oscillator. This is a low-power oscillator (LPO) and provides two clock sources: one nominally 80 kHz and one nominally 10 MHz.
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Clock detection | Oscillator fail frequency - lower threshold, using untrimmed LPO output | 1.375 | 2.4 | 4.875 | MHz |
Oscillator fail frequency - higher threshold, using untrimmed LPO output | 22 | 38.4 | 78 | MHz | |
LPO - HF oscillator | Untrimmed frequency | 5.5 | 9 | 19.5 | MHz |
Trimmed frequency | 8 | 9.6 | 11 | MHz | |
Start-up time from STANDBY (LPO BIAS_EN high for at least 900 µs) | 10 | µs | |||
Cold start-up time | 900 | µs | |||
LPO - LF oscillator | Untrimmed frequency | 36 | 85 | 180 | kHz |
Start-up time from STANDBY (LPO BIAS_EN high for at least 900 µs) | 100 | µs | |||
Cold start-up time | 2000 | µs |
The PLL is used to multiply the input frequency to some higher frequency.
The main features of the PLL are:
Figure 6-6 shows a high-level block diagram of the PLL macro on this microcontroller.
The device supports up to two external clock inputs. This clock input must be a square-wave input. Table 6-12 specifies the electrical and timing requirements for these clock inputs. The external clock sources are not checked for validity. They are assumed valid when enabled.
PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|
fEXTCLKx | External clock input frequency | 80 | MHz | |
tw(EXTCLKIN)H | EXTCLK high-pulse duration | 6 | ns | |
tw(EXTCLKIN)L | EXTCLK low-pulse duration | 6 | ns | |
viL(EXTCLKIN) | Low-level input voltage | –0.3 | 0.8 | V |
viH(EXTCLKIN) | High-level input voltage | 2 | VCCIO + 0.3 | V |
Table 6-13 lists the device clock domains and their default clock sources. The table also shows the system module control register that is used to select an available clock source for each clock domain.
CLOCK DOMAIN | DEFAULT SOURCE |
SOURCE SELECTION REGISTER |
SPECIAL CONSIDERATIONS |
---|---|---|---|
HCLK | OSCIN | GHVSRC |
|
GCLK | OSCIN | GHVSRC |
|
GCLK2 | OSCIN | GHVSRC |
|
VCLK | OSCIN | GHVSRC |
|
VCLK2 | OSCIN | GHVSRC |
|
VCLK4 | OSCIN | GHVSRC |
|
VCLKA1 | VCLK | VCLKASRC |
|
RTICLK | VCLK | RCLKSRC |
|
Each clock domain has a dedicated functionality as shown in Figure 6-7 .
The platform architecture defines a special mode that allows various clock signals to be selected and output on the ECLK pin and N2HET1[12] device outputs. This special mode, Clock Test Mode, is very useful for debugging purposes and can be configured through the CLKTEST register in the system module. See Table 6-14 for the CLKTEST bits value and signal selection.
The LPO Clock Detect (LPOCLKDET) module consists of a clock monitor (CLKDET) and an internal LPO.
The LPO provides two different clock sources – a low frequency (LFLPO) and a high frequency (HFLPO).
The CLKDET is a supervisor circuit for an externally supplied clock signal (OSCIN). In case the OSCIN frequency falls out of a frequency window, the CLKDET flags this condition in the global status register (GLBSTAT bit 0: OSC FAIL) and switches all clock domains sourced by OSCIN to the HFLPO clock (limp mode clock).
The valid OSCIN frequency range is defined as: fHFLPO / 4 < fOSCIN < fHFLPO * 4.
For more information on LPO and Clock detection, see Table 6-10.
The ECLK pin can be configured to output a prescaled clock signal indicative of an internal device clock. This output can be externally monitored as a safety diagnostic.
The Dual Clock Comparator (DCC) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). If one clock is out of spec, an error signal is generated. For example, the DCC1 can be configured to use HFLPO as the reference clock (for counter 0) and VCLK as the "clock under test" (for counter 1). This configuration allows the DCC1 to monitor the PLL output clock when VCLK is using the PLL output as its source.
An additional use of this module is to measure the frequency of a selectable clock source, using the input clock as a reference, by counting the pulses of two independent clock sources. Counter 0 generates a fixed-width counting window after a preprogrammed number of pulses. Counter 1 generates a fixed-width pulse (1 cycle) after a preprogrammed number of pulses. This pulse sets as an error signal if counter 1 does not reach 0 within the counting window generated by counter 0.
CLOCK SOURCE[3:0] | CLOCK NAME |
---|---|
Others | Oscillator (OSCIN) |
0x5 | High-frequency LPO |
0xA | Test clock (TCK) |
CLOCK SOURCE [3:0] | CLOCK NAME |
---|---|
Others | Oscillator (OSCIN) |
0xA | Test clock (TCK) |
KEY [3:0] | CLOCK SOURCE [3:0] | CLOCK NAME |
---|---|---|
Others | – | N2HET2[0] |
0xA | 00x0 - 0x7 | Reserved |
0x8 - 0xF | VCLK |
A glitch filter is present on the following signals.
PIN | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
nPORRST | tf(nPORRST) |
Filter time nPORRST pin; pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset(1) |
475 | 2000 | ns |
nRST | tf(nRST) |
Filter time nRST pin; pulses less than MIN will be filtered out, pulses greater than MAX will generate a reset |
475 | 2000 | ns |
TEST | tf(TEST) |
Filter time TEST pin; pulses less than MIN will be filtered out, pulses greater than MAX will pass through |
475 | 2000 | ns |
Figure 6-9 shows the device memory map.
The Flash memory is mirrored to support ECC logic testing. The base address of the mirrored Flash image is 0x2000 0000.
See Figure 1-1 for block diagrams showing the devices interconnect.
Any CPU write access to a Normal or Device type memory, which generates a fault, will generate an imprecise abort. The imprecise abort exception is disabled by default and must be enabled for the CPU to handle this exception. The imprecise abort handling is enabled by clearing the "A" bit in the CPU program status register (CPSR).
Table 6-21 lists the access permissions for each bus master on the device. A bus master is a module that can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. Yes indicates that the module listed in the MASTERS column can access that slave module.
MASTERS | ACCESS MODE | SLAVES ON MAIN SCR | ||||
---|---|---|---|---|---|---|
Flash Module Bus2 Interface: OTP, ECC, Bank 7 |
Non-CPU Accesses to Program Flash and CPU Data RAM | CRC | Slave Interfaces | Peripheral Control Registers, All Peripheral Memories, And All System Module Control Registers And Memories | ||
CPU READ | User/Privilege | Yes | Yes | Yes | Yes | Yes |
CPU WRITE | User/Privilege | No | Yes | Yes | Yes | Yes |
DMA | User | Yes | Yes | Yes | Yes | Yes |
DAP | Privilege | Yes | Yes | Yes | Yes | Yes |
HTU1 | Privilege | No | Yes | Yes | Yes | Yes |
HTU2 | Privilege | No | Yes | Yes | Yes | Yes |
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU (master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in a power domain that has been turned off.
Flash Bank: A separate block of logic consisting of 1 to 16 sectors. Each flash bank normally has a customer-OTP and a TI-OTP area. These flash sectors share input/output buffers, data paths, sense amplifiers, and control logic.
Flash Sector: A contiguous region of flash memory which must be erased simultaneously due to physical construction constraints.
Flash Pump: A charge pump which generates all the voltages required for reading, programming, or erasing the flash banks.
Flash Module: Interface circuitry required between the host CPU and the flash banks and pump module.
MEMORY ARRAYS (OR BANKS) | SECTOR NO. | SEGMENT | LOW ADDRESS | HIGH ADDRESS |
---|---|---|---|---|
BANK0 (768KB)(1) | 0 | 16KB | 0x0000_0000 | 0x0000_3FFF |
1 | 16KB | 0x0000_4000 | 0x0000_7FFF | |
2 | 16KB | 0x0000_8000 | 0x0000_BFFF | |
3 | 16KB | 0x0000_C000 | 0x0000_FFFF | |
4 | 16KB | 0x0001_0000 | 0x0001_3FFF | |
5 | 16KB | 0x0001_4000 | 0x0001_7FFF | |
6 | 32KB | 0x0001_8000 | 0x0001_FFFF | |
7 | 128KB | 0x0002_0000 | 0x0003_FFFF | |
8 | 128KB | 0x0004_0000 | 0x0005_FFFF | |
9 | 128KB | 0x0006_0000 | 0x0007_FFFF | |
10 | 128KB | 0x0008_0000 | 0x0009_FFFF | |
11 | 128KB | 0x000A_0000 | 0x000B_FFFF | |
BANK7 (64KB) for EEPROM emulation(2)(3)(4) | 0 | 4KB | 0xF020_0000 | 0xF020_0FFF |
1 | 4KB | 0xF020_1000 | 0xF020_1FFF | |
2 | 4KB | 0xF020_2000 | 0xF020_2FFF | |
3 | 4KB | 0xF020_3000 | 0xF020_3FFF | |
4 | 4KB | 0xF020_4000 | 0xF020_4FFF | |
5 | 4KB | 0xF020_5000 | 0xF020_5FFF | |
6 | 4KB | 0xF020_6000 | 0xF020_6FFF | |
7 | 4KB | 0xF020_7000 | 0xF020_7FFF | |
8 | 4KB | 0xF020_8000 | 0xF020_8FFF | |
9 | 4KB | 0xF020_9000 | 0xF020_9FFF | |
10 | 4KB | 0xF020_A000 | 0xF020_AFFF | |
11 | 4KB | 0xF020_B000 | 0xF020_BFFF | |
12 | 4KB | 0xF020_C000 | 0xF020_CFFF | |
13 | 4KB | 0xF020_D000 | 0xF020_DFFF | |
14 | 4KB | 0xF020_E000 | 0xF020_EFFF | |
15 | 4KB | 0xF020_F000 | 0xF020_FFFF |
All accesses to the program flash memory are protected by SECDED logic embedded inside the CPU. The flash module provides 8 bits of ECC code for 64 bits of instructions or data fetched from the flash memory. The CPU calculates the expected ECC code based on the 64 bits received and compares it with the ECC code returned by the flash module. A single-bit error is corrected and flagged by the CPU, while a multibit error is only flagged. The CPU signals an ECC error through its Event bus. This signaling mechanism is not enabled by default and must be enabled by setting the "X" bit of the Performance Monitor Control Register, c9.
MRC p15,#0,r1,c9,c12,#0 ;Enabling Event monitor states
ORR r1, r1, #0x00000010
MCR p15,#0,r1,c9,c12,#0 ;Set 4th bit (‘X’) of PMNC register
MRC p15,#0,r1,c9,c12,#0
The application must also explicitly enable the ECC checking of the CPU for accesses on the CPU ATCM and BTCM interfaces. These are connected to the program flash and data RAM, respectively. ECC checking for these interfaces can be done by setting the B1TCMPCEN, B0TCMPCEN, and ATCMPCEN bits of the System Control Coprocessor Auxiliary Control Register, c1.
MRC p15, #0, r1, c1, c0, #1
ORR r1, r1, #0x0e000000 ;Enable ECC checking for ATCM and BTCMs
DMB
MCR p15, #0, r1, c1, c0, #1
For information on flash memory access speeds and the relevant wait states required, see Section 5.8.1.2.
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tprog(144bit) | Wide Word (144-bit) programming time | 40 | 300 | µs | ||
tprog(Total) | 768KB programming time(1) | –40°C to 125°C | 8 | s | ||
0°C to 60°C, for first 25 cycles | 2 | 4 | s | |||
terase(bank0) | Sector/Bank erase time(2) | –40°C to 125°C | 0.03 | 4 | s | |
0°C to 60°C, for first 25 cycles | 16 | 100 | ms | |||
twec | Write/erase cycles with 15-year Data Retention requirement | –40°C to 125°C | 1000 | cycles |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
tprog(144bit) | Wide Word (72-bit) programming time | 47 | 310 | µs | ||
tprog(Total) | EEPROM Emulation (bank 7) 64KByte programming time(1) | –40°C to 125°C | 2.6 | s | ||
0°C to 60°C, for first 25 cycles | 775 | 1435 | ms | |||
terase(bank7) | Sector/Bank erase time, EEPROM Emulation (bank 7) | –40°C to 125°C | 0.2 | 8 | s | |
0°C to 60°C, for first 25 cycles | 14 | 100 | ms | |||
twec | Write/erase cycles with 15-year Data Retention requirement | –40°C to 125°C | 100000 | cycles |
Figure 6-10 shows the connection of the Tightly Coupled RAM (TCRAM) to the Cortex-R4F™ CPU.
The features of the Tightly Coupled RAM (TCRAM) Module are:
The TCRAMW passes on the ECC code for each data read by the Cortex-R4F CPU from the RAM. The TCRAMW also stores the ECC port contents of the CPU in the ECC RAM when the CPU does a write to the RAM. The TCRAMW monitors the CPU event bus and provides registers for indicating single-bit or multibit errors and also for identifying the address that caused the single or multi-bit error. The event signaling and the ECC checking for the RAM accesses must be enabled inside the CPU.
For more information, see the device-specific Technical Reference Manual.
Accesses to some peripheral RAMs are protected by odd/even parity checking. During a read access the parity is calculated based on the data read from the peripheral RAM and compared with the good parity value stored in the parity RAM for that peripheral. If any word fails the parity check, the module generates a parity error signal that is mapped to the Error Signaling Module. The module also captures the peripheral RAM address that caused the parity error.
The parity protection for peripheral RAMs is not enabled by default and must be enabled by the application. Each individual peripheral contains control registers to enable the parity protection for accesses to its RAM.
NOTE
The CPU read access gets the actual data from the peripheral. The application can choose to generate an interrupt whenever a peripheral RAM parity error is detected.
MEMORY | RAM GROUP |
TEST CLOCK | MEM TYPE |
Test Pattern (Algorithm) | |||
---|---|---|---|---|---|---|---|
TRIPLE READ SLOW READ |
TRIPLE READ FAST READ |
MARCH 13N(1)
TWO PORT (cycles) |
MARCH 13N(1)
SINGLE PORT (cycles) |
||||
ALGO MASK 0x1 | ALGO MASK 0x2 | ALGO MASK 0x4 | ALGO MASK 0x8 | ||||
PBIST_ROM | 1 | ROM CLK | ROM | 24578 | 8194 | ||
STC_ROM | 2 | ROM CLK | ROM | 19586 | 6530 | ||
DCAN1 | 3 | VCLK | Dual port | 25200 | |||
DCAN2 | 4 | VCLK | Dual port | 25200 | |||
DCAN3 | 5 | VCLK | Dual port | 25200 | |||
ESRAM1(2) | 6 | HCLK | Single port | 266280 | |||
MIBSPI1 | 7 | VCLK | Dual port | 33440 | |||
MIBSPI3 | 8 | VCLK | Dual port | 33440 | |||
MIBSPI5 | 9 | VCLK | Dual port | 33440 | |||
VIM | 10 | VCLK | Dual port | 12560 | |||
MIBADC1 | 11 | VCLK | Dual port | 4200 | |||
DMA | 12 | HCLK | Dual port | 18960 | |||
N2HET1 | 13 | VCLK | Dual port | 31680 | |||
HET TU1 | 14 | VCLK | Dual port | 6480 | |||
MIBADC2 | 18 | VCLK | Dual port | 4200 | |||
N2HET2 | 19 | VCLK | Dual port | 31680 | |||
HET TU2 | 20 | VCLK | Dual port | 6480 | |||
ESRAM5(3) | 21 | HCLK | Single port | 266280 |
The PBIST ROM clock frequency is limited to 100 MHz, if 100 MHz < HCLK <= HCLKmax, or HCLK, if HCLK <= 100 MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
This microcontroller allows some of the on-chip memories to be initialized through the Memory Hardware Initialization mechanism in the system module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC).
The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized.
For more information on these registers, see the device-specific Technical Reference Manual.
The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in Table 6-26.
CONNECTING MODULE | ADDRESS RANGE | MSINENA REGISTER BIT # | |
---|---|---|---|
BASE ADDRESS | ENDING ADDRESS | ||
RAM (PD#1) | 0x08000000 | 0x0800FFFF | 0(1) |
RAM (RAM_PD#1) | 0x08010000 | 0x0801FFFF | 0(1) |
MIBSPI5 RAM | 0xFF0A0000 | 0xFF0BFFFF | 12(2) |
MIBSPI3 RAM | 0xFF0C0000 | 0xFF0DFFFF | 11(2) |
MIBSPI1 RAM | 0xFF0E0000 | 0xFF0FFFFF | 7(2) |
DCAN3 RAM | 0xFF1A0000 | 0xFF1BFFFF | 10 |
DCAN2 RAM | 0xFF1C0000 | 0xFF1DFFFF | 6 |
DCAN1 RAM | 0xFF1E0000 | 0xFF1FFFFF | 5 |
MIBADC2 RAM | 0xFF3A0000 | 0xFF3BFFFF | 14 |
MIBADC1 RAM | 0xFF3E0000 | 0xFF3FFFFF | 8 |
N2HET2 RAM | 0xFF440000 | 0xFF45FFFF | 15 |
N2HET1 RAM | 0xFF460000 | 0xFF47FFFF | 3 |
HET TU2 RAM | 0xFF4C0000 | 0xFF4DFFFF | 16 |
HET TU1 RAM | 0xFF4E0000 | 0xFF4FFFFF | 4 |
DMA RAM | 0xFFF80000 | 0xFFF80FFF | 1 |
VIM RAM | 0xFFF82000 | 0xFFF82FFF | 2 |
The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and controlling the many interrupt sources present on this device. Interrupts are caused by events outside of the normal flow of program execution. Normally, these events require a timely response from the CPU; therefore, when an interrupt occurs, the CPU switches execution from the normal program flow to an interrupt service routine (ISR).
The VIM module has the following features:
NOTE
Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry; therefore only request channels 0..126 can be used and are offset by one address in the VIM RAM.
NOTE
The lower-order interrupt channels are higher priority channels than the higher-order interrupt channels.
NOTE
The application can change the mapping of interrupt sources to the interrupt channels through the interrupt channel control registers (CHANCTRLx) inside the VIM module.
The DMA controller is used to transfer data between two locations in the memory map in the background of CPU operations. Typically, the DMA is used to:
The DMA module on this microcontroller has 16 channels and up to 32 hardware DMA requests. The module contains DREQASIx registers which are used to map the DMA requests to the DMA channels. By default, channel 0 is mapped to request 0, channel 1 to request 1, and so on.
Some DMA requests have multiple sources, as shown in Table 6-28. The application must ensure that only one of these DMA request sources is enabled at any time.
Modules | DMA Request Sources | DMA Request |
---|---|---|
MIBSPI1 | MIBSPI1[1](1) | DMAREQ[0] |
MIBSPI1 | MIBSPI1[0](2) | DMAREQ[1] |
SPI2 | SPI2 receive | DMAREQ[2] |
SPI2 | SPI2 transmit | DMAREQ[3] |
MIBSPI1 / MIBSPI3 / DCAN2 | MIBSPI1[2] / MIBSPI3[2] / DCAN2 IF3 | DMAREQ[4] |
MIBSPI1 / MIBSPI3 / DCAN2 | MIBSPI1[3] / MIBSPI3[3] / DCAN2 IF2 | DMAREQ[5] |
DCAN1 / MIBSPI5 | DCAN1 IF2 / MIBSPI5[2] | DMAREQ[6] |
MIBADC1 / MIBSPI5 | MIBADC1 event / MIBSPI5[3] | DMAREQ[7] |
MIBSPI1 / MIBSPI3 / DCAN1 | MIBSPI1[4] / MIBSPI3[4] / DCAN1 IF1 | DMAREQ[8] |
MIBSPI1 / MIBSPI3 / DCAN2 | MIBSPI1[5] / MIBSPI3[5] / DCAN2 IF1 | DMAREQ[9] |
MIBADC1 / I2C / MIBSPI5 | MIBADC1 G1 / I2C receive / MIBSPI5[4] | DMAREQ[10] |
MIBADC1 / I2C / MIBSPI5 | MIBADC1 G2 / I2C transmit / MIBSPI5[5] | DMAREQ[11] |
RTI / MIBSPI1 / MIBSPI3 | RTI DMAREQ0 / MIBSPI1[6] / MIBSPI3[6] | DMAREQ[12] |
RTI / MIBSPI1 / MIBSPI3 | RTI DMAREQ1 / MIBSPI1[7] / MIBSPI3[7] | DMAREQ[13] |
MIBSPI3 / MibADC2 / MIBSPI5 | MIBSPI3[1](1) / MibADC2 event / MIBSPI5[6] | DMAREQ[14] |
MIBSPI3 / MIBSPI5 | MIBSPI3[0](2) / MIBSPI5[7] | DMAREQ[15] |
MIBSPI1 / MIBSPI3 / DCAN1 / MibADC2 | MIBSPI1[8] / MIBSPI3[8] / DCAN1 IF3 / MibADC2 G1 | DMAREQ[16] |
MIBSPI1 / MIBSPI3 / DCAN3 / MibADC2 | MIBSPI1[9] / MIBSPI3[9] / DCAN3 IF1 / MibADC2 G2 | DMAREQ[17] |
RTI / MIBSPI5 | RTI DMAREQ2 / MIBSPI5[8] | DMAREQ[18] |
RTI / MIBSPI5 | RTI DMAREQ3 / MIBSPI5[9] | DMAREQ[19] |
N2HET1 / N2HET2 / DCAN3 | N2HET1 DMAREQ[4] / N2HET2 DMAREQ[4] / DCAN3 IF2 | DMAREQ[20] |
N2HET1 / N2HET2 / DCAN3 | N2HET1 DMAREQ[5] / N2HET2 DMAREQ[5] / DCAN3 IF3 | DMAREQ[21] |
MIBSPI1 / MIBSPI3 / MIBSPI5 | MIBSPI1[10] / MIBSPI3[10] / MIBSPI5[10] | DMAREQ[22] |
MIBSPI1 / MIBSPI3 / MIBSPI5 | MIBSPI1[11] / MIBSPI3[11] / MIBSPI5[11] | DMAREQ[23] |
N2HET1 / N2HET2 / SPI4 / MIBSPI5 | N2HET1 DMAREQ[6] / N2HET2 DMAREQ[6] / SPI4 receive / MIBSPI5[12] | DMAREQ[24] |
N2HET1 / N2HET2 / SPI4 / MIBSPI5 | N2HET1 DMAREQ[7] / N2HET2 DMAREQ[7] / SPI4 transmit / MIBSPI5[13] | DMAREQ[25] |
CRC / MIBSPI1 / MIBSPI3 | CRC DMAREQ[0] / MIBSPI1[12] / MIBSPI3[12] | DMAREQ[26] |
CRC / MIBSPI1 / MIBSPI3 | CRC DMAREQ[1] / MIBSPI1[13] / MIBSPI3[13] | DMAREQ[27] |
LIN / MIBSPI5 | LIN receive / MIBSPI5[14] | DMAREQ[28] |
LIN / MIBSPI5 | LIN transmit / MIBSPI5[15] | DMAREQ[29] |
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5 | MIBSPI1[14] / MIBSPI3[14] / SCI receive / MIBSPI5[1](1) | DMAREQ[30] |
MIBSPI1 / MIBSPI3 / SCI / MIBSPI5 | MIBSPI1[15] / MIBSPI3[15] / SCI transmit / MIBSPI5[0](2) | DMAREQ[31] |
The real-time interrupt (RTI) module provides timer functionality for operating systems and for benchmarking code. The RTI module can incorporate several counters that define the time bases needed for scheduling an operating system.
The timers also let you benchmark certain areas of code by reading the values of the counters at the beginning and the end of the desired code range and calculating the difference between the values.
The RTI module has the following features:
Figure 6-11 shows a high-level block diagram for one of the two 64-bit counter blocks inside the RTI module. Both the counter blocks are identical except the Network Time Unit (NTUx) inputs are only available as time-base inputs for the counter block 0. Figure 6-12 shows the compare unit block diagram of the RTI module.
The RTI module uses the RTI1CLK clock domain for generating the RTI time bases.
The application can select the clock source for the RTI1CLK by configuring the RCLKSRC register in the system module at address 0xFFFFFF50. The default source for RTI1CLK is VCLK.
For more information on clock sources, see Table 6-8 and Table 6-13.
The RTI module supports four Network Time Unit (NTU) inputs that signal internal system events, and which can be used to synchronize the time base used by the RTI module. On this device, these NTU inputs are connected as shown in Table 6-29.
NTU INPUT | SOURCE |
---|---|
0 | Reserved |
1 | Reserved |
2 | Reserved |
3 | EXTCLKIN1 clock input |
The Error Signaling Module (ESM) manages the various error conditions on the TMS570 microcontroller. The error condition is handled based on a fixed severity level assigned to it. Any severe error condition can be configured to drive a low level on a dedicated device terminal called nERROR. The nERROR can be used as an indicator to an external monitor circuit to put the system into a safe state.
The features of the ESM are:
The ESM integrates all the device error conditions and groups them in the order of severity. Group1 is used for errors of the lowest severity while Group3 is used for errors of the highest severity. The device response to each error is determined by the severity group it is connected to. Table 6-31 lists the channel assignment for each group.
ERROR GROUP | INTERRUPT CHARACTERISTICS | INFLUENCE ON ERROR TERMINAL |
---|---|---|
Group1 | Maskable, low or high priority | Configurable |
Group2 | Nonmaskable, high priority | Fixed |
Group3 | No interrupt generated | Fixed |
ERROR CONDITION | GROUP | CHANNELS |
---|---|---|
Group1 | ||
Reserved | Group1 | 0 |
MibADC2 - RAM parity error | Group1 | 1 |
DMA - MPU configuration violation | Group1 | 2 |
DMA - control packet RAM parity error | Group1 | 3 |
Reserved | Group1 | 4 |
DMA - error on DMA read access, imprecise error | Group1 | 5 |
FMC - correctable ECC error: bus1 and bus2 interfaces (does not include accesses to Bank 7) |
Group1 | 6 |
N2HET1 - RAM parity error | Group1 | 7 |
HET TU1/HET TU2 - dual-control packet RAM parity error | Group1 | 8 |
HET TU1/HET TU2 - MPU configuration violation | Group1 | 9 |
PLL1 - Slip | Group1 | 10 |
Clock Monitor - oscillator fail | Group1 | 11 |
Reserved | Group1 | 12 |
DMA - error on DMA write access, imprecise error | Group1 | 13 |
Reserved | Group1 | 14 |
VIM RAM - parity error | Group1 | 15 |
Reserved | Group1 | 16 |
MibSPI1 - RAM parity error | Group1 | 17 |
MibSPI3 - RAM parity error | Group1 | 18 |
MibADC1 - RAM parity error | Group1 | 19 |
Reserved | Group1 | 20 |
DCAN1 - RAM parity error | Group1 | 21 |
DCAN3 - RAM parity error | Group1 | 22 |
DCAN2 - RAM parity error | Group1 | 23 |
MibSPI5 - RAM parity error | Group1 | 24 |
Reserved | Group1 | 25 |
RAM even bank (B0TCM) - correctable ECC error | Group1 | 26 |
CPU - self-test failed | Group1 | 27 |
RAM odd bank (B1TCM) - correctable ECC error | Group1 | 28 |
Reserved | Group1 | 29 |
DCC1 - error | Group1 | 30 |
CCM-R4 - self-test failed | Group1 | 31 |
Reserved | Group1 | 32 |
Reserved | Group1 | 33 |
N2HET2 - RAM parity error | Group1 | 34 |
FMC - correctable ECC error (Bank 7 access) | Group1 | 35 |
FMC - uncorrectable ECC error (Bank 7 access) | Group1 | 36 |
IOMM - Access to unimplemented location in IOMM frame, or write access detected in unprivileged mode | Group1 | 37 |
Power domain controller compare error | Group1 | 38 |
Power domain controller self-test error | Group1 | 39 |
eFuse Controller Error – this error signal is generated when any bit in the eFuse controller error status register is set. The application can choose to generate an interrupt whenever this bit is set to service any eFuse controller error conditions. | Group1 | 40 |
eFuse Controller - Self-Test Error. This error signal is generated only when a self-test on the eFuse controller generates an error condition. When an ECC self-test error is detected, group 1 channel 40 error signal will also be set. | Group1 | 41 |
Reserved | Group1 | 42 |
Reserved | Group1 | 43 |
Reserved | Group1 | 44 |
Reserved | Group1 | 45 |
Reserved | Group1 | 46 |
Reserved | Group1 | 47 |
Reserved | Group1 | 48 |
Reserved | Group1 | 49 |
Reserved | Group1 | 50 |
Reserved | Group1 | 51 |
Reserved | Group1 | 52 |
Reserved | Group1 | 53 |
Reserved | Group1 | 54 |
Reserved | Group1 | 55 |
Reserved | Group1 | 56 |
Reserved | Group1 | 57 |
Reserved | Group1 | 58 |
Reserved | Group1 | 59 |
Reserved | Group1 | 60 |
Reserved | Group1 | 61 |
DCC2 - error | Group1 | 62 |
Reserved | Group1 | 63 |
Group2 | ||
Reserved | Group2 | 0 |
Reserved | Group2 | 1 |
CCMR4 - dual-CPU lock-step error | Group2 | 2 |
Reserved | Group2 | 3 |
FMC - uncorrectable address parity error on accesses to main flash | Group2 | 4 |
Reserved | Group2 | 5 |
RAM even bank (B0TCM) - uncorrectable redundant address decode error | Group2 | 6 |
Reserved | Group2 | 7 |
RAM odd bank (B1TCM) - uncorrectable redundant address decode error | Group2 | 8 |
Reserved | Group2 | 9 |
RAM even bank (B0TCM) - address bus parity error | Group2 | 10 |
Reserved | Group2 | 11 |
RAM odd bank (B1TCM) - address bus parity error | Group2 | 12 |
Reserved | Group2 | 13 |
Reserved | Group2 | 14 |
Reserved | Group2 | 15 |
TCM - ECC live lock detect | Group2 | 16 |
Reserved | Group2 | 17 |
Reserved | Group2 | 18 |
Reserved | Group2 | 19 |
Reserved | Group2 | 20 |
Reserved | Group2 | 21 |
Reserved | Group2 | 22 |
Reserved | Group2 | 23 |
Windowed Watchdog (WWD) violation | Group2 | 24 |
Reserved | Group2 | 25 |
Reserved | Group2 | 26 |
Reserved | Group2 | 27 |
Reserved | Group2 | 28 |
Reserved | Group2 | 29 |
Reserved | Group2 | 30 |
Reserved | Group2 | 31 |
Group3 | ||
Reserved | Group3 | 0 |
eFuse Farm - autoload error | Group3 | 1 |
Reserved | Group3 | 2 |
RAM even bank (B0TCM) - ECC uncorrectable error | Group3 | 3 |
Reserved | Group3 | 4 |
RAM odd bank (B1TCM) - ECC uncorrectable error | Group3 | 5 |
Reserved | Group3 | 6 |
FMC - uncorrectable ECC error: bus1 and bus2 interfaces (does not include address parity error and errors on accesses to Bank 7) |
Group3 | 7 |
Reserved | Group3 | 8 |
Reserved | Group3 | 9 |
Reserved | Group3 | 10 |
Reserved | Group3 | 11 |
Reserved | Group3 | 12 |
Reserved | Group3 | 13 |
Reserved | Group3 | 14 |
Reserved | Group3 | 15 |
Reserved | Group3 | 16 |
Reserved | Group3 | 17 |
Reserved | Group3 | 18 |
Reserved | Group3 | 19 |
Reserved | Group3 | 20 |
Reserved | Group3 | 21 |
Reserved | Group3 | 22 |
Reserved | Group3 | 23 |
Reserved | Group3 | 24 |
Reserved | Group3 | 25 |
Reserved | Group3 | 26 |
Reserved | Group3 | 27 |
Reserved | Group3 | 28 |
Reserved | Group3 | 29 |
Reserved | Group3 | 30 |
Reserved | Group3 | 31 |
ERROR SOURCE | CPUMODE | ERROR RESPONSE | ESM HOOKUP GROUP.CHANNEL |
---|---|---|---|
CPU TRANSACTIONS | |||
Precise write error (NCNB/Strongly Ordered) | User/Privilege | Precise Abort (CPU) | N/A |
Precise read error (NCB/Device or Normal) | User/Privilege | Precise Abort (CPU) | N/A |
Imprecise write error (NCB/Device or Normal) | User/Privilege | Imprecise Abort (CPU) | N/A |
Illegal instruction | User/Privilege | Undefined Instruction Trap (CPU)(1) | N/A |
MPU access violation | User/Privilege | Abort (CPU) | N/A |
SRAM | |||
B0 TCM (even) ECC single error (correctable) | User/Privilege | ESM | 1.26 |
B0 TCM (even) ECC double error (uncorrectable) | User/Privilege | Abort (CPU), ESM => → nERROR | 3.3 |
B0 TCM (even) uncorrectable error (that is, redundant address decode) | User/Privilege | ESM => NMI => nERROR | 2.6 |
B0 TCM (even) address bus parity error | User/Privilege | ESM => NMI => nERROR | 2.10 |
B1 TCM (odd) ECC single error (correctable) | User/Privilege | ESM | 1.28 |
B1 TCM (odd) ECC double error (uncorrectable) | User/Privilege | Abort (CPU), ESM => nERROR | 3.5 |
B1 TCM (odd) uncorrectable error (that is, redundant address decode) | User/Privilege | ESM => NMI => nERROR | 2.8 |
B1 TCM (odd) address bus parity error | User/Privilege | ESM => NMI => nERROR | 2.12 |
FLASH WITH CPU BASED ECC | |||
FMC correctable error - Bus1 and Bus2 interfaces (does not include accesses to Bank 7) | User/Privilege | ESM | 1.6 |
FMC uncorrectable error - Bus1 and Bus2 accesses (does not include address parity error) |
User/Privilege | Abort (CPU), ESM => nERROR | 3.7 |
FMC uncorrectable error - address parity error on Bus1 accesses | User/Privilege | ESM => NMI => nERROR | 2.4 |
FMC correctable error - Accesses to Bank 7 | User/Privilege | ESM | 1.35 |
FMC uncorrectable error - Accesses to Bank 7 | User/Privilege | ESM | 1.36 |
DMA TRANSACTIONS | |||
External imprecise error on read (Illegal transaction with ok response) | User/Privilege | ESM | 1.5 |
External imprecise error on write (Illegal transaction with ok response) | User/Privilege | ESM | 1.13 |
Memory access permission violation | User/Privilege | ESM | 1.2 |
Memory parity error | User/Privilege | ESM | 1.3 |
HET TU1 (HTU1) | |||
NCNB (Strongly Ordered) transaction with slave error response | User/Privilege | Interrupt => VIM | N/A |
External imprecise error (Illegal transaction with ok response) | User/Privilege | Interrupt => VIM | N/A |
Memory access permission violation | User/Privilege | ESM | 1.9 |
Memory parity error | User/Privilege | ESM | 1.8 |
HET TU2 (HTU2) | |||
NCNB (Strongly Ordered) transaction with slave error response | User/Privilege | Interrupt => VIM | N/A |
External imprecise error (Illegal transaction with ok response) | User/Privilege | Interrupt => VIM | N/A |
Memory access permission violation | User/Privilege | ESM | 1.9 |
Memory parity error | User/Privilege | ESM | 1.8 |
N2HET1 | |||
Memory parity error | User/Privilege | ESM | 1.7 |
N2HET2 | |||
Memory parity error | User/Privilege | ESM | 1.34 |
MIBSPI | |||
MibSPI1 memory parity error | User/Privilege | ESM | 1.17 |
MibSPI3 memory parity error | User/Privilege | ESM | 1.18 |
MibSPI5 memory parity error | User/Privilege | ESM | 1.24 |
MIBADC | |||
MibADC1 memory parity error | User/Privilege | ESM | 1.19 |
MibADC2 memory parity error | User/Privilege | ESM | 1.1 |
DCAN | |||
DCAN1 memory parity error | User/Privilege | ESM | 1.21 |
DCAN2 memory parity error | User/Privilege | ESM | 1.23 |
DCAN3 memory parity error | User/Privilege | ESM | 1.22 |
PLL | |||
PLL slip error | User/Privilege | ESM | 1.10 |
CLOCK MONITOR | |||
Clock monitor interrupt | User/Privilege | ESM | 1.11 |
DCC | |||
DCC1 error | User/Privilege | ESM | 1.30 |
DCC2 error | User/Privilege | ESM | 1.62 |
CCM-R4 | |||
Self-test failure | User/Privilege | ESM | 1.31 |
Compare failure | User/Privilege | ESM => NMI => nERROR | 2.2 |
VIM | |||
Memory parity error | User/Privilege | ESM | 1.15 |
VOLTAGE MONITOR | |||
VMON out of voltage range | N/A | Reset | N/A |
CPU SELF-TEST (LBIST) | |||
Cortex-R4F CPU self-test (LBIST) error | User/Privilege | ESM | 1.27 |
PIN MULTIPLEXING CONTROL | |||
Mux configuration error | User/Privilege | ESM | 1.37 |
POWER DOMAIN CONTROL | |||
PSCON compare error | User/Privilege | ESM | 1.38 |
PSCON self-test error | User/Privilege | ESM | 1.39 |
eFuse CONTROLLER | |||
eFuse Controller Autoload error | User/Privilege | ESM => nERROR | 3.1 |
eFuse Controller - Any bit set in the error status register | User/Privilege | ESM | 1.40 |
eFuse Controller self-test error | User/Privilege | ESM | 1.41 |
WINDOWED WATCHDOG | |||
WWD Nonmaskable Interrupt exception | N/A | ESM => NMI => nERROR | 2.24 |
ERRORS REFLECTED IN THE SYSESR REGISTER | |||
Power-Up Reset | N/A | Reset | N/A |
Oscillator fail / PLL slip(2) | N/A | Reset | N/A |
Watchdog exception | N/A | Reset | N/A |
CPU Reset (driven by the CPU STC) | N/A | Reset | N/A |
Software Reset | N/A | Reset | N/A |
External Reset | N/A | Reset | N/A |
This device includes a Digital Windowed Watchdog (DWWD) module that protects against runaway code execution (see Figure 6-13).
The DWWD module allows the application to configure the time window within which the DWWD module expects the application to service the watchdog. A watchdog violation occurs if the application services the watchdog outside of this window, or fails to service the watchdog at all. The application can choose to generate a system reset or an ESM group2 error signal in case of a watchdog violation.
The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog can only be disabled upon a system reset.
The device contains an ICEPICK module (version C) to allow JTAG access to the scan chains (see Figure 6-14).
MODULE NAME |
FRAME CHIP SELECT |
FRAME ADDRESS RANGE | FRAME SIZE |
ACTUAL SIZE |
RESPONSE FOR ACCESS TO UNIMPLEMENTED LOCATIONS IN FRAME |
|
---|---|---|---|---|---|---|
START | END | |||||
CoreSight Debug ROM | CSCS0 | 0xFFA0_0000 | 0xFFA0_0FFF | 4KB | 4KB | Reads return zeros, writes have no effect |
Cortex-R4F Debug | CSCS1 | 0xFFA0_1000 | 0xFFA0_1FFF | 4KB | 4KB | Reads return zeros, writes have no effect |
The JTAG ID code for this device is the same as the device ICEPick Identification Code. For the JTAG ID Code per silicon revision, see Table 6-34.
SILICON REVISION | ID |
---|---|
Rev 0 | 0x0BB0302F |
Rev A | 0x1BB0302F |
The Debug ROM stores the location of the components on the Debug APB bus (see Table 6-35).
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fTCK | TCK frequency (at HCLKmax) | 12 | MHz | ||
fRTCK | RTCK frequency (at TCKmax and HCLKmax) | 10 | MHz | ||
1 | td(TCK -RTCK) | Delay time, TCK to RTCK | 24 | ns | |
2 | tsu(TDI/TMS - RTCKr) | Setup time, TDI, TMS before RTCK rise (RTCKr) | 26 | ns | |
3 | th(RTCKr -TDI/TMS) | Hold time, TDI, TMS after RTCKr | 0 | ns | |
4 | th(RTCKr -TDO) | Hold time, TDO after RTCKf | 0 | ns | |
5 | td(TCKf -TDO) | Delay time, TDO valid after RTCK fall (RTCKf) | 12 | ns |
This device includes a an Advanced JTAG Security Module (AJSM) module. The AJSM provides maximum security to the memory content of the device by letting users secure the device after programming.
The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP address 0xF0000000. The OTP contents are XOR-ed with the contents of the "Unlock By Scan" register. The outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this combinational logic is compared against a secret hard-wired 128-bit value. A match results in the UNLOCK signal being asserted, so that the device is now unsecure.
A user can secure the device by changing at least 1 bit in the visible unlock code from 1 to 0. Changing a 0 to 1 is not possible because the visible unlock code is stored in the One Time Programmable (OTP) flash region. Also, changing all 128 bits to zeros is not a valid condition and will permanently secure the device.
Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By Scan" register of the AJSM module. This register is accessible by configuring an IR value of 0b1011 on the AJSM TAP. The value to be scanned is such that the XOR of the OTP contents and the Unlock-By-Scan register contents results in the original visible unlock code.
The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).
A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap 2 of the ICEPick module. All other secondary taps, test taps, and the boundary scan interface are not accessible in this state.
The device supports BSDL-compliant boundary scan for testing pin-to-pin compatibility. The boundary scan chain is connected to the Boundary Scan Interface of the ICEPICK module (see Figure 6-17).
Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO.