SPNS141G August   2010  – October 2018 TMS570LS10106 , TMS570LS10116 , TMS570LS10206 , TMS570LS20206 , TMS570LS20216

PRODUCTION DATA.  

  1. 1 TMS570LS Series 16/32-BIT RISC Flash Microcontroller
    1. 1.1 Features
    2. 1.2 Description
    3. 1.3 Functional Block Diagram
  2. 2 Device Overview
    1. 2.1 Terms and Acronyms
    2. 2.2 Device Characteristics
    3. 2.3 Memory
      1. 2.3.1 Memory Map
      2. 2.3.2 Flash Memory
      3. 2.3.3 System Modules Assignment
      4. 2.3.4 Peripheral Selects
      5. 2.3.5 Memory Auto-Initialization
      6. 2.3.6 PBIST RAM Self Test
    4. 2.4 Pin Assignments
      1. 2.4.1 PGE QFP Package Pinout (144 pin)
      2. 2.4.2 ZWT BGA Package Pinout (337 ball)
    5. 2.5 Terminal Functions
    6. 2.6 Device Support
      1. 2.6.1 Device and Development-Support Tool Nomenclature
  3. 3 Reset / Abort Sources
    1. 3.1 Reset / Abort Sources
  4. 4 Peripherals
    1. 4.1  Error Signaling Module (ESM)
    2. 4.2  Direct Memory Access (DMA)
    3. 4.3  High End Timer Transfer Unit (HET-TU)
    4. 4.4  Vectored Interrupt Manager (VIM)
    5. 4.5  MIBADC Event Trigger Sources
    6. 4.6  MIBSPI
      1. 4.6.1 MIBSPI Event Trigger Sources
      2. 4.6.2 MIBSPIP5/DMM Pin Multiplexing
    7. 4.7  ETM
    8. 4.8  Debug Scan Chains
      1. 4.8.1 JTAG
    9. 4.9  CCM
      1. 4.9.1 Dual Core Implementation
      2. 4.9.2 CCM-R4
    10. 4.10 LPM
    11. 4.11 Voltage Monitor
    12. 4.12 CRC
    13. 4.13 System Module Access
    14. 4.14 Debug ROM
    15. 4.15 CPU Self Test Controller: STC / LBIST
  5. 5 Device Registers
    1. 5.1 Device Identification Code Register
      1. Table 5-1 Device ID Bit Allocation Register Field Descriptions
    2. 5.2 Die-ID Registers
    3. 5.3 PLL Registers
  6. 6 Device Electrical Specifications
    1. 7 Operating Conditions
      1. 7.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)
      2. 7.2 Device Recommended Operating Conditions
      3. 7.3 Electrical Characteristics Over Operating Free-Air Temperature Range
  7. 8 Peripheral and Electrical Specifications
    1. 8.1  Clocks
      1. 8.1.1 PLL And Clock Specifications
      2. 8.1.2 External Reference Resonator/Crystal Oscillator Clock Option
      3. 8.1.3 Validated FMPLL Setting
      4. 8.1.4 LPO And Clock Detection
      5. 8.1.5 Switching Characteristics Over Recommended Operating Conditions For Clocks
        1. 8.1.5.1 Timing - Wait States
    2. 8.2  ECLK Specification
      1. 8.2.1 Switching Characteristics Over Recommended Operating Conditions For External Clocks
    3. 8.3  RST And PORRST Timings
      1. 8.3.1 Timing Requirements For PORRST
      2. 8.3.2 Switching Characteristics Over Recommended Operating Conditions For RST
      3. 8.3.3 IO Status During PORRST
    4. 8.4  TEST Pin Timing
    5. 8.5  DAP - JTAG Scan Interface Timing
      1. 8.5.1 JTAG clock specification 12-MHz and 50-pF load on TDO output
    6. 8.6  Output Timings
      1. 8.6.1 Switching Characteristics For Output Timings Versus Load Capacitance (CL)
    7. 8.7  Input Timings
      1. 8.7.1 Timing Requirements For Input Timings
    8. 8.8  Flash Timings
    9. 8.9  SPI Master Mode Timing Parameters
      1. 8.9.1 SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
      2. 8.9.2 SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
    10. 8.10 SPI Slave Mode Timing Parameters
      1. 8.10.1 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO = input, and SPISOMI = output)
      2. 8.10.2 SPI Slave Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO = input, and SPISOMI = output)
    11. 8.11 CAN Controller Mode Timings
      1. 8.11.1 Dynamic Characteristics For The CANnTX And CANnRX Pins
    12. 8.12 SCI/LIN Mode Timings
    13. 8.13 FlexRay Controller Mode Timings
      1. 8.13.1 Jitter Timing
    14. 8.14 EMIF Timings
      1. 8.14.1 Read Timing (Asynchronous RAM)
      2. 8.14.2 Write Timing (Asynchronous RAM)
    15. 8.15 ETM Timings
      1. 8.15.1 ETMTRACECLK Timing
      2. 8.15.2 ETMDATA Timing
    16. 8.16 RTP Timings
      1. 8.16.1 RTPCLK Timing
      2. 8.16.2 RTPDATA Timing
      3. 8.16.3 RTPENABLE Timing
    17. 8.17 DMM Timings
      1. 8.17.1 DMMCLK Timing
      2. 8.17.2 DMMDATA Timing
      3. 8.17.3 DMMENA Timing
    18. 8.18 MibADC
      1. 8.18.1 MibADC
      2. 8.18.2 MibADC Recommended Operating Conditions
      3. 8.18.3 Operating Characteristics Over Full Ranges Of Recommended Operating Conditions
      4. 8.18.4 MibADC Input Model
      5. 8.18.5 MibADC Timings
      6. 8.18.6 MibADC Nonlinearity Error
      7. 8.18.7 MibADC Total Error
  8. 9 Revision History
  9. 10Mechanical Packaging and Orderable Information
    1. 10.1 Thermal Data
      1. 10.1.1 PGE (S-PQFP-G144) plastic Quad Flat Pack
      2. 10.1.2 ZWT (S-PBGA-N337) Plastic ball grid array
    2. 10.2 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PGE|144
サーマルパッド・メカニカル・データ
発注情報

2.5 Terminal Functions

This following table describes the pins on the device.

NOTE

Table Abbreviations: PWR = power, GND = ground, REF = reference voltage, NC = no connect, IPD = Internal Pull Down, IPU = Internal Pull Up, I/O = Input/Output, I = Input, O = Output

Table 2-9 Terminal Functions

Terminal Type Internal pullup/pulldown Description
Name TMS570LSXXX16 TMS570LSXXX06
337 144 337 144
HIGH-END TIMER (NHET)
NHET[0] K18 105 K18 105 3.3V I/O 2mA - z programmable IPD (20uA) Timer input capture or output compare. The applicable NHET pins can be programmed as general-purpose input/output (GIO) pins. NHET pins are high-resolution.
The high-resolution (HR) SHARE feature allows even HR pins to share the next higher odd HR pin structures. The next higher odd HR pin structure is always implemented, even if the next higher odd HR pad and/or pin itself is not. The HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available externally and shared, then the odd pin can only be used as a general-purpose I/O.
NHET[0] provides SPI clock when used for SPI emulation.
Each NHET pin is equipped with an input suppression filter that can be used to eliminate the sampling of pulses that are smaller than a programmable duration
GIOA[0]/INT[0] is also connected to the NHET Pin Disable input of the NHET module.
NHET pins can be programmed as a GIO pins when not used as NHET functional pins.
NHET[1] V2 42 V2 42
NHET[2] W5 56 W5 56
NHET[3] U1 41 U1 41
NHET[4] B12 121 B12 121
NHET[5] V6 44 V6 44
NHET[6] W3 48 W3 48
NHET[7] T1 109 T1 109
NHET[8] E18 112 E18 112
NHET[9] V7 57 V7 57
NHET[10] D19 116 D19 116
NHET[11] E3 117 E3 117
NHET[12] B4 8 B4 8
NHET[13] N2 26 N2 26
NHET[14] A11 138 A11 138
NHET[15] N1 113 N1 113
NHET[16] A4 142 A4 142
NHET[17] A13 A13
NHET[18] J1 10 J1 10
NHET[19] B13 B13
NHET[20] P2 45 P2 45
NHET[21] H4 11 H4 11
NHET[22] B3 9 B3 9
NHET[23] J4 12 J4 12
NHET[24] P1 43 P1 43
NHET[25] M3 M3
NHET[26] A14 A14
NHET[27] A9 A9
NHET[28] K19 106 K19 106
NHET[29] A3 A3
NHET[30] B11 137 B11 137
NHET[31] J17 J17
GENERAL-PURPOSE I/O (GIO)
GIOA[0]/INT0 A5 118 A5 118 3.3V I/O 2mA - z Programmable IPD (20uA) General-purpose input/output pin. GIOA[0]/INT[0] is an interrupt-capable pin. GIOA[0]/INT[0] is also connected to the NHET Pin Disable input of the NHET module.
GIOA[1]/INT1 C2 134 C2 134 General-purpose input/output pins.GIOA[7:1]/INT[7:1] are interrupt-capable pins.
GIOA[2]/INT2 C1 141 C1 141
GIOA[3]/INT3 E1 144 E1 144
GIOA[4]/INT4 A6 110 A6 110
GIOA[5]/INT5 B5 111 B5 111
GIOA[6]/INT6 H3 27 H3 27
GIOA[7]/INT7 M1 51 M1 51
GIOB[0] M2 M2 General-purpose input/output pins.
GIOB[1] K2 K2
GIOB[2] F2 F2
GIOB[3] W10 W10
GIOB[4] G1 G1
GIOB[5] G2 G2
GIOB[6] J2 J2
GIOB[7] F1 F1
FlexRay Controller (FLEXRAY)
NOTE: Devices with out the FlexRay option should leave all FlexRay pins unconnected (NC)
FRAYRX1 A15 126 3.3V I Programmable IPD (20uA) FlexRay data receive (channel 1) pin
FRAYTX1 B15 124 3.3V O 8mA FlexRay data transmit (channel 1) pin
FRAYTXEN1 B16 125 8mA FlexRay transmit enable (channel 1) pin
FRAYRX2 A8 131 3.3V I Programmable IPD(20uA) FlexRay data receive (channel 2) pin
FRAYTX2 B8 129 3.3V O 8mA FlexRay data transmit (channel 2) pin
FRAYTXEN2 B9 130 8mA FlexRay transmit enable (channel 2) pin
CAN Controller (DCAN1)
CAN1TX A10 50 A10 50 3.3V I/O 2mA - z Programmable IPU (20uA) CAN1 transmit pin or GIO pin
CAN1RX B10 49 B10 49 CAN1 receive pin or GIO pin
CAN Controller (DCAN2)
CAN2TX H2 54 H2 54 3.3V I/O 2mA - z Programmable IPU (20uA) CAN2 transmit pin or GIO pin
CAN2RX H1 55 H1 55 CAN2 receive pin or GIO pin
CAN Controller (DCAN3)
CAN3TX M18 M18 3.3V I/O 2mA - z programmable IPU (20uA) CAN3 transmit pin or GIO pin
CAN3RX M19 M19 CAN3 receive pin or GIO pin
Serial Communications Interface (SCI)/Local Interconnect Network (LIN1)
LIN1RX W12 53 W12 53 3.3V I/O 2mA - z Programmable IPU (20uA) LIN1 data receive pin or GIO pin
LIN1TX V12 52 V12 52 LIN1 data transmit pin or GIO pin
Serial Communications Interface (SCI)/Local Interconnect Network (LIN2)
LIN2RX A7 140 A7 140 3.3V I/O 2mA - z Programmable IPU (20uA) LIN2 data receive pin or GIO pin
LIN2TX B7 139 B7 139 LIN2 data transmit pin or GIO pin
Multibuffered Serial Peripheral Interface (MIBSPI1)
MIBSPI1CLK F18 17 F18 17 3.3V I/O 4mA Programmable IPU (20uA) MIBSPI1 clock pin or GIO pin
MIBSPI1CS[0] R2 23 R2 23 2mA - z MIBSPI1 slave chip select pins or GIO pins
MIBSPI1CS[1] F3 24 F3 24
MIBSPI1CS[2] G3 25 G3 25
MIBSPI1CS[3] J3 J3
MIBSPI1ENA G19 18 G19 18 2mA - z MIBSPI1 enable pin or GIO pin
MIBSPI1SIMO F19 14 F19 14 4mA MIBSPI1 data stream - Slave in/master out pin or GIO pin
MIBSPI1SOMI G18 13 G18 13 MIBSPI1 data stream - Slave out/master in pin or GIO pin
Multibuffered Serial Peripheral Interface (MIBSPI3)
MIBSPI3CLK V9 3 V9 3 3.3V I/O 4mA Programmable IPU (20uA) MIBSPI3 clock pin or GIO pin
MIBSPI3CS[0] V10 7 V10 7 2mA - z MIBSPI3 slave chip select pins or GIO pins
MIBSPI3CS[1] V5 V5
MIBSPI3CS[2] B2 B2
MIBSPI3CS[3] C3 C3
MIBSPI3ENA W9 6 W9 6 2mA - z MIBSPI3 enable pin or GIO pin
MIBSPI3SIMO W8 4 W8 4 4mA MIBSPI3 data stream - Slave in/master out pin or GIO pin
MIBSPI3SOMI V8 5 V8 5 MIBSPI3 data stream - Slave out/master in pin or GIO pin
Multibuffered Serial Peripheral Interface - Parallel (MIBSPIP5)
MIBSPI5CLK/DMMDATA[4] H19 91 H19 91 3.3V I/O 4mA Programmable IPU (20uA) MIBSPI5 clock pin or GIO pin; multiplexed with DMMDATA[4] pin
MIBSPI5CS[0]/DMMDATA[5] E19 92 E19 92 2mA - z MIBSPI5 slave chip select pins or GIO pins; multiplexed with DMMDATA pins
MIBSPI5CS[1]/DMMDATA[6] B6 93 B6 93
MIBSPI5CS[2]/DMMDATA[2] W6 W6
MIBSPI5CS[3]/DMMDATA[3] T12 T12
MIBSPI5ENA/DMMDATA[7] H18 94 H18 94 MIBSPI5 enable pin or GIO pin; multiplexed with DMMDATA[7] pin
MIBSPI5SIMO[0]/DMMDATA[8] J19 95 J19 95 4mA MIBSPI5 data stream - Slave in/master out pins or GIO pins; multiplexed with DMMDATA pins
DMMDATA[9]/MIBSPI5SIMO[1] E16 96 E16 96
MIBSPI5SIMO[2]/DMMDATA[10] H17 97 H17 97
MIBSPI5SIMO[3]/DMMDATA[11] G17 98 G17 98
MIBSPI5SOMI[0]/DMMDATA[12] J18 99 J18 99 MIBSPI5 data stream - Slave out/master in pins or GIO pins; multiplexed with DMMDATA pins
MIBSPI5SOMI[1]/DMMDATA[13] E17 100 E17 100
MIBSPI5SOMI[2]/DMMDATA[14] H16 101 H16 101
MIBSPI5SOMI[3]/DMMDATA[15]/ G16 102 G16 102
Multibuffered Analog-To-Digital Converter (MIBADC1)
AD1EVT N19 84 N19 84 3.3V I/O 2 mA - z Programmable IPD (20uA) MibADC1 event input pin or GIO pin
AD1IN[0] W14 83 W14 83 3.3V I MibADC1 analog input pins
AD1IN[1] V17 82 V17 82
AD1IN[2] V18 81 V18 81
AD1IN[3] T17 80 T17 80
AD1IN[4] U18 79 U18 79
AD1IN[5] R17 78 R17 78
AD1IN[6] T19 77 T19 77
AD1IN[7] V14 76 V14 76
Multibuffered Analog-To-Digital Converter (MIBADC2)
AD2EVT W13 59 W13 59 3.3V I/O 2 mA - z Programmable IPD (20uA) MibADC2 event input pin or GIO pin
AD2IN[0] V13 60 V13 60 3.3 V I MibADC2 analog input pins
AD2IN[1] U13 61 U13 61
AD2IN[2] U14 62 U14 62
AD2IN[3] U16 63 U16 63
AD2IN[4] U15 U15
AD2IN[5] T15 T15
AD2IN[6] R19 R19
AD2IN[7] R16 R16
Multibuffered Analog-To-Digital Converter - shared signals (MIBADC1, MIBADC2)
ADSIN[8] P18 75 P18 75 3.3 V I MibADC1, MibADC2 shared analog input pins
ADSIN[9] W17 74 W17 74
ADSIN[10] U17 73 U17 73
ADSIN[11] U19 72 U19 72
ADSIN[12] T16 71 T16 71
ADSIN[13] T18 70 T18 70
ADSIN[14] R18 69 R18 69
ADSIN[15] P19 68 P19 68
ADREFHI V15 66 V15 66 3.3-V REF MibADC1, MibADC2 module high-voltage reference input
ADREFLO V16 65 V16 65 GND REF MibADC1, MibADC2 module low-voltage reference input
VCCAD W15 67 W15 67 3.3-V PWR MibADC1, MibADC2 analog supply voltage
VSSAD V19 64 V19 64 GND MibADC1, MibADC2 analog ground reference
VSSAD W16 W16
VSSAD W18 W18
VSSAD W19 W19
Oscillator (OSC)
OSCIN K1 20 K1 20 1.5V I Oscillator input connection pin or external clock input pin
OSCOUT L1 21 L1 21 1.5V O Oscillator ouptut connection pin
Kelvin_GND L2 L2 GND Kelvin_GND for oscillator
System Module (SYS)
PORRST W7 28 W7 28 3.3V I IPD (100µA) Power on Reset Pin. External power supply monitor circuitry must assert a power-on reset on this pin.
RST B17 85 B17 85 3.3V I/O 4mA IPU (100µA) Active Low Bidirectional Reset pin. An external device can assert a device reset on this pin.
The output buffer on this pin is implemented as an open drain (drives low only).
To ensure an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this pin.
ECLK A12 88 A12 88 8mA IPD (20µA) External Clock Prescaler module output pin or GIO pin
Tset/Debug (T/D)
TCK B18 30 B18 30 3.3V I IPD (100uA) JTAG test clock pin. Clocks the JTAG debug logic.
RTCK A16 35 A16 35 3.3V O 8 mA JTAG return test clock pin. (JTAG)
TDI A17 34 A17 34 3.3V I/O IPU (100uA) JTAG test data in pin.
TDO C18 33 C18 33 IPD (100uA) JTAG test data out pin.
TMS C19 36 C19 36 IPU (100uA) JTAG serial input pin for controlling the state of the CPU test access port (TAP) controller.
TRST D18 29 D18 29 3.3V I IPD (100uA) JTAG test hardware reset to TAP. IEEE Standard 1149-1 (JTAG) Boundary-Scan Logic
TEST U2 58 U2 58 IPD (100uA) Test enable pin. Reserved for internal TI use only. For proper operation, this pin must be connected to ground, e.g. using a external resistor.
Error Signaling Module (ESM)
ERROR B14 143 B14 143 3.3V I/O 8mA IPD (20uA) Error Signaling pin
Flash
FLTP1 J5 122 J5 122 Flash Test Pad 1 pin. For proper operation this pin must connect only to a test pad or not be connected at all [no connect (NC)]. The test pad must not be exposed in the final product where it might be subjected to an ESD event.
FLTP2 H5 123 H5 123 Flash Test Pad 2 pin. For proper operation this pin must connect only to a test pad or not be connected at all [no connect (NC)]. The test pad must not be exposed in the final product where it might be subjected to an ESD event.
VCCP F8 128 F8 128 3.3V PWR Flash pump voltage supply (3.3 V). This pin is required for Flash read, program and erase operations.
RAM Trace Port Module (RTP)
RTPDATA[0] V11 V11 3.3V I/O 8mA Programmable IPU (20uA) RAM Trace Port Output Data Signal pins or GIO pins
RTPDATA[1] U11 U11
RTPDATA[2] T10 T10
RTPDATA[3] U10 U10
RTPDATA[4] T9 T9
RTPDATA[5] U9 U9
RTPDATA[6] U8 U8
RTPDATA[7] U7 U7
RTPDATA[8] U6 U6
RTPDATA[9] U5 U5
RTPDATA[10] U4 U4
RTPDATA[11] T4 T4
RTPDATA[12] V3 V3
RTPDATA[13] U3 U3
RTPDATA[14] T3 T3
RTPDATA[15] T2 T2
RTPENA U12 U12 2mA - z Packet Handshake Signal pin or GIO pin
RTPSYNC T11 T11 8mA Packet Synchronization Signal pin or GIO pin
RTPCLK W11 W11 Packet Clock Signal pin or GIO pin
Data Modification Module (DMM)
DMMDATA[0] L19 L19 3.3V I/O 2mA - z Programmable IPU (20uA) DMM Data pins or GIO pins
DMMDATA[1] L18 L18
DMMDATA[2]/MIBSPI5CS[2] W6 W6 DMM Data pins or GIO pins; multiplexed with MIBSPI5 pins
DMMDATA[3]/MIBSPI5CS[3] T12 T12
DMMDATA[4]/MIBSPI5CLK H19 H19 4mA
DMMDATA[5]/MIBSPI5CS[0] E19 E19 2mA - z
DMMDATA[6]/MIBSPI5CS[1] B6 B6
DMMDATA[7]/MIBSPI5ENA H18 H18
DMMDATA[8]/MIBSPI5SIMO[0] J19 J19 4mA
DMMDATA[9]/MIBSPI5SIMO[1] E16 E16
DMMDATA[10]/MIBSPI5SIMO[2] H17 H17
DMMDATA[11]/MIBSPI5SIMO[3] G17 G17
DMMDATA[12]/MIBSPI5SOMI[0] J18 J18
DMMDATA[13]/MIBSPI5SOMI[1] E17 E17
DMMDATA[14]/MIBSPI5SOMI[2] H16 H16
DMMDATA[15]/MIBSPI5SOMI[3] G16 G16
DMMENA F16 F16 8mA DMM Handshake pin or GIO pin
DMMSYNC J16 J16 2mA - z DMM Synchronization pin or GIO pin
DMMCLK F17 F17 DMM Clock input pin or GIO pin
External Memory Interface Module (EMIF)
EMIFBADD[0] D13 D13 3.3V I/O 8mA EMIF Byte Address pins
EMIFBADD[1] D16 D16
EMIFDATA[0] K16 K16 3.3V I/O 8mA Programmable IPU (20uA) EMIF Data pins
EMIFDATA[1] L16 L16
EMIFDATA[2] M16 M16
EMIFDATA[3] N16 N16
EMIFDATA[4] E4 E4
EMIFDATA[5] F4 F4
EMIFDATA[6] G4 G4
EMIFDATA[7] K4 K4
EMIFDATA[8] L4 L4
EMIFDATA[9] M4 M4
EMIFDATA[10] N4 N4
EMIFDATA[11] P4 P4
EMIFDATA[12] T5 T5
EMIFDATA[13] T6 T6
EMIFDATA[14] T7 T7
EMIFDATA[15] T8 T8
EMIFADD[0] D4 D4 3.3V I/O 8mA EMIF Address pins
EMIFADD[1] D5 D5
EMIFADD[2] D6 D6
EMIFADD[3] D7 D7
EMIFADD[4] D8 D8
EMIFADD[5] D9 D9
EMIFADD[6] C4 C4
EMIFADD[7] C5 C5
EMIFADD[8] C6 C6
EMIFADD[9] C7 C7
EMIFADD[10] C8 C8
EMIFADD[11] C9 C9
EMIFADD[12] C10 C10
EMIFADD[13] C11 C11
EMIFADD[14] C12 C12
EMIFADD[15] C13 C13
EMIFADD[16] D14 D14
EMIFADD[17] C14 C14
EMIFADD[18] D15 D15
EMIFADD[19] C15 C15
EMIFADD[20] C16 C16
EMIFADD[21] C17 C17
EMIFCS[0] L17 L17 3.3V I/O 8mA EMIF Chip Select pins
EMIFCS[1] K17 K17
EMIFCS[2] M17 M17
EMIFCS[3] N17 N17
EMIFWE D17 D17 3.3V I/O 8mA EMIF Write Enable pin
EMIFOE D12 D12 3.3V I/O 8mA EMIF Output Enable pin
EMIFDQM[0] D10 D10 3.3V I/O 8mA EMIF Byte Enable pins
EMIFDQM[1] D11 D11
Embedded Trace Module (ETM)
ETMDATA[0] R12 R12 3.3V O 8mA ETM Trace Data output pins
ETMDATA[1] R13 R13
ETMDATA[2] J15 J15
ETMDATA[3] H15 H15
ETMDATA[4] G15 G15
ETMDATA[5] F15 F15
ETMDATA[6] E15 E15
ETMDATA[7] E14 E14
ETMDATA[8] E9 E9
ETMDATA[9] E8 E8
ETMDATA[10] E7 E7
ETMDATA[11] E6 E6
ETMDATA[12] E13 E13
ETMDATA[13] E12 E12
ETMDATA[14] E11 E11
ETMDATA[15] E10 E10
ETMDATA[16] K15 K15
ETMDATA[17] L15 L15
ETMDATA[18] M15 M15
ETMDATA[19] N15 N15
ETMDATA[20] E5 E5
ETMDATA[21] F5 F5
ETMDATA[22] G5 G5
ETMDATA[23] K5 K5
ETMDATA[24] L5 L5
ETMDATA[25] M5 M5
ETMDATA[26] N5 N5
ETMDATA[27] P5 P5
ETMDATA[28] R5 R5
ETMDATA[29] R6 R6
ETMDATA[30] R7 R7
ETMDATA[31] R8 R8
ETMTRACECTL R11 R11 3.3V O 8mA ETM Control pin
ETMTRACECLKOUT R10 R10 ETM Clock output pin
ETMTRACECLKIN R9 R9 3.3V I IPU (20uA) ETM Clock input pin
Supply Voltage Digital I/O (3.3V) and Core (1.5V)
VCCIO F6 1 F6 1 3.3V PWR Digital I/O supply pins
Note: All VccIO pads are connected to the BGA packages through the package substrate. There is not a direct ball to bond pad connection for this supply.
VCCIO F7 15 F7 15
VCCIO F11 40 F11 40
VCCIO F12 90 F12 90
VCCIO F13 108 F13 108
VCCIO F14 119 F14 119
VCCIO G6 132 G6 132
VCCIO G14 G14
VCCIO H6 H6
VCCIO H14 H14
VCCIO J6 J6
VCCIO L14 L14
VCCIO M6 M6
VCCIO M14 M14
VCCIO N6 N6
VCCIO N14 N14
VCCIO P6 P6
VCCIO P7 P7
VCCIO P8 P8
VCCIO P9 P9
VCCIO P12 P12
VCCIO P13 P13
VCCIO P14 P14
VCCIO
VCC F9 19 F9 19 1.5V PWR Digital Core supply pins
Note: All Vcc pads are connected to the BGA packages through the package substrate. There is not a direct ball to bond pad connection for this supply.
VCC F10 31 F10 31
VCC H10 37 H10 37
VCC J14 47 J14 47
VCC K6 87 K6 87
VCC K8 104 K8 104
VCC K12 114 K12 114
VCC K14 135 K14 135
VCC L6 L6
VCC M10 M10
VCC P10 P10
VCC P11 P11
VCC
Supply Ground
VSS A1 2 A1 2 GND Digital supply ground reference pins
Note: All Vss pads are connected to the BGA packages through the package substrate.
VSS A2 16 A2 16
VSS A18 22 A18 22
VSS A19 32 A19 32
VSS B1 38 B1 38
VSS B19 39 B19 39
VSS H8 46 H8 46
VSS H9 86 H9 86
VSS H11 89 H11 89
VSS H12 103 H12 103
VSS J8 107 J8 107
VSS J9 115 J9 115
VSS J10 120 J10 120
VSS J11 127 J11 127
VSS J12 133 J12 133
VSS K9 136 K9 136
VSS K10 K10
VSS K11 K11
VSS L8 L8
VSS L9 L9
VSS L10 L10
VSS L11 L11
VSS L12 L12
VSS M8 M8
VSS M9 M9
VSS M11 M11
VSS M12 M12
VSS V1 V1
VSS W1 W1
VSS W2 W2
VSS V4 V4
VSS
VSS
VSS
VSS
VSS