SPNS165B April   2012  – May 2015 TMS570LS2124 , TMS570LS2134 , TMS570LS3134

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 ZWT BGA Package Ball-Map (337-Ball Grid Array)
    2. 4.2 Terminal Functions
      1. 4.2.1 PGE Package
        1. 4.2.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.2.1.2  Enhanced Next Generation High-End Timer (N2HET) Modules
        3. 4.2.1.3  General-Purpose Input/Output (GPIO)
        4. 4.2.1.4  Controller Area Network Controllers (DCANs)
        5. 4.2.1.5  Local Interconnect Network Interface Module (LIN)
        6. 4.2.1.6  Standard Serial Communication Interface (SCI)
        7. 4.2.1.7  Inter-Integrated Circuit Interface Module (I2C)
        8. 4.2.1.8  Standard Serial Peripheral Interface (SPI)
        9. 4.2.1.9  Multibuffered Serial Peripheral Interface Modules (MibSPI)
        10. 4.2.1.10 System Module Interface
        11. 4.2.1.11 Clock Inputs and Outputs
        12. 4.2.1.12 Test and Debug Modules Interface
        13. 4.2.1.13 Flash Supply and Test Pads
        14. 4.2.1.14 Supply for Core Logic: 1.2-V Nominal
        15. 4.2.1.15 Supply for I/O Cells: 3.3-V Nominal
        16. 4.2.1.16 Ground Reference for All Supplies Except VCCAD
      2. 4.2.2 ZWT Package
        1. 4.2.2.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.2.2.2  Enhanced Next Generation High-End Timer (N2HET) Modules
        3. 4.2.2.3  General-Purpose Input/Output (GPIO)
        4. 4.2.2.4  Controller Area Network Controllers (DCANs)
        5. 4.2.2.5  Local Interconnect Network Interface Module (LIN)
        6. 4.2.2.6  Standard Serial Communication Interface (SCI)
        7. 4.2.2.7  Inter-Integrated Circuit Interface Module (I2C)
        8. 4.2.2.8  Standard Serial Peripheral Interface (SPI)
        9. 4.2.2.9  Multibuffered Serial Peripheral Interface Modules (MibSPI)
        10. 4.2.2.10 External Memory Interface (EMIF)
        11. 4.2.2.11 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
        12. 4.2.2.12 RAM Trace Port (RTP)
        13. 4.2.2.13 Data Modification Module (DMM)
        14. 4.2.2.14 System Module Interface
        15. 4.2.2.15 Clock Inputs and Outputs
        16. 4.2.2.16 Test and Debug Modules Interface
        17. 4.2.2.17 Flash Supply and Test Pads
        18. 4.2.2.18 Reserved
        19. 4.2.2.19 No Connects
        20. 4.2.2.20 Supply for Core Logic: 1.2-V Nominal
        21. 4.2.2.21 Supply for I/O Cells: 3.3-V Nominal
        22. 4.2.2.22 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Switching Characteristics for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption
    8. 5.8  Input/Output Electrical Characteristics
    9. 5.9  Thermal Resistance Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM Cortex-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low-Power Oscillator (LPO)
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Master/Slave Access Privileges
        1. 6.9.3.1 Special Notes on Accesses to Certain Slaves
      4. 6.9.4 POM Overlay Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Flash Program and Erase Timings for Program Flash
      6. 6.10.6 Flash Program and Erase Timings for Data Flash
    11. 6.11 Tightly Coupled RAM (TCRAM) Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAM Interface ECC Support
    12. 6.12 Parity Protection for Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1  Block Diagram
      2. 6.21.2  Debug Components Memory Map
      3. 6.21.3  JTAG Identification Code
      4. 6.21.4  Debug ROM
      5. 6.21.5  JTAG Scan Interface Timings
      6. 6.21.6  Advanced JTAG Security Module
      7. 6.21.7  Embedded Trace Macrocell (ETM-R4)
        1. 6.21.7.1 ETM TRACECLKIN Selection
        2. 6.21.7.2 Timing Specifications
      8. 6.21.8  RAM Trace Port (RTP)
        1. 6.21.8.1 Features
        2. 6.21.8.2 Timing Specifications
      9. 6.21.9  Data Modification Module (DMM)
        1. 6.21.9.1 Features
        2. 6.21.9.2 Timing Specifications
      10. 6.21.10 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1 Peripheral Legend
    2. 7.2 Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 Default MIBADC1 Event Trigger Hookup
        2. 7.2.2.2 Alternate MIBADC1 Event Trigger Hookup
        3. 7.2.2.3 Default MIBADC2 Event Trigger Hookup
        4. 7.2.2.4 Alternate MIBADC2 Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3 General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4 Enhanced Next Generation High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET1-N2HET2 Interconnections
      5. 7.4.5 N2HET Checking
        1. 7.4.5.1 Internal Monitoring
        2. 7.4.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.4.6 Disabling N2HET Outputs
      7. 7.4.7 High-End Timer Transfer Unit (HTU)
        1. 7.4.7.1 Features
        2. 7.4.7.2 Trigger Connections
    5. 7.5 Controller Area Network (DCAN)
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
    6. 7.6 Local Interconnect Network Interface (LIN)
      1. 7.6.1 LIN Features
    7. 7.7 Serial Communication Interface (SCI)
      1. 7.7.1 Features
    8. 7.8 Inter-Integrated Circuit (I2C)
      1. 7.8.1 Features
      2. 7.8.2 I2C I/O Timing Specifications
    9. 7.9 Multibuffered / Standard Serial Peripheral Interface
      1. 7.9.1 Features
      2. 7.9.2 MibSPI Transmit and Receive RAM Organization
      3. 7.9.3 MibSPI Transmit Trigger Events
        1. 7.9.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.9.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.9.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.9.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.9.5 SPI Slave Mode I/O Timings
  8. 8Device and Documentation Support
    1. 8.1  Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2  Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
    3. 8.3  Related Links
    4. 8.4  Community Resources
    5. 8.5  Trademarks
    6. 8.6  Electrostatic Discharge Caution
    7. 8.7  Glossary
    8. 8.8  Device Identification Code Register
    9. 8.9  Die Identification Registers
    10. 8.10 Module Certifications
      1. 8.10.1 DCAN Certification
      2. 8.10.2 LIN Certification
        1. 8.10.2.1 LIN Master Mode
        2. 8.10.2.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.10.2.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZWT|337
  • PGE|144
サーマルパッド・メカニカル・データ
発注情報

4 Terminal Configuration and Functions

PGE QFP Package Pinout (144-Pin)

TMS570LS3134 TMS570LS2134 TMS570LS2124 PGE_144_f4_spns160.gif
A. Pins can have multiplexed functions. Only the default function is depicted in the figure.
Figure 4-1 PGE QFP Package Pinout (144-Pin)(A)

4.1 ZWT BGA Package Ball-Map (337-Ball Grid Array)

TMS570LS3134 TMS570LS2134 TMS570LS2124 337ZWT_automotive_ball_map_no_flexray_f4.gif
A. Balls can have multiplexed functions. Only the default function, except for the EMIF signals that are multiplexed with ETM signals, is depicted in the figure.
Figure 4-2 ZWT Package Pinout. Top View(A)

4.2 Terminal Functions

Section 4.2.1 and Section 4.2.2identify the external signal names, the associated pin or ball numbers along with the mechanical package designator, the pin or ball type (Input, Output, I/O, Power, or Ground), whether the pin or ball has any internal pullup or pulldown, whether the pin or ball can be configured as a GPIO, and a functional pin or ball description. The first signal name listed is the primary function for that terminal. The signal name in bold is the function being described. For information on how to select between different multiplexed functions, see the TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU499) .

NOTE

In the Terminal Functions table below, the "Reset Pull State" is the state of the pull applied to the terminal while nPORRST is low and immediately after nPORRST goes High. The default pull direction may change when software configures the pin for an alternate function. The "Pull Type" is the type of pull asserted when the signal name in bold is enabled for the given terminal by the IOMM control registers.


All I/O signals except nRST are configured as inputs while nPORRST is low and immediately after nPORRST goes High. While nPORRST is low, the input buffers are disabled, and the output buffers are disabled with the default pulls enabled.


All output-only signals have the output buffer disabled and the default pull enabled while nPORRST is low, and are configured as outputs with the pulls disabled immediately after nPORRST goes High.

4.2.1 PGE Package

4.2.1.1 Multibuffered Analog-to-Digital Converters (MibADCs)

Table 4-1 PGE Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
ADREFHI(1) 66 Input N/A None ADC high reference supply
ADREFLO(1) 67 Input ADC low reference supply
VCCAD(1) 69 Power Operating supply for ADC
VSSAD(1) 68 Ground
AD1EVT 86 I/O Pulldown Programmable, 20 µA ADC1 event trigger input, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup Programmable, 20 µA ADC2 event trigger input, or GPIO
AD1IN[0] 60 Input N/A None ADC1 analog input
AD1IN[1] 71
AD1IN[2] 73
AD1IN[3] 74
AD1IN[4] 76
AD1IN[5] 78
AD1IN[6] 80
AD1IN[7] 61
AD1IN[8] / AD2IN[8] 83 Input N/A None ADC1/ADC2 shared analog inputs
AD1IN[9] / AD2IN[9] 70
AD1IN[10] / AD2IN[10] 72
AD1IN[11] / AD2IN[11] 75
AD1IN[12] / AD2IN[12] 77
AD1IN[13] / AD2IN[13] 79
AD1IN[14] / AD2IN[14] 82
AD1IN[15] / AD2IN[15] 85
AD1IN[16] / AD2IN[0] 58
AD1IN[17] / AD2IN[1] 59
AD1IN[18] / AD2IN[2] 62
AD1IN[19] / AD2IN[3] 63
AD1IN[20] / AD2IN[4] 64
AD1IN[21] / AD2IN[5] 65
AD1IN[22] / AD2IN[6] 81
AD1IN[23] / AD2IN[7] 84
(1) The ADREFHI, ADREFLO, VCCAD, and VSSAD connections are common for both ADC cores.

4.2.1.2 Enhanced Next Generation High-End Timer (N2HET) Modules

Table 4-2 PGE Enhanced Next Generation High-End Timer Modules (N2HET1, N2HET2)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
N2HET1[0]/SPI4CLK 25 I/O Pulldown Programmable, 20 µA N2HET1 timer input capture or output compare, or GIO.

Each terminal has a suppression filter with a programmable duration.
N2HET1[1]/SPI4NENA/N2HET2[8] 23
N2HET1[2]/SPI4SIMO[0] 30
N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24
N2HET1[4] 36
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31
N2HET1[6]/SCIRX 38
N2HET1[7]/N2HET2[14] 33
N2HET1[8]/MIBSPI1SIMO[1] 106
N2HET1[9]/N2HET2[16] 35
N2HET1[10] 118
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6
N2HET1[12] 124
N2HET1[13]/SCITX 39
N2HET1[14] 125
N2HET1[15]/MIBSPI1NCS[4] 41
N2HET1[16] 139
MIBSPI1NCS[1]/N2HET1[17] 130 I/O Pullup Programmable, 20 µA
N2HET1[18] 140 I/O Pulldown Programmable, 20 µA
MIBSPI1NCS[2]/N2HET1[19] 40 I/O Pullup Programmable, 20 µA
N2HET1[20] 141 I/O Pulldown Programmable, 20 µA
N2HET1[22] 15 I/O Pulldown Programmable, 20 µA
MIBSPI1NENA/N2HET1[23] 96 I/O Pullup Programmable, 20 µA
N2HET1[24]/MIBSPI1NCS[5] 91 I/O Pulldown Programmable, 20 µA
MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37 I/O Pullup Programmable, 20 µA
N2HET1[26] 92 I/O Pulldown Programmable, 20 µA
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 I/O Pullup Programmable, 20 µA
N2HET1[28] 107 I/O Pulldown Programmable, 20 µA
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 I/O Pullup Programmable, 20 µA
N2HET1[30] 127 I/O Pulldown Programmable, 20 µA
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 I/O Pullup Programmable, 20 µA
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14 I/O Pulldown Programmable, 20 µA Disable selected PWM outputs
GIOA[2]/N2HET2[0] 9 I/O Pulldown Programmable, 20 µA N2HET2 time input capture or output compare, or GPIO

Each terminal has a suppression filter with a programmable duration.
GIOA[6]/N2HET2[4] 16
GIOA[7]/N2HET2[6] 22
N2HET1[1]/SPI4NENA/N2HET2[8] 23
N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31
N2HET1[7]/N2HET2[14] 33
N2HET1[9]/N2HET2[16] 35
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 I/O Pullup Programmable, 20 µA Disable selected PWM outputs

4.2.1.3 General-Purpose Input/Output (GPIO)

Table 4-3 PGE General-Purpose Input/Output (GPIO)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
GIOA[0] 2 I/O Pulldown Programmable, 20 µA General-purpose I/O.
All GPIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges.
GIOA[1] 5
GIOA[2]/N2HET2[0] 9
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14
GIOA[6]/N2HET2[4] 16
GIOA[7]/N2HET2[6] 22
GIOB[0] 126
GIOB[1] 133
GIOB[2]/N2HET1_PIN_nDIS 142
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55(1) Pullup
GIOB[3] 1 Pulldown
(1) The application cannot output a level onto this terminal when it is configured as GIOB[2]. A pullup is enabled on this input. This pull cannot be disabled, and is not programmable using the GIO module pull control registers.

4.2.1.4 Controller Area Network Controllers (DCANs)

Table 4-4 PGE Controller Area Network Controllers (DCAN)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
CAN1RX 90 I/O Pullup Programmable, 20 µA CAN1 receive, or GPIO
CAN1TX 89 CAN1 transmit, or GPIO
CAN2RX 129 CAN2 receive, or GPIO
CAN2TX 128 CAN2 transmit, or GPIO
CAN3RX 12 CAN3 receive, or GPIO
CAN3TX 13 CAN3 transmit, or GPIO

4.2.1.5 Local Interconnect Network Interface Module (LIN)

Table 4-5 PGE Local Interconnect Network Interface Module (LIN)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
LINRX 131 I/O Pullup Programmable, 20 µA LIN receive, or GPIO
LINTX 132 LIN transmit, or GPIO

4.2.1.6 Standard Serial Communication Interface (SCI)

Table 4-6 PGE Standard Serial Communication Interface (SCI)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
N2HET1[6]/SCIRX 38 I/O Pulldown Programmable, 20 µA SCI receive, or GPIO
N2HET1[13]/SCITX 39 SCI transmit, or GPIO

4.2.1.7 Inter-Integrated Circuit Interface Module (I2C)

Table 4-7 PGE Inter-Integrated Circuit Interface Module (I2C)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4 I/O Pullup Programmable, 20 µA I2C serial data, or GPIO
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3 I2C serial clock, or GPIO

4.2.1.8 Standard Serial Peripheral Interface (SPI)

Table 4-8 PGE Standard Serial Peripheral Interface (SPI)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
N2HET1[0]/SPI4CLK 25 I/O Pulldown Programmable, 20 µA SPI4 clock, or GPIO
N2HET1[3]/SPI4NCS[0]/N2HET2[10] 24 SPI4 chip select, or GPIO
N2HET1[1]/SPI4NENA/N2HET2[8] 23 SPI4 enable, or GPIO
N2HET1[2]/SPI4SIMO[0] 30 SPI4 slave-input master-output, or GPIO
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] 31 SPI4 slave-output master-input, or GPIO

4.2.1.9 Multibuffered Serial Peripheral Interface Modules (MibSPI)

Table 4-9 PGE Multibuffered Serial Peripheral Interface Modules (MibSPI)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
MIBSPI1CLK 95 I/O Pullup Programmable, 20 µA MibSPI1 clock, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1] 105 MibSPI1 chip select, or GPIO
MIBSPI1NCS[1]/N2HET1[17] 130
MIBSPI1NCS[2]/N2HET1[19] 40
N2HET1[15]/MIBSPI1NCS[4] 41 Pulldown Programmable, 20 µA MibSPI1 chip select, or GPIO
N2HET1[24]/MIBSPI1NCS[5] 91
MIBSPI1NENA/N2HET1[23] 96 Pullup Programmable, 20 µA MibSPI1 enable, or GPIO
MIBSPI1SIMO[0] 93 MibSPI1 slave-in master-out, or GPIO
N2HET1[8]/MIBSPI1SIMO[1] 106 Pulldown Programmable, 20 µA MibSPI1 slave-in master-out, or GPIO
MIBSPI1SOMI[0] 94 Pullup Programmable, 20 µA MibSPI1 slave-out master-in, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1] 105
MIBSPI3CLK 53 I/O Pullup Programmable, 20 µA MibSPI3 clock, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS 55 MibSPI3 chip select, or GPIO
MIBSPI3NCS[1]/N2HET1[25]/MDCLK 37
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] 4
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] 3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] 6 Pulldown Programmable, 20 µA MibSPI3 chip select, or GPIO
MIBSPI3NENA /MIBSPI3NCS[5]/N2HET1[31] 54 Pullup Programmable, 20 µA MibSPI3 chip select, or GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] 54 MibSPI3 enable, or GPIO
MIBSPI3SIMO[0] 52 MibSPI3 slave-in master-out, or GPIO
MIBSPI3SOMI[0] 51 MibSPI3 slave-out master-in, or GPIO
MIBSPI5CLK 100 I/O Pullup Programmable, 20 µA MibSPI5 clock, or GPIO
MIBSPI5NCS[0] 32 MibSPI5 chip select, or GPIO
MIBSPI5NENA 97 MibSPI5 enable, or GPIO
MIBSPI5SIMO[0] 99 MibSPI5 slave-in master-out, or GPIO
MIBSPI5SOMI[0] 98 MibSPI5 slave-out master-in, or GPIO

4.2.1.10 System Module Interface

Table 4-10 PGE System Module Interface

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
nPORRST 46 Input Pulldown Fixed 100-µA
Pulldown		 Power-on reset, cold reset
External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter.
See Section 6.8.
nRST 116 I/O Pullup Fixed 100-µA
Pullup		 System reset, warm reset, bidirectional.
The internal circuitry indicates any reset condition by driving nRST low.
The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. See Section 6.8.
nERROR 117 I/O Pulldown Fixed 20-µA
Pulldown		 ESM Error Signal
Indicates error of high severity. See Section 6.18.

4.2.1.11 Clock Inputs and Outputs

Table 4-11 PGE Clock Inputs and Outputs

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
OSCIN 18 Input N/A None From external crystal/resonator, or external clock input
KELVIN_GND 19 Input Kelvin ground for oscillator
OSCOUT 20 Output To external crystal/resonator
ECLK 119 I/O Pulldown Programmable, 20  µA External prescaled clock output, or GIO.
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS 14 Input Pulldown 20 µA External clock input #1

4.2.1.12 Test and Debug Modules Interface

Table 4-12 PGE Test and Debug Modules Interface

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
TEST 34 I/O Pulldown Fixed 100-µA
Pulldown		 Test enable. This terminal must be connected to ground directly or through a pulldown resistor.
nTRST 109 Input JTAG test hardware reset
RTCK 113 Output N/A None JTAG return test clock
TCK 112 Input Pulldown Fixed 100-µA
Pulldown		 JTAG test clock
TDI 110 I/O Pullup Fixed 100-µA
Pullup		 JTAG test data in
TDO 111 Output 100 µA Pulldown None JTAG test data out
TMS 108 I/O Pullup Fixed 100-µA
Pullup		 JTAG test select

4.2.1.13 Flash Supply and Test Pads

Table 4-13 PGE Flash Supply and Test Pads

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
VCCP 134 3.3-V Power N/A None Flash pump supply
FLTP1 7 N/A None Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)].
FLTP2 8

4.2.1.14 Supply for Core Logic: 1.2-V Nominal

Table 4-14 PGE Supply for Core Logic: 1.2-V Nominal

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
VCC 17 1.2-V Power N/A None 1.2-V Core supply
VCC 29
VCC 45
VCC 48
VCC 49
VCC 57
VCC 87
VCC 101
VCC 114
VCC 123
VCC 137
VCC 143

4.2.1.15 Supply for I/O Cells: 3.3-V Nominal

Table 4-15 PGE Supply for I/O Cells: 3.3-V Nominal

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
VCCIO 10 3.3-V Power N/A None 3.3-V Operating supply for I/Os
VCCIO 26
VCCIO 42
VCCIO 104
VCCIO 120
VCCIO 136

4.2.1.16 Ground Reference for All Supplies Except VCCAD

Table 4-16 PGE Ground Reference for All Supplies Except VCCAD

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 144 PGE
VSS 11 Ground N/A None Ground reference
VSS 21
VSS 27
VSS 28
VSS 43
VSS 44
VSS 47
VSS 50
VSS 56
VSS 88
VSS 102
VSS 103
VSS 115
VSS 121
VSS 122
VSS 135
VSS 138
VSS 144

4.2.2 ZWT Package

4.2.2.1 Multibuffered Analog-to-Digital Converters (MibADCs)

Table 4-17 ZWT Multibuffered Analog-to-Digital Converters (MibADC1, MibADC2)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
ADREFHI(1) V15 Input N/A None ADC high reference supply
ADREFLO(1) V16 Input ADC low reference supply
VCCAD(1) W15 Power Operating supply for ADC
VSSAD V19 Ground N/A None ADC supply power
VSSAD W16
VSSAD W18
VSSAD W19
AD1EVT N19 I/O Pulldown Programmable, 20 µA ADC1 event trigger input, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 I/O Pullup Programmable, 20 µA ADC2 event trigger input, or GPIO
AD1IN[0] W14 Input N/A None ADC1 analog input
AD1IN[1] V17
AD1IN[2] V18
AD1IN[3] T17
AD1IN[4] U18
AD1IN[5] R17
AD1IN[6] T19
AD1IN[7] V14
AD1IN[8] / AD2IN[8] P18 Input N/A None ADC1/ADC2 shared analog inputs
AD1IN[9] / AD2IN[9] W17
AD1IN[10] / AD2IN[10] U17
AD1IN[11] / AD2IN[11] U19
AD1IN[12] / AD2IN[12] T16
AD1IN[13] / AD2IN[13] T18
AD1IN[14] / AD2IN[14] R18
AD1IN[15] / AD2IN[15] P19
AD1IN[16] / AD2IN[0] V13
AD1IN[17] / AD2IN[1] U13
AD1IN[18] / AD2IN[2] U14
AD1IN[19] / AD2IN[3] U16
AD1IN[20] / AD2IN[4] U15
AD1IN[21] / AD2IN[5] T15
AD1IN[22] / AD2IN[6] R19
AD1IN[23] / AD2IN[7] R16
(1) The ADREFHI, ADREFLO, VCCAD, and VSSAD connections are common for both ADC cores.

4.2.2.2 Enhanced Next Generation High-End Timer (N2HET) Modules

Table 4-18 ZWT Enhanced Next Generation High-End Timer (N2HET) Modules

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
N2HET1[0]/SPI4CLK K18 I/O Pulldown Programmable, 20 µA N2HET1 time input capture or output compare, or GIO.

Each terminal has a suppression filter with a programmable duration.
N2HET1[1]/SPI4NENA/N2HET2[8] V2
N2HET1[2]/SPI4SIMO[0] W5
N2HET1[3]/SPI4NCS[0]/N2HET2[10] U1
N2HET1[4] B12
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] V6
N2HET1[6]/SCIRX W3
N2HET1[7]/N2HET2[14] T1
N2HET1[8]/MIBSPI1SIMO[1] E18
N2HET1[9]/N2HET2[16] V7
N2HET1[10] D19
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3
N2HET1[12] B4
N2HET1[13]/SCITX N2
N2HET1[14] A11
N2HET1[15]/MIBSPI1NCS[4] N1
N2HET1[16] A4
N2HET1[17] A13
MIBSPI1NCS[1]/N2HET1[17] F3
N2HET1[18] J1
N2HET1[19] B13
MIBSPI1NCS[2]/N2HET1[19] G3
N2HET1[20] P2
N2HET1[21] H4
MIBSPI1NCS[3]/N2HET1[21] J3
N2HET1[22] B3
N2HET1[23] J4
MIBSPI1NENA/N2HET1[23] G19
N2HET1[24]/MIBSPI1NCS[5] P1
N2HET1[25] M3
MIBSPI3NCS[1]/N2HET1[25] V5
N2HET1[26] A14
N2HET1[27] A9
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] B2
N2HET1[28] K19
N2HET1[29] A3
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] C3
N2HET1[30] B11
N2HET1[31] J17
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] W9
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS B5 I/O Pulldown Programmable, 20 µA Disable selected PWM outputs
GIOA[2]/N2HET2[0] C1 I/O Pulldown Programmable, 20 µA N2HET2 time input capture or output compare, or GIO.

Each terminal has a suppression filter with a programmable duration.
EMIF_ADDR[0]/N2HET2[1] D4
GIOA[3]/N2HET2[2] E1
EMIF_ADDR[1]/N2HET2[3] D5
GIOA[6]/N2HET2[4] H3
EMIF_BA[1]/N2HET2[5] D16
GIOA[7]/N2HET2[6] M1
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17
N2HET1[1]/SPI4NENA/N2HET2[8] V2
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17
N2HET1[3]/SPI4NCS[0]/N2HET2[10] U1
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] V6
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5
N2HET1[7]/N2HET2[14] T1
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6
N2HET1[9]/N2HET2[16] V7
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 I/O Pullup Programmable, 20 µA Disable selected PWM outputs

4.2.2.3 General-Purpose Input/Output (GPIO)

Table 4-19 ZWT General-Purpose Input/Output (GPIO)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
GIOA[0] A5 I/O Pulldown Programmable, 20 µA General-purpose I/O.
All GPIO terminals are capable of generating interrupts to the CPU on rising / falling / both edges.
GIOA[1] C2
GIOA[2]/N2HET2[0] C1
GIOA[3]/N2HET2[2] E1
GIOA[4] A6
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS B5
GIOA[6]/N2HET2[4] H3
GIOA[7]/N2HET2[6] M1
GIOB[0] M2
GIOB[1] K2
GIOB[2] F2
GIOB[3] W10
GIOB[4] G1
GIOB[5] G2
GIOB[6] J2
GIOB[7] F1
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 Pullup Fixed 20 µA Pulldown The application cannot output a level onto this terminal when it is configured as GIOB[2]. A pullup is enabled on this input. This pull cannot be disabled, and is not programmable using the GIO module pull control registers

4.2.2.4 Controller Area Network Controllers (DCANs)

Table 4-20 ZWT Controller Area Network Controllers (DCANs)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
CAN1RX B10 I/O Pullup Programmable, 20 µA CAN1 receive, or GPIO
CAN1TX A10 CAN1 transmit, or GPIO
CAN2RX H1 CAN2 receive, or GPIO
CAN2TX H2 CAN2 transmit, or GPIO
CAN3RX M19 CAN3 receive, or GPIO
CAN3TX M18 CAN3 transmit, or GPIO

4.2.2.5 Local Interconnect Network Interface Module (LIN)

Table 4-21 ZWT Local Interconnect Network Interface Module (LIN)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
LINRX A7 I/O Pullup Programmable, 20 µA LIN receive, or GPIO
LINTX B7 LIN transmit, or GPIO

4.2.2.6 Standard Serial Communication Interface (SCI)

Table 4-22 ZWT Standard Serial Communication Interface (SCI)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
N2HET1[6]/SCIRX W3 I/O Pulldown Programmable, 20 µA SCI receive, or GPIO
N2HET1[13]/SCITX N2 SCI transmit, or GPIO

4.2.2.7 Inter-Integrated Circuit Interface Module (I2C)

Table 4-23 ZWT Inter-Integrated Circuit Interface Module (I2C)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] B2 I/O Pullup Programmable, 20 µA I2C serial data, or GPIO
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] C3 I2C serial clock, or GPIO

4.2.2.8 Standard Serial Peripheral Interface (SPI)

Table 4-24 ZWT Standard Serial Peripheral Interface (SPI)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
SPI2CLK E2 I/O Pullup Programmable, 20 µA SPI2 clock, or GPIO
SPI2NCS[0] N3 SPI2 chip select, or GPIO
SPI2NENA/SPI2NCS[1] D3 SPI2 chip select, or GPIO
SPI2NENA/SPI2NCS[1] D3 SPI2 enable, or GPIO
SPI2SIMO[0] D1 SPI2 slave-input master-output, or GPIO
SPI2SOMI[0] D2 SPI2 slave-output master-input, or GPIO
N2HET1[0]/SPI4CLK K18 I/O Pulldown Programmable, 20 µA SPI4 clock, or GPIO
N2HET1[3]/SPI4NCS[0]/N2HET2[10] U1 SPI4 chip select, or GPIO
N2HET1[1]/SPI4NENA/N2HET2[8] V2 SPI4 enable, or GPIO
N2HET1[2]/SPI4SIMO[0] W5 SPI4 slave-input master-output, or GPIO
N2HET1[5]/SPI4SOMI[0]/N2HET2[12] V6 SPI4 slave-output master-input, or GPIO

4.2.2.9 Multibuffered Serial Peripheral Interface Modules (MibSPI)

Table 4-25 ZWT Multibuffered Serial Peripheral Interface Modules (MibSPI)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
MIBSPI1CLK F18 I/O Pullup Programmable, 20 µA MibSPI1 clock, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1] R2 MibSPI1 chip select, or GPIO
MIBSPI1NCS[1]/N2HET1[17] F3
MIBSPI1NCS[2]/N2HET1[19] G3
MIBSPI1NCS[3]/N2HET1[21] J3
N2HET1[15]/MIBSPI1NCS[4] N1 Pulldown Programmable, 20 µA MibSPI1 chip select, or GPIO
N2HET1[24]/MIBSPI1NCS[5] P1
MIBSPI1NENA/N2HET1[23] G19 Pullup Programmable, 20 µA MibSPI1 enable, or GPIO
MIBSPI1SIMO[0] F19 MibSPI1 slave-in master-out, or GPIO
N2HET1[8]/MIBSPI1SIMO[1] E18 Pulldown Programmable, 20 µA MibSPI1 slave-in master-out, or GPIO
MIBSPI1SOMI[0] G18 Pullup Programmable, 20 µA MibSPI1 slave-out master-in, or GPIO
MIBSPI1NCS[0]/MIBSPI1SOMI[1] R2
MIBSPI3CLK V9 I/O Pullup Programmable, 20 µA MibSPI3 clock, or GPIO
MIBSPI3NCS[0]/AD2EVT/GIOB[2]/N2HET2_PIN_nDIS V10 MibSPI3 chip select, or GPIO
MIBSPI3NCS[1]/N2HET1[25]/MDCLK V5
MIBSPI3NCS[2]/I2C_SDA/N2HET1[27] B2
MIBSPI3NCS[3]/I2C_SCL/N2HET1[29] C3
N2HET1[11]/MIBSPI3NCS[4]/N2HET2[18] E3 Pulldown Programmable, 20 µA MibSPI3 chip select, or GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] W9 Pullup Programmable, 20 µA MibSPI3 chip select, or GPIO
MIBSPI3NENA/MIBSPI3NCS[5]/N2HET1[31] W9 MibSPI3 enable, or GPIO
MIBSPI3SIMO[0] W8 MibSPI3 slave-in master-out, or GPIO
MIBSPI3SOMI[0] V8 MibSPI3 slave-out master-in, or GPIO
MIBSPI5CLK/DMM_DATA[4] H19 I/O Pullup Programmable, 20 µA MibSPI5 clock, or GPIO
MIBSPI5NCS[0]/DMM_DATA[5] E19 MibSPI5 chip select, or GPIO
MIBSPI5NCS[1]/DMM_DATA[6] B6
MIBSPI5NCS[2]/DMM_DATA[2] W6
MIBSPI5NCS[3]/DMM_DATA[3] T12
MIBSPI5NENA/DMM_DATA[7] H18 MibSPI5 enable, or GPIO
MIBSPI5SIMO[0]/DMM_DATA[8] J19 MibSPI5 slave-in master-out, or GPIO
MIBSPI5SIMO[1]/DMM_DATA[9] E16
MIBSPI5SIMO[2]/DMM_DATA[10] H17
MIBSPI5SIMO[3]/DMM_DATA[11] G17
MIBSPI5SOMI[0]/DMM_DATA[12] J18
MIBSPI5SOMI[1]/DMM_DATA[13] E17
MIBSPI5SOMI[2]/DMM_DATA[14] H16
MIBSPI5SOMI[3]/DMM_DATA[15] G16

4.2.2.10 External Memory Interface (EMIF)

Table 4-26 External Memory Interface (EMIF)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
EMIF_CKE L3 Output Pulldown None EMIF Clock Enable
EMIF_CLK K3 I/O None EMIF clock. This is an output signal in functional mode. It is gated off by default, so that the signal is tri-stated. PINMUX29[8] must be cleared to enable this output.
ETMDATA[13]/EMIF_nOE E12 Pulldown None EMIF Output Enable
EMIF_nWAIT P3 I/O Pullup Fixed 20-µA
Pullup		 EMIF Extended Wait Signal
EMIF_nWE D17 Output Pullup None EMIF Write Enable.
EMIF_nCAS R4 Output EMIF column address strobe
EMIF_nRAS R3 Output EMIF row address strobe
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17 Output Pulldown EMIF chip select, SDRAM
EMIF_nCS[2] L17 Output Pullup EMIF chip selects, asynchronous
This applies to chip selects 2, 3, and 4
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17 Output Pulldown
EMIF_nCS[4]/RTP_DATA[7] M17 Output Pullup
ETMDATA[15]/EMIF_nDQM[0] E10 Output Pulldown EMIF Data Mask or Write Strobe.
Data mask for SDRAM devices, write strobe for connected asynchronous devices.
ETMDATA[14]/EMIF_nDQM[1] E11 Output
ETMDATA[12]/EMIF_BA[0] E13 Output EMIF bank address or address line
EMIF_BA[1]/N2HET2[5] D16 Output EMIF bank address or address line
EMIF_ADDR[0]/N2HET2[1] D4 Output EMIF address
EMIF_ADDR[1]/N2HET2[3] D5 Output
ETMDATA[11]/EMIF_ADDR[2] E6 Output
ETMDATA[10]/EMIF_ADDR[3] E7 Output
ETMDATA[9]/EMIF_ADDR[4] E8 Output
ETMDATA[8]/EMIF_ADDR[5] E9 Output
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4 Output
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5 Output
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6 Output
EMIF_ADDR[9]/RTP_DATA[10] C7 Output
EMIF_ADDR[10]/RTP_DATA[9] C8 Output
EMIF_ADDR[11]/RTP_DATA[8] C9 Output
EMIF_ADDR[12]/RTP_DATA[6] C10 Output
EMIF_ADDR[13]/RTP_DATA[5] C11 Output
EMIF_ADDR[14]/RTP_DATA[4] C12 Output
EMIF_ADDR[15]/RTP_DATA[3] C13 Output
EMIF_ADDR[16]/RTP_DATA[2] D14 Output
EMIF_ADDR[17]/RTP_DATA[1] C14 Output Pulldown
EMIF_ADDR[18]/RTP_DATA[0] D15 Output
EMIF_ADDR[19]/RTP_nENA C15 Output
EMIF_ADDR[20]/RTP_nSYNC C16 Output
EMIF_ADDR[21]/RTP_CLK C17 Output
ETMDATA[16]/EMIF_DATA[0] K15 I/O Pulldown Fixed 20-µA
Pullup		 EMIF Data
ETMDATA[17]/EMIF_DATA[1] L15 I/O
ETMDATA[18]/EMIF_DATA[2] M15 I/O
ETMDATA[19]/EMIF_DATA[3] N15 I/O
ETMDATA[20]/EMIF_DATA[4] E5 I/O
ETMDATA[21]/EMIF_DATA[5] F5 I/O
ETMDATA[22]/EMIF_DATA[6] G5 I/O
ETMDATA[23]/EMIF_DATA[7] K5 I/O
ETMDATA[24]/EMIF_DATA[8] L5 I/O
ETMDATA[25]/EMIF_DATA[9] M5 I/O
ETMDATA[26]/EMIF_DATA[10] N5 I/O
ETMDATA[27]/EMIF_DATA[11] P5 I/O
ETMDATA[28]/EMIF_DATA[12] R5 I/O
ETMDATA[29]/EMIF_DATA[13] R6 I/O
ETMDATA[30]/EMIF_DATA[14] R7 I/O
ETMDATA[31]/EMIF_DATA[15] R8 I/O

4.2.2.11 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)

Table 4-27 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
ETMTRACECLKIN/EXTCLKIN2 R9 Input Pulldown Fixed 20-µA
Pullup		 ETM Trace Clock Input
ETMTRACECLKOUT R10 Output Pulldown None ETM Trace Clock Output
ETMTRACECTL R11 ETM trace control
ETMDATA[0] R12 ETM data
ETMDATA[1] R13
ETMDATA[2] J15
ETMDATA[3] H15
ETMDATA[4] G15
ETMDATA[5] F15
ETMDATA[6] E15
ETMDATA[7] E14
ETMDATA[8]/EMIF_ADDR[5] E9
ETMDATA[9]/EMIF_ADDR[4] E8
ETMDATA[10]/EMIF_ADDR[3] E7
ETMDATA[11]/EMIF_ADDR[2] E6
ETMDATA[12]/EMIF_BA[0] E13
ETMDATA[13]/EMIF_nOE E12
ETMDATA[14]/EMIF_nDQM[1] E11
ETMDATA[15]/EMIF_nDQM[0] E10
ETMDATA[16]/EMIF_DATA[0] K15
ETMDATA[17]/EMIF_DATA[1] L15
ETMDATA[18]/EMIF_DATA[2] M15
ETMDATA[19]/EMIF_DATA[3] N15
ETMDATA[20]/EMIF_DATA[4] E5
ETMDATA[21]/EMIF_DATA[5] F5
ETMDATA[22]/EMIF_DATA[6] G5
ETMDATA[23]/EMIF_DATA[7] K5
ETMDATA[24]/EMIF_DATA[8] L5
ETMDATA[25]/EMIF_DATA[9] M5
ETMDATA[26]/EMIF_DATA[10] N5
ETMDATA[27]/EMIF_DATA[11] P5
ETMDATA[28]/EMIF_DATA[12] R5
ETMDATA[29]/EMIF_DATA[13] R6
ETMDATA[30]/EMIF_DATA[14] R7
ETMDATA[31]/EMIF_DATA[15] R8

4.2.2.12 RAM Trace Port (RTP)

Table 4-28 RAM Trace Port (RTP)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
EMIF_ADDR[21]/RTP_CLK C17 I/O Pulldown Programmable, 20 µA RTP packet clock, or GPIO
EMIF_ADDR[19]/RTP_nENA C15 I/O RTP packet handshake, or GPIO
EMIF_ADDR[20]/RTP_nSYNC C16 I/O RTP synchronization, or GPIO
EMIF_ADDR[18]/RTP_DATA[0] D15 I/O RTP packet data, or GPIO
EMIF_ADDR[17]/RTP_DATA[1] C14
EMIF_ADDR[16]/RTP_DATA[2] D14
EMIF_ADDR[15]/RTP_DATA[3] C13
EMIF_ADDR[14]/RTP_DATA[4] C12
EMIF_ADDR[13]/RTP_DATA[5] C11
EMIF_ADDR[12]/RTP_DATA[6] C10
EMIF_nCS[4]/RTP_DATA[7] M17 Pullup Programmable, 20 µA
EMIF_ADDR[11]/RTP_DATA[8] C9 Pulldown Programmable, 20 µA
EMIF_ADDR[10]/RTP_DATA[9] C8
EMIF_ADDR[9]/RTP_DATA[10] C7
EMIF_ADDR[8]/RTP_DATA[11]/N2HET2[15] C6
EMIF_ADDR[7]/RTP_DATA[12]/N2HET2[13] C5
EMIF_ADDR[6]/RTP_DATA[13]/N2HET2[11] C4
EMIF_nCS[0]/RTP_DATA[15]/N2HET2[7] N17
EMIF_nCS[3]/RTP_DATA[14]/N2HET2[9] K17

4.2.2.13 Data Modification Module (DMM)

Table 4-29 Data Modification Module (DMM)

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
DMM_CLK F17 I/O Pullup Programmable, 20 µA DMM clock, or GPIO
DMM_nENA F16 DMM handshake, or GPIO
DMM_SYNC J16 DMM synchronization, or GPIO
DMM_DATA[0] L19 DMM data, or GPIO
DMM_DATA[1] L18
MIBSPI5NCS[2]/DMM_DATA[2] W6
MIBSPI5NCS[3]/DMM_DATA[3] T12
MIBSPI5CLK/DMM_DATA[4] H19
MIBSPI5NCS[0]/DMM_DATA[5] E19
MIBSPI5NCS[1]/DMM_DATA[6] B6
MIBSPI5NENA/DMM_DATA[7] H18
MIBSPI5SIMO[0]/DMM_DATA[8] J19
MIBSPI5SIMO[1]/DMM_DATA[9] E16
MIBSPI5SIMO[2]/DMM_DATA[10] H17
MIBSPI5SIMO[3]/DMM_DATA[11] G17
MIBSPI5SOMI[0]/DMM_DATA[12] J18
MIBSPI5SOMI[1]/DMM_DATA[13] E17
MIBSPI5SOMI[2]/DMM_DATA[14] H16
MIBSPI5SOMI[3]/DMM_DATA[15] G16

4.2.2.14 System Module Interface

Table 4-30 ZWT System Module Interface

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
nPORRST W7 Input Pulldown Fixed 100-µA
Pulldown		 Power-on reset, cold reset
External power supply monitor circuitry must drive nPORRST low when any of the supplies to the microcontroller fall out of the specified range. This terminal has a glitch filter.
See Section 6.8.
nRST B17 I/O Pullup Fixed 100-µA
Pullup		 System reset, warm reset, bidirectional.
The internal circuitry indicates any reset condition by driving nRST low.
The external circuitry can assert a system reset by driving nRST low. To ensure that an external reset is not arbitrarily generated, TI recommends that an external pullup resistor is connected to this terminal.
This terminal has a glitch filter. See Section 6.8.
nERROR B14 I/O Pulldown Fixed 20-µA
Pulldown		 ESM Error Signal
Indicates error of high severity. See Section 6.18.

4.2.2.15 Clock Inputs and Outputs

Table 4-31 ZWT Clock Inputs and Outputs

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
OSCIN K1 Input N/A None From external crystal/resonator, or external clock input
KELVIN_GND L2 Input Kelvin ground for oscillator
OSCOUT L1 Output To external crystal/resonator
ECLK A12 I/O Pulldown Programmable, 20 µA External prescaled clock output, or GIO.
GIOA[5]/EXTCLKIN/N2HET1_PIN_nDIS B5 Input Pulldown Fixed 20-µA
Pulldown		 External clock input #1
ETMTRACECLKIN/EXTCLKIN2 R9 Input External clock input #2
VCCPLL P11 1.2-V Power N/A None Dedicated core supply for PLLs

4.2.2.16 Test and Debug Modules Interface

Table 4-32 ZWT Test and Debug Modules Interface

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
TEST U2 I/O Pulldown Fixed 100-µA
Pulldown		 Test enable. This terminal must be connected to ground directly or through a pulldown resistor.
nTRST D18 Input JTAG test hardware reset
RTCK A16 Output N/A None JTAG return test clock
TCK B18 Input Pulldown Fixed 100-µA
Pulldown		 JTAG test clock
TDI A17 I/O Pullup Fixed 100-µA
Pullup		 JTAG test data in
TDO C18 Output 100 µA Pulldown None JTAG test data out
TMS C19 I/O Pullup Fixed 100-µA
Pullup		 JTAG test select

4.2.2.17 Flash Supply and Test Pads

Table 4-33 ZWT Flash Supply and Test Pads

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
VCCP F8 3.3-V Power N/A None Flash pump supply
FLTP1 J5 – N/A None Flash test pads. These terminals are reserved for TI use only. For proper operation these terminals must connect only to a test pad or not be connected at all [no connect (NC)].
FLTP2 H5

4.2.2.18 Reserved

Table 4-34 Reserved

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
Reserved A15 – N/A None Reserved. These balls are connected to internal logic but are not outputs nor do they have internal pulls. They are subject to ±1 µA leakage current.
Reserved B15 – N/A None
Reserved B16 – N/A None
Reserved A8 – N/A None
Reserved B8 – N/A None
Reserved B9 – N/A None

4.2.2.19 No Connects

Table 4-35 No Connects

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
NC D6 – N/A None No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device.
NC D7 – N/A None
NC D8 – N/A None
NC D9 – N/A None
NC D10 – N/A None
NC D11 – N/A None
NC D12 – N/A None
NC D13 – N/A None
NC E4 – N/A None
NC F4 – N/A None
NC G4 – N/A None
NC K4 – N/A None
NC K16 – N/A None
NC L4 – N/A None
NC L16 – N/A None
NC M4 – N/A None
NC M16 – N/A None
NC N4 – N/A None
NC N16 – N/A None
NC N18 – N/A None
NC P4 – N/A None
NC P15 – N/A None
NC P16 – N/A None
NC P17 – N/A None
NC R1 – N/A None
NC R14 – N/A None
NC R15 – N/A None
NC T2 – N/A None
NC T3 – N/A None
NC T4 – N/A None
NC T5 – N/A None
NC T6 – N/A None
NC T7 – N/A None
NC T8 – N/A None
NC T9 – N/A None
NC T10 – N/A None
NC T11 – N/A None
NC T13 – N/A None
NC T14 – N/A None
NC U3 – N/A None
NC U4 – N/A None
NC U5 – N/A None No Connects. These balls are not connected to any internal logic and can be connected to the PCB ground without affecting the functionality of the device.
NC U6 – N/A None
NC U7 – N/A None
NC U8 – N/A None
NC U9 – N/A None
NC U10 – N/A None
NC U11 – N/A None
NC U12 – N/A None
NC V3 – N/A None
NC V4 – N/A None
NC V11 – N/A None
NC V12 – N/A None
NC W4 – N/A None
NC W11 – N/A None
NC W12 – N/A None
NC W13 – N/A None

4.2.2.20 Supply for Core Logic: 1.2-V Nominal

Table 4-36 ZWT Supply for Core Logic: 1.2-V Nominal

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
VCC F9 1.2-V Power N/A None Core supply
VCC F10
VCC H10
VCC J14
VCC K6
VCC K8
VCC K12
VCC K14
VCC L6
VCC M10
VCC P10

4.2.2.21 Supply for I/O Cells: 3.3-V Nominal

Table 4-37 ZWT Supply for I/O Cells: 3.3-V Nominal

TERMINAL SIGNAL TYPE RESET PULL STATE PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
VCCIO F6 3.3-V Power N/A None Operating supply for I/Os
VCCIO F7
VCCIO F11
VCCIO F12
VCCIO F13
VCCIO F14
VCCIO G6
VCCIO G14
VCCIO H6
VCCIO H14
VCCIO J6
VCCIO L14
VCCIO M6
VCCIO M14
VCCIO N6
VCCIO N14
VCCIO P6
VCCIO P7
VCCIO P8
VCCIO P9
VCCIO P12
VCCIO P13
VCCIO P14

4.2.2.22 Ground Reference for All Supplies Except VCCAD

Table 4-38 ZWT Ground Reference for All Supplies Except VCCAD

TERMINAL SIGNAL
TYPE		 RESET PULL
STATE		 PULL TYPE DESCRIPTION
SIGNAL NAME 337 ZWT
VSS A1 Ground N/A None Ground reference
VSS A2
VSS A18
VSS A19
VSS B1
VSS B19
VSS H8
VSS H9
VSS H11
VSS H12
VSS J8
VSS J9
VSS J10
VSS J11
VSS J12
VSS K9
VSS K10
VSS K11
VSS L8
VSS L9
VSS L10
VSS L11
VSS L12
VSS M8
VSS M9
VSS M11
VSS M12
VSS V1
VSS W1
VSS W2