SPNS164C April   2012  – April 2015 TMS570LS2125 , TMS570LS2135 , TMS570LS3135

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PGE QFP Package Pinout (144-Pin)
    2. 4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array)
    3. 4.3 Terminal Functions
      1. 4.3.1 PGE Package
        1. 4.3.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.3.1.2  Enhanced High-End Timer (N2HET) Modules
        3. 4.3.1.3  General-Purpose Input/Output (GPIO)
        4. 4.3.1.4  FlexRay Interface Controller (FlexRay)
        5. 4.3.1.5  Controller Area Network Controllers (DCANs)
        6. 4.3.1.6  Local Interconnect Network Interface Module (LIN)
        7. 4.3.1.7  Standard Serial Communication Interface (SCI)
        8. 4.3.1.8  Inter-Integrated Circuit Interface Module (I2C)
        9. 4.3.1.9  Standard Serial Peripheral Interface (SPI)
        10. 4.3.1.10 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        11. 4.3.1.11 System Module Interface
        12. 4.3.1.12 Clock Inputs and Outputs
        13. 4.3.1.13 Test and Debug Modules Interface
        14. 4.3.1.14 Flash Supply and Test Pads
        15. 4.3.1.15 Supply for Core Logic: 1.2-V Nominal
        16. 4.3.1.16 Supply for I/O Cells: 3.3-V Nominal
        17. 4.3.1.17 Ground Reference for All Supplies Except VCCAD
      2. 4.3.2 ZWT Package
        1. 4.3.2.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.3.2.2  Enhanced High-End Timer (N2HET) Modules
        3. 4.3.2.3  General-Purpose Input/Output (GPIO)
        4. 4.3.2.4  FlexRay Interface Controller (FlexRay)
        5. 4.3.2.5  Controller Area Network Controllers (DCANs)
        6. 4.3.2.6  Local Interconnect Network Interface Module (LIN)
        7. 4.3.2.7  Standard Serial Communication Interface (SCI)
        8. 4.3.2.8  Inter-Integrated Circuit Interface Module (I2C)
        9. 4.3.2.9  Standard Serial Peripheral Interface (SPI)
        10. 4.3.2.10 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        11. 4.3.2.11 External Memory Interface (EMIF)
        12. 4.3.2.12 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
        13. 4.3.2.13 RAM Trace Port (RTP)
        14. 4.3.2.14 Data Modification Module (DMM)
        15. 4.3.2.15 System Module Interface
        16. 4.3.2.16 Clock Inputs and Outputs
        17. 4.3.2.17 Test and Debug Modules Interface
        18. 4.3.2.18 Flash Supply and Test Pads
        19. 4.3.2.19 No Connects
        20. 4.3.2.20 Supply for Core Logic: 1.2-V Nominal
        21. 4.3.2.21 Supply for I/O Cells: 3.3-V Nominal
        22. 4.3.2.22 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Switching Characteristics for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption
    8. 5.8  Input/Output Electrical Characteristics
    9. 5.9  Thermal Resistance Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low Power Oscillator
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Master/Slave Access Privileges
        1. 6.9.3.1 Special Notes on Accesses to Certain Slaves
      4. 6.9.4 POM Overlay Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Flash Program and Erase Timings for Program Flash
      6. 6.10.6 Flash Program and Erase Timings for Data Flash
    11. 6.11 Tightly Coupled RAM (TCRAM) Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAM Interface ECC Support
    12. 6.12 Parity Protection for Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1  Block Diagram
      2. 6.21.2  Debug Components Memory Map
      3. 6.21.3  JTAG Identification Code
      4. 6.21.4  Debug ROM
      5. 6.21.5  JTAG Scan Interface Timings
      6. 6.21.6  Advanced JTAG Security Module
      7. 6.21.7  Embedded Trace Macrocell (ETM-R4)
        1. 6.21.7.1 ETM TRACECLKIN Selection
        2. 6.21.7.2 Timing Specifications
      8. 6.21.8  RAM Trace Port (RTP)
        1. 6.21.8.1 Features
        2. 6.21.8.2 Timing Specifications
      9. 6.21.9  Data Modification Module (DMM)
        1. 6.21.9.1 Features
        2. 6.21.9.2 Timing Specifications
      10. 6.21.10 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Peripheral Legend
    2. 7.2  Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 Default MIBADC1 Event Trigger Hookup
        2. 7.2.2.2 Alternate MIBADC1 Event Trigger Hookup
        3. 7.2.2.3 Default MIBADC2 Event Trigger Hookup
        4. 7.2.2.4 Alternate MIBADC2 Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3  General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4  Enhanced High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET1-N2HET2 Interconnections
      5. 7.4.5 N2HET Checking
        1. 7.4.5.1 Internal Monitoring
        2. 7.4.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.4.6 Disabling N2HET Outputs
      7. 7.4.7 High-End Timer Transfer Unit (HTU)
        1. 7.4.7.1 Features
        2. 7.4.7.2 Trigger Connections
    5. 7.5  FlexRay Interface
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
      3. 7.5.3 FlexRay Transfer Unit
    6. 7.6  Controller Area Network (DCAN)
      1. 7.6.1 Features
      2. 7.6.2 Electrical and Timing Specifications
    7. 7.7  Local Interconnect Network Interface (LIN)
      1. 7.7.1 LIN Features
    8. 7.8  Serial Communication Interface (SCI)
      1. 7.8.1 Features
    9. 7.9  Inter-Integrated Circuit (I2C)
      1. 7.9.1 Features
      2. 7.9.2 I2C I/O Timing Specifications
    10. 7.10 Multibuffered / Standard Serial Peripheral Interface
      1. 7.10.1 Features
      2. 7.10.2 MibSPI Transmit and Receive RAM Organization
      3. 7.10.3 MibSPI Transmit Trigger Events
        1. 7.10.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.10.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.10.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.10.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.10.5 SPI Slave Mode I/O Timings
  8. 8Device and Documentation Support
    1. 8.1  Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2  Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
    3. 8.3  Related Links
    4. 8.4  Community Resources
    5. 8.5  Trademarks
    6. 8.6  Electrostatic Discharge Caution
    7. 8.7  Glossary
    8. 8.8  Device Identification Code Register
    9. 8.9  Die Identification Registers
    10. 8.10 Module Certifications
      1. 8.10.1 FlexRay™ Certifications
      2. 8.10.2 DCAN Certification
      3. 8.10.3 LIN Certification
        1. 8.10.3.1 LIN Master Mode
        2. 8.10.3.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.10.3.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PGE|144
サーマルパッド・メカニカル・データ
発注情報

2 Revision History

This data manual revision history highlights the technical changes made to the SPNS164B device-specific data manual to make it an SPNS164C revision.

Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the TMS570LS31x5/21x5 devices, which are now in the production data (PD) stage of development have been incorporated.

Changes from August 1, 2013 to April 30, 2015 (from B Revision (July 2013) to C Revision)

  • Section 1 (Device Overview): Updated/Changed section title Go
  • Updated/Changed the N2HET featureGo
  • (Device Information): Added tableGo
  • Added Section 3, Device ComparisonGo
  • Section 4 (Terminal Configuration and Functions): Updated/Changed section titleGo
  • Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET1, N2HET2)): Updated/Changed N2HET1 time input capture or output compare pin descriptionGo
  • Table 4-2: Added N2HET1_PIN_nDIS signal DESCRIPTIONGo
  • Table 4-2: Updated/Changed N2HET2 time input capture or output compare pin descriptionGo
  • Table 4-2: Added N2HET2_PIN_nDIS signal DESCRIPTIONGo
  • Table 4-3 Updated description about using GIOB[2] on pin 55 Go
  • Table 4-13 (PGE Test and Debug Modules Interface): Updated/Changed TEST pin descriptionGo
  • Table 4-19 (ZWT Enhanced High-End Timer (N2HET) Modules): Updated/Changed N2HET1 time input capture or output compare pin descriptionGo
  • Table 4-19 Added alternate terminals for N2HET1 pins 17, 19, 21, 23, 25, 27, 29 and 31Go
  • Table 4-19: Added N2HET1_PIN_nDIS signal DESCRIPTIONGo
  • Table 4-19: Updated/Changed N2HET2 time input capture or output compare pin descriptionGo
  • Table 4-19: Added N2HET2_PIN_nDIS signal DESCRIPTIONGo
  • Table 4-20 Updated description about using GIOB[2] on ball V10Go
  • Table 4-28 (External Memory Interface (EMIF)): Global: Deleted EMIF_RNW pin function.Go
  • Table 4-34 (ZWT Test and Debug Modules Interface): Updated/Changed TEST pin descriptionGo
  • Table 4-36 (No Connects): Deleted NC pins A8, B8, and B9; supported on FlexRay Interface ControllerGo
  • Section 5 (Specifications): Updated/Changed section titleGo
  • Section 5.1 (Absolute Maximum Ratings): Reformatted tableGo
  • Section 5.1 (Absolute Maximum Ratings): Updated/Changed VCCAD supply voltage range MAX value from "5.5" to "6.25" VGo
  • Section 5.1: Updated/Changed ADC input pins input voltage range MAX value from "5.5" to "6.25" VGo
  • Section 5.2 (ESD Ratings): Added table (new)Go
  • Section 5.3 (Power-On Hours (POH)): Added table (new)Go
  • Section 5.8 (Input/Output Electrical Characteristics): Updated/Changed Input Clamp Current from IIC to IIKGo
  • Section 5.9 (Thermal Resistance Characteristics): Moved section and updated/changed subsection title.Go
  • Table 5-2 (Thermal Resistance Characteristics (PGE Package)): Added test conditions and added ΨJT row for PGE packageGo
  • Table 5-3 (Thermal Resistance Characteristics (ZWT Package)): Added test conditions and added ΨJT row for ZWT packageGo
  • Clarified impact of SPI2PC9 register on drive strength of SPI2SOMI pin Go
  • Updated/Changed the MIN value of tv(RST) to 2256tc(OSC) ns Go
  • Section 6.6.1 (Clock Sources): Added Table 6-8, Available Clock Source cross-referencesGo
  • Section 6.6.1.1 (Main Oscillator): Added Figure 6-4, Recommended Crystal/Clock Connection cross-referenceGo
  • Table 6-10 Added limits for HF LPO after software trim Go
  • Table 6-13 (Clock Domain Descriptions): Added missing "1" to the VCLKACON clock source selection register name for VCLKA3 rowGo
  • Section 6.9.1 Added addititional device-specific memory mapGo
  • Table 6-20 Corrected size of bank 7 OTP and bank 7 OTP ECCGo
  • Figure 6-12 (TCRAM Block Diagram): Updated/Changed figure, deleted A TCMGo
  • Table 6-25 Added table footnotes identifying the address ranges of the ESRAM PBIST groupsGo
  • Table 6-25 Added RAM power domain information in the table notesGo
  • Table 6-26(Memory Initialization): Updated/Changed N2HET2 RAM ending address from "0xFF57FFFF" to "0xFF45FFFF"Go
  • Table 6-38 Corrected base JTAG ID Base Value From 0xnD8A002F to 0xnB8A002FGo
  • Table 6-38 (JTAG ID Code): Added JTAG Identification Code for Silicon Revision "Rev D" Go
  • Table 7-7 (MibADC Recommended Operating Conditions): Updated/Changed Analog input clamp current from IAIC to IAIKGo
  • FlexRay Interface, Section 7.5.1 (Features): Updated/Changed "8KB of message ..." bullet for clarificationGo
  • Controller Area Network (DCAN) Section 7.6.1 (Features): Updated/Changed TRM references to the correct document titles Go
  • Table 7-24 (SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)): Updated/Changed table footnote to "... CLOCK PHASE bit (SPIFMTx.16) is cleared"Go
  • Section 8 (Device and Documentation Support): Updated/Changed section to meet new requirements, including addition of several subsectionsGo
  • Section 8.8 (Device Identification Code Register): Added Device ID code value for silicon Rev DGo
  • Section 8.9 (Die Identification Registers): Updated/Changed the address of the two die identification registers (DIEIDL and DIEIDH) to point to the original registers at location 0xFFFFFF7C and 0xFFFFFF80 for this section.Go
  • Table 8-3 (Die-ID Registers): Updated/Changed the BIT LOCATION column for all ITEM rowsGo
  • Section 9 (Mechanical Packaging and Orderable Information): Updated/Changed section titleGo
  • Section 9.1 (Packaging Information): Updated/Changed the paragraphGo