JAJSHU5B August   2019  – February 2024 TMUX1121 , TMUX1122 , TMUX1123

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics (VDD = 5V ±10 %)
    6. 6.6 Electrical Characteristics (VDD = 3.3V ±10 %)
    7. 6.7 Electrical Characteristics (VDD = 1.8V ±10 %)
    8. 6.8 Electrical Characteristics (VDD = 1.2V ±10 %)
    9. 6.9 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1 On-Resistance
    2. 7.2 Off-Leakage Current
    3. 7.3 On-Leakage Current
    4. 7.4 Transition time
    5. 7.5 Break-Before-Make
    6. 7.6 Charge Injection
    7. 7.7 Off Isolation
    8. 7.8 Channel-to-Channel Crosstalk
    9. 7.9 Bandwidth
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8V Logic Compatible Inputs
      4. 8.3.4 Fail-Safe Logic
      5. 8.3.5 Ultra-Low Leakage Current
      6. 8.3.6 Ultra-Low Charge Injection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Truth Tables
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application - Sample-and-Hold Circuit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Typical Application - Switched Gain Amplifier
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curve
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • DGK|8
サーマルパッド・メカニカル・データ
発注情報

Typical Application - Sample-and-Hold Circuit

One useful application to take advantage of the TMUX1121, TMUX1122, and TMUX1123 performance is the sample-and-hold circuit. A sample-and-hold circuit can be useful for an analog to digital converter (ADC) to sample a varying input voltage with improved reliability and stability. It can also be used to store the output samples from a single digital-to-analog converter (DAC) in a multi-output application. A simple sample-and-hold circuit can be realized using an analog switch such as the TMUX1121, TMUX1122, and TMUX1123 analog switches. Figure 9-1 shows a single channel sample-and hold circuit using only 1 of 2 channels in the TMUX112x devices.

GUID-24D9B103-F50A-474D-8D76-B5A1A21F206C-low.gifFigure 9-1 Single Channel Sample-and-Hold Circuit Example

An optional operational amplifier is used before the switch since buffered DACs typically have limitations in driving capacitive loads. The additional buffer stage is included following the DAC to prevent potential stability problems from driving a large capacitive load.

Ideally, the switch delivers only the input signals to the holding capacitors. However, when the switch gets toggled, some amount of charge also gets transferred to the switch output in the form of charge injection, resulting in a pedestal sampling error. The TMUX1121, TMUX1122, and TMUX1123 switches have excellent charge injection performance of only -1.5pC, making them an excellent choice for minimizing sampling errors in this implementation. The pedestal error voltage is indirectly related to the size of the capacitance on the output, for better precision a larger capacitor is required due to charge injection. Larger capacitance limits the system settling time which may not be acceptable in some applications. Figure 9-2 shows a TMUX112x device configured for a 2-channel sample-and-hold circuit with pedestal error compensation.

GUID-6DF1D048-445F-435D-9B28-5BAA35879456-low.gifFigure 9-2 2-Channel Sample-and-Hold Circuit with Pedestal Error Compensation