JAJSHU5B August   2019  – February 2024 TMUX1121 , TMUX1122 , TMUX1123

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics (VDD = 5V ±10 %)
    6. 6.6 Electrical Characteristics (VDD = 3.3V ±10 %)
    7. 6.7 Electrical Characteristics (VDD = 1.8V ±10 %)
    8. 6.8 Electrical Characteristics (VDD = 1.2V ±10 %)
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 On-Resistance
    2. 7.2 Off-Leakage Current
    3. 7.3 On-Leakage Current
    4. 7.4 Transition time
    5. 7.5 Break-Before-Make
    6. 7.6 Charge Injection
    7. 7.7 Off Isolation
    8. 7.8 Channel-to-Channel Crosstalk
    9. 7.9 Bandwidth
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8V Logic Compatible Inputs
      4. 8.3.4 Fail-Safe Logic
      5. 8.3.5 Ultra-Low Leakage Current
      6. 8.3.6 Ultra-Low Charge Injection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application - Sample-and-Hold Circuit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Typical Application - Switched Gain Amplifier
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curve
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DGK|8
サーマルパッド・メカニカル・データ
発注情報

9.2.2 Detailed Design Procedure

The TMUX1121, TMUX1122, or TMUX1123 switch is used in conjunction with the voltage holding capacitors (CH) to implement the sample-and-hold circuit. The basic operation is:

  1. When the switch (SW2) is closed, it samples the input voltage and charges the holding capacitors (CH) to the input voltages values.
  2. When the switch (SW2) is open, the holding capacitors (CH) holds its previous value, maintaining stable voltage at the amplifier output (VOUT).

Due to switch and capacitor leakage current, as well as amplifier bias current, the voltage on the hold capacitors droops with time. The TMUX1121, TMUX1122, or TMUX1123 minimize the droops due to its ultra-low leakage performance. At 25°C, the TMUX1121, TMUX1122, and TMUX1123 have extremely low leakage current at 3pA typical.

A second switch SW1 is also included to operate in parallel with SW2 to reduce pedestal error during switch toggling. Because both switches are driven at the same potential, they act as common-mode signal to the op-amp, thereby minimizing the charge injection effects caused by the switch toggling action. Compensation network consisting of RC and CC is also added to further reduce the pedestal error, whiling reducing the hold-time glitch and improving the settling time of the circuit. Refer to Sample and Hold Glitch Reduction for Precision Outputs Reference Design for more information on sample-and-hold circuits.