JAJSUX5 June   2024 TMUX1308A-Q1 , TMUX1309A-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information: TMUX1308A-Q1
    4. 6.4  Thermal Information: TMUX1309A-Q1
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  Logic and Dynamic Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Injection Current Coupling
    10. 6.10 Typical Characteristics
  8. Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  Break-Before-Make
    6. 7.6  tON(EN) and tOFF(EN)
    7. 7.7  Charge Injection
    8. 7.8  Off Isolation
    9. 7.9  Crosstalk
    10. 7.10 Bandwidth
    11. 7.11 Injection Current Control
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8V Logic Compatible Inputs
      4. 8.3.4 Fail-Safe Logic
      5. 8.3.5 High-Impedance Optimization
      6. 8.3.6 Injection Current Control
        1. 8.3.6.1 TMUX13xxA-Q1 is Powered, Channel is Unselected, and the Input Signal is Greater Than VDD (VDD = 5V, VINPUT = 5.5V)
        2. 8.3.6.2 TMUX13xxA-Q1 is Powered, Channel is Selected, and the Input Signal is Greater Than VDD (VDD = 5V, VINPUT = 5.5V)
        3. 8.3.6.3 TMUX13xxA-Q1 is Unpowered and the Input Signal has a Voltage Present (VDD = 0V, VINPUT = 3V)
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Short To Battery Protection
      4. 9.2.4 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Injection Current Control

Injection current is the current that is being forced into a pin by an input voltage (VIN) higher than the positive supply (VDD + ∆V) or lower than ground (VSS). The current flows through the input protection diodes into whichever supply of the device is potentially compromising the accuracy and reliability of the system. Injected currents can come from various sources depending on the application.

  • Harsh environments and applications with long cabling, such as in factory automation and automotive systems, may be susceptible to injected currents from switching or transient events.
  • Other self-contained systems can also be subject to injected current if the input signal is coming from various sensors or current sources.

Injected Current Impact: typical CMOS switches have ESD protection diodes on the inputs and outputs. These diodes not only serve as ESD protection but also provide a voltage clamp to prevent the inputs or outputs going above VDD or below GND and VSS. When current is injected into the pin of a disabled signal path, a small amount of current goes through the ESD diode but most of the current goes through conduction to the drain. If forward diode voltage of the ESD diode (VF) is greater than the PMOS threshold voltage (VT), then the PMOS of all OFF switches turns ON and there would be undesirable sub threshold leakage between the source and the drain that can lift the OFF source pins up also. Figure 8-3 shows a simplified diagram of a typical CMOS switch and associated injected current path.

TMUX1308A-Q1 TMUX1309A-Q1 Simplified Diagram of Typical CMOS Switch and Associated Injected Current PathFigure 8-3 Simplified Diagram of Typical CMOS Switch and Associated Injected Current Path

It is quite difficult to cut off these current paths. The drain pin can never be allowed to exceed the voltage above VDD by more than a VT. Analog pins can be protected against current injection by adding external components like a Schottky diode from the drain pin to ground to clamp the drain voltage at < VDD + VT and cut off the current path.

Change in RON due to Current Injection: because the ON resistance of the enabled FET switch is impacted by the change in the supply rail, when the drain pin voltage exceeds the supply voltage by more than a VT, an error in the output signal voltage can be expected. This undesired change in the output can cause issues related to false trigger events and incorrect measurement readings, potentially compromising the accuracy and reliability of the system. As shown in Figure 8-4, S2 is the enabled signal path that is conducting a signal from S2 pin to D pin. Because there is an injected current at the disabled S1 pin, the voltage at that pin increases above the supply voltage and the ESD protection diode is forward biased, shifting the power supply rail. This shift in supply voltage alters the RON of the internal FET switches, causing a ∆V error on the output at the D pin.

TMUX1308A-Q1 TMUX1309A-Q1 Injected Current Impact on
                        RONFigure 8-4 Injected Current Impact on RON

To avoid the complications of added external protection to your system, the TMUX1308A-Q1 and TMUX1309A-Q1 devices have an internal injection current control feature which eliminates the need for external diode and resistor networks typically used to protect the switch and keep the input signals within the supply voltage. The internal injection current control circuitry allows the signals on the disabled signal paths to exceed the supply voltage without affecting the signal of the enabled signal path. The injection current control circuitry also protects the TMUX13xxA-Q1 from currents injected into disabled signal paths without impacting the enabled signal path, which typical CMOS switches do not support. Additionally, the TMUX1308A-Q1 and TMUX1309A-Q1 do not have any internal diode paths to the supply pin, which eliminates the risk of damaging components connected to the supply pin or providing unintended power to the system supply rail. For a simplified diagram that shows one signal path for the TMUX13xxA-Q1 devices and the associated injection current circuit, refer to Section 8.2.

TMUX1308A-Q1 TMUX1309A-Q1 Simplified Diagram of Injection Current ControlFigure 8-5 Simplified Diagram of Injection Current Control

The injection current control circuitry is independently controlled for each source or drain pin (Sx or D). The control circuitry for a particular pin is enabled when that input is disabled by the logic pins and the injected current causes the voltage at the pin to be above VDD or below GND. The injection current circuit includes an FET to shunt the undesired current to GND in the case of overvoltage or injected current events. Each injection current circuit is rated to handle up to 50mA; the device, however, can support a maximum current of 100mA at any given time. Depending on the system application, a series limiting resistor may be needed and must be sized appropriately. Figure 8-5 shows the TMUX13xxA-Q1 protection circuitry with an injected current at an input pin.

TMUX1308A-Q1 TMUX1309A-Q1 Injected Current at Input PinFigure 8-6 Injected Current at Input Pin

Figure 8-7 shows an example of using a series limiting resistor in the case of an overvoltage event.

TMUX1308A-Q1 TMUX1309A-Q1 Over-Voltage Event with Series ResistorFigure 8-7 Over-Voltage Event with Series Resistor

For the injection current control circuitry to be active, two conditions must be present. First, the voltage at the source or drain pins is greater than VDD, or less than GND. Next, the channel must be unselected. With those two requirements met, the protection FET will be turned on for any disabled signal path and shunt the pin to GND. In this event, a series resistor is needed to limit the total current injected into the device to be less than 100mA. Three example scenarios are outlined in the following sections.