JAJSG54A September   2018  – December 2018 TMUX1511

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーションの例
      2.      ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Dynamic Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
      1. 6.8.1 Eye Diagrams
  7. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  IPOFF Leakage Current
    5. 7.5  Transition Time
    6. 7.6  TON (VDD) and TOFF (VDD) Time
    7. 7.7  Propagation Delay
    8. 7.8  Skew
    9. 7.9  Charge Injection
    10. 7.10 Capacitance
    11. 7.11 Off Isolation
    12. 7.12 Channel-to-Channel Crosstalk
    13. 7.13 Bandwidth
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Beyond Supply Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Powered-off Protection
      5. 8.3.5 Fail-Safe Logic
      6. 8.3.6 Low Capacitance
      7. 8.3.7 Integrated Pull-Down Resistors
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Protocol / Signal Isolation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Transimpedance Amplifier Feedback Control
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

VDD = 1.5 V to 5.5 V, GND = 0 V, TA = –40°C to +125°C,
Typical values are at VDD = 3.3 V, TA = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VDD Power supply voltage 1.5 5.5 V
IDD Supply current VSEL = 0 V, 1.4 V or VDD
VS = 0 V to 5.5 V		 37 70 μA
DC CHARACTERISTICS
RON On-resistance VS = 0 V to VDD*2
VS(max) = 5.5 V
ISD = 8 mA
Refer to ON-State Resistance Figure 		2 4.5 Ω
ΔRON On-resistance match between channels VS = VDD
ISD = 8 mA
Refer to ON-State Resistance Figure 		0.07 0.28 Ω
RON (FLAT)  On-resistance flatness VS = 0 V to VDD
ISD = 8 mA
Refer to ON-State Resistance Figure 		1 1.8 Ω
IPOFF Powered-off I/O pin leakage current VDD =  0 V
VS =  0 V to 3 V
VD = 0 V
TA = 25℃
Refer to Ipoff Leakage Figure 		–10 0.01 10 nA
IPOFF Powered-off I/O pin leakage current VDD =  0 V
VS =  0 V to 3.6 V
VD = 0 V
Refer to Ipoff Leakage Figure 		–2 0.01 2 µA
IS(OFF)
ID(OFF) 		OFF leakage current Switch Off
VD = 0.8*VDD / 0.2*VDD
VS = 0.2*VDD / 0.8*VDD
Refer to Off Leakage Figure 		–100 0.03 100 nA
ID(ON)
IS(ON) 		ON leakage current Switch On
VD = 0.8*VDD / 0.2*VDD, S pins floating
or
VS = 0.8*VDD / 0.2*VDD, D pins floating
Refer to On Leakage Figure 		–50 0.01 50 nA
LOGIC INPUTS
VIH Input logic high 1.2 5.5 V
VIL Input logic low 0 0.45 V
IIH Input high leakage current VSEL = 1.8 V, VDD 1 ±2 μA
IIL Input low leakage current VSEL = 0 V 0.2 ±2 μA
RPD Internal pull-down resistor on logic input pins 6 MΩ
CI Logic input capacitance VSEL = 0 V, 1.8 V or VDD
f = 1 MHz		 3 pF