JAJSO44A June   2023  – September 2024 TMUX582F-SEP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Global)
    6. 5.6 Single Supply: Electrical Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  On-Resistance
    2. 6.2  Off-Leakage Current
    3. 6.3  On-Leakage Current
    4. 6.4  Input and Output Leakage Current Under Overvoltage Fault
    5. 6.5  Break-Before-Make Delay
    6. 6.6  Enable Delay Time
    7. 6.7  Transition Time
    8. 6.8  Fault Response Time
    9. 6.9  Fault Recovery Time
    10. 6.10 Fault Flag Response Time
    11. 6.11 Fault Flag Recovery Time
    12. 6.12 Charge Injection
    13. 6.13 Off Isolation
    14. 6.14 Crosstalk
    15. 6.15 Bandwidth
    16. 6.16 THD + Noise
  8. 7 Truth Table
  9. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1 Flat ON- Resistance
      2. 8.2.2 Protection Features
        1. 8.2.2.1 Powered-Off Protection
        2. 8.2.2.2 Fail-Safe Logic
        3. 8.2.2.3 Overvoltage Protection and Detection
        4. 8.2.2.4 Adjacent Channel Operation During Fault
        5. 8.2.2.5 ESD Protection
        6. 8.2.2.6 Latch-Up Immunity
        7. 8.2.2.7 EMC Protection
      3. 8.2.3 Overvoltage Fault Flags
      4. 8.2.4 Bidirectional and Rail-to-Rail Operation
      5. 8.2.5 1.8V Logic Compatible Inputs
      6. 8.2.6 Integrated Pull-Down Resistor on Logic Pins
    3. 8.3 Device Functional Modes
      1. 8.3.1 Normal Mode
      2. 8.3.2 Fault Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 System Diagnostics – Telemetry
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|20
サーマルパッド・メカニカル・データ
発注情報

8.2.2.4 Adjacent Channel Operation During Fault

When the logic pins are set to a channel under a fault, the overvoltage detection will trigger, the switch will open, and the drain pin will be pulled up or down as described in Section 8.2.2.3. During such an event, all other channels not under a fault can continue to operate as normal. For example, if S1 voltage exceeds VFP, and the logic pins are set to S1, the drain output is pulled to VFP. Then if the logic pins are changed to set S4, which is not in overvoltage, the drain will disconnect from the pullup to VFP and the S4 switch will be enabled and connected to the drain, operating as normal. If the logic pins are switched back to S1, the S4 switch will be disabled, the drain pin will be pulled up to VFP again, and the switch from S1 to drain will not be enabled until the overvoltage fault is removed.