JAJSJW0E September   2020  – July 2024 TMUX6219

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Source or Drain Continuous Current
    6. 5.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 5.7  ±15 V Dual Supply: Switching Characteristics 
    8. 5.8  36 V Single Supply: Electrical Characteristics 
    9. 5.9  36 V Single Supply: Switching Characteristics 
    10. 5.10 12 V Single Supply: Electrical Characteristics 
    11. 5.11 12 V Single Supply: Switching Characteristics 
    12. 5.12 +5 V / -8 V Dual Supply: Electrical Characteristics 
    13. 5.13 +5 V / -8 V Dual Supply: Switching Characteristics 
    14. 5.14 ±5 V Dual Supply: Electrical Characteristics 
    15. 5.15 ±5 V Dual Supply: Switching Characteristics 
    16. 5.16 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  On-Resistance
    2. 6.2  Off-Leakage Current
    3. 6.3  On-Leakage Current
    4. 6.4  Transition Time
    5. 6.5  tON(EN) and tOFF(EN)
    6. 6.6  Break-Before-Make
    7. 6.7  tON (VDD) Time
    8. 6.8  Propagation Delay
    9. 6.9  Charge Injection
    10. 6.10 Off Isolation
    11. 6.11 Crosstalk
    12. 6.12 Bandwidth
    13. 6.13 THD + Noise
    14. 6.14 Power Supply Rejection Ratio (PSRR)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bidirectional Operation
      2. 7.3.2 Rail to Rail Operation
      3. 7.3.3 1.8V Logic Compatible Inputs
      4. 7.3.4 Fail-Safe Logic
      5. 7.3.5 Latch-Up Immune
      6. 7.3.6 Ultra-Low Charge Injection
    4. 7.4 Device Functional Modes
    5. 7.5 Truth Tables
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Power Amplifier Gate Driver
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curve
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.12 +5 V / -8 V Dual Supply: Electrical Characteristics 

VDD = +5 V ± 10%, VSS = –8 V ±10%, GND = 0 V (unless otherwise noted) 
Typical at VDD = +5 V, VSS = –5 V, TA = 25℃  (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
ANALOG SWITCH
RON On-resistance VDD = +5 V, VSS = –8 V
VS = VDD to VSS
ID = –10 mA
Refer to On-Resistance		 25°C 4.2 5.5 Ω
–40°C to +85°C 6.8 Ω
–40°C to +125°C 7.6 Ω
ΔRON On-resistance mismatch between channels VS = VDD to VSS
ID = –10 mA
Refer to On-Resistance		 25°C 0.1 0.23 Ω
–40°C to +85°C 0.27 Ω
–40°C to +125°C 0.35 Ω
RON FLAT On-resistance flatness VS = VDD to VSS
ID = –10 mA
Refer to On-Resistance		 25°C 1 1.5 Ω
–40°C to +85°C 1.7 Ω
–40°C to +125°C 2 Ω
RON DRIFT On-resistance drift VS = 0 V, IS = –10 mA
Refer to On-Resistance		 –40°C to +125°C 0.019 Ω/°C
IS(OFF) Source off leakage current(1) VDD = +5.5 V, VSS = –8.8 V
Switch state is off
VS = VDD - 1 / VSS + 1
VD = VSS + 1 / VDD - 1 
Refer to Off-Leakage Current		 25°C –0.3 0.1 0.3 nA
–40°C to +85°C –3 3 nA
–40°C to +125°C –50 50 nA
ID(OFF) Drain off leakage current(1) VDD = +5.5 V, VSS = –8.8 V
Switch state is off
VS = VDD - 1 / VSS + 1
VD = VSS + 1 / VDD - 1 
Refer to Off-Leakage Current		 25°C –0.5 0.1 0.5 nA
–40°C to +85°C –3 3 nA
–40°C to +125°C –55 55 nA
IS(ON)
ID(ON)		 Channel on leakage current(2) VDD = +5.5 V, VSS = –8.8 V
Switch state is on
VS = VD = VDD - 1 / VSS + 1
Refer to On-Leakage Current		 25°C –0.5 0.1 0.5 nA
–40°C to +85°C –3 3 nA
–40°C to +125°C –40 40 nA
LOGIC INPUTS (SEL / EN pins)
VIH Logic voltage high –40°C to +125°C 1.3 44 V
VIL Logic voltage low –40°C to +125°C 0 0.8 V
IIH Input leakage current –40°C to +125°C 0.005 2 µA
IIL Input leakage current –40°C to +125°C –1 –0.005 µA
CIN Logic input capacitance –40°C to +125°C 3 pF
POWER SUPPLY
IDD VDD supply current VDD = +5.5 V, VSS = –8.8 V
Logic inputs = 0 V, 5 V, or VDD		 25°C 24 30 µA
–40°C to +85°C 37 µA
–40°C to +125°C 42 µA
ISS VSS supply current VDD = +5.5 V, VSS = –8.8 V
Logic inputs = 0 V, 5 V, or VDD		 25°C 1 5 µA
–40°C to +85°C 8 µA
–40°C to +125°C 12 µA
(1) When VS is positive, VD is negative, or when VS is negative, VD is positive.
(2) When VS is at a voltage potential, VD is floating, or when VD is at a voltage potential, VS is floating.