JAJSKT7B January   2021  – July 2024 TMUX7219-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Source or Drain Continuous Current
    6. 5.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 5.7  ±15 V Dual Supply: Switching Characteristics 
    8. 5.8  ±20 V Dual Supply: Electrical Characteristics
    9. 5.9  ±20 V Dual Supply: Switching Characteristics
    10. 5.10 44 V Single Supply: Electrical Characteristics 
    11. 5.11 44 V Single Supply: Switching Characteristics 
    12. 5.12 12 V Single Supply: Electrical Characteristics 
    13. 5.13 12 V Single Supply: Switching Characteristics 
    14. 5.14 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  On-Resistance
    2. 6.2  Off-Leakage Current
    3. 6.3  On-Leakage Current
    4. 6.4  Transition Time
    5. 6.5  tON(EN) and tOFF(EN)
    6. 6.6  Break-Before-Make
    7. 6.7  tON (VDD) Time
    8. 6.8  Propagation Delay
    9. 6.9  Charge Injection
    10. 6.10 Off Isolation
    11. 6.11 Crosstalk
    12. 6.12 Bandwidth
    13. 6.13 THD + Noise
    14. 6.14 Power Supply Rejection Ratio (PSRR)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bidirectional Operation
      2. 7.3.2 Rail-to-Rail Operation
      3. 7.3.3 1.8 V Logic Compatible Inputs
      4. 7.3.4 Integrated Pull-Up and Pull-Down Resistor on Logic Pins
      5. 7.3.5 Fail-Safe Logic
      6. 7.3.6 Latch-Up Immune
      7. 7.3.7 Ultra-Low Charge Injection
    4. 7.4 Device Functional Modes
    5. 7.5 Truth Tables
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition Calibration
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.7 Ultra-Low Charge Injection

Figure 7-1 shows how the TMUX7219-Q1 has a transmission gate topology. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.

TMUX7219-Q1 Transmission Gate Topology Figure 7-1 Transmission Gate Topology

The TMUX7219-Q1 contains specialized architecture to reduce charge injection on the source (Sx). To further reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the drain (D). This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the drain (D) instead of the source (Sx). As a general rule, Cp should be 20× larger than the equivalent load capacitance on the source (Sx). Figure 7-2 shows charge injection variation with source voltage with different compensation capacitors on the drain side.

TMUX7219-Q1 Charge Injection Compensation Figure 7-2 Charge Injection Compensation