JAJSK10B september   2021  – august 2023 TMUX8108 , TMUX8109

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings: TMUX810x Devices
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions: TMUX810x Devices
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics (Global): TMUX810x Devices
    6. 7.6  Electrical Characteristics (±15-V Dual Supply)
    7. 7.7  Electrical Characteristics (±36-V Dual Supply)
    8. 7.8  Electrical Characteristics (±50-V Dual Supply)
    9. 7.9  Electrical Characteristics (72-V Single Supply)
    10. 7.10 Electrical Characteristics (100-V Single Supply)
    11. 7.11 Switching Characteristics: TMUX810x Devices
    12. 7.12 Typical Characteristics
  9. 8 Parameter Measurement Information
    1. 8.1  On-Resistance
    2. 8.2  Off-Leakage Current
    3. 8.3  On-Leakage Current
    4. 8.4  Break-Before-Make Delay
    5. 8.5  Enable Turn-on and Turn-off Time
    6. 8.6  Transition Time
    7. 8.7  Charge Injection
    8. 8.8  Off Isolation
    9. 8.9  Crosstalk
    10. 8.10 Bandwidth
    11. 8.11 THD + Noise
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bidirectional Operation
      2. 9.3.2 Flat On – Resistance
      3. 9.3.3 Protection Features
        1. 9.3.3.1 Fail-Safe Logic
        2. 9.3.3.2 ESD Protection
        3. 9.3.3.3 Latch-Up Immunity
      4. 9.3.4 1.8 V Logic Compatible Inputs
      5. 9.3.5 Integrated Pull-Down Resistor on Logic Pins
    4. 9.4 Device Functional Modes
      1. 9.4.1 Normal Mode
      2. 9.4.2 Truth Tables
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
  • RUM|16
サーマルパッド・メカニカル・データ
発注情報

7.9 Electrical Characteristics (72-V Single Supply)

VDD = +72 V ± 10%, VSS = 0 V, GND = 0 V (unless otherwise noted) 
Typical at TA = 25℃  (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
ANALOG SWITCH
RON On-resistance VS = 0 V to +60 V
ID = –5 mA		 25°C 38 48 Ω
–40°C to +85°C 65
–40°C to +125°C 80
ΔRON On-resistance mismatch between channels VS = 0 V to +60 V
ID = –5 mA		 25°C 0.65 Ω
–40°C to +85°C 1.5
–40°C to +125°C 2.1
RON FLAT On-resistance flatness VS = 0 V to +60 V
ID = –5 mA		 25°C 0.6 Ω
RON DRIFT On-resistance drift VS = 0 V, IS = –5 mA –40°C to +125°C 0.25 Ω/°C
IS(OFF) Source off leakage current(1) Switch state is off
VS = +60 V / 1 V
VD = 1 V / +60 V		 25°C 0.02 nA
–40°C to +85°C –3 3
–40°C to +125°C –15 15
ID(OFF) Drain off leakage current(1) Switch state is off
VS = +60 V / 1 V
VD = 1 V / +60 V		 25°C 0.06 nA
–40°C to +85°C –8 8
–40°C to +125°C –40 40
IS(ON)
ID(ON)		 Channel on leakage current(2) Switch state is on
VS = VD = 1 V / +60 V		 25°C 0.07 nA
–40°C to +85°C –8 8
–40°C to +125°C –40 40
ΔIS(ON)
ΔID(ON)		 Leakage current mismatch between channels(2) Switch state is on
VS = VD = 1 V / +60 V		 25°C 20 pA
85°C 50
125°C 120
(1) When VS is 60 V, VD is 1 V. Or when VS is 1 V, VD is 60 V.
(2) When VS is at a voltage potential, VD is floating. Or when VD is at a voltage potential, VS is floating.