JAJSUQ7B June   2024  – September 2024 TMUXS7614D

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Source or Drain Current through Switch
    6. 5.6  Electrical Characteristics (Global)
    7. 5.7  Electrical Characteristics (±15 V Dual Supply)
    8. 5.8  Switching Characteristics (±15 V Dual Supply)
    9. 5.9  Electrical Characteristics (±20 V Dual Supply)
    10. 5.10 Switching Characteristics (±20 V Dual Supply)
    11. 5.11 Electrical Characteristics (+37.5 V/–12.5 V Dual Supply)
    12. 5.12 Switching Characteristics (+37.5 V/–12.5 V Dual Supply)
    13. 5.13 Electrical Characteristics (12 V Single Supply)
    14. 5.14 Switching Characteristics (12 V Single Supply)
    15. 5.15 SPI Timing Characteristics (2.7 V to 5.5 V)
    16. 5.16 SPI Timing Characteristics (1.8 V to 2.7 V)
    17. 5.17 Timing Diagrams
    18. 5.18 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  On-Resistance
    2. 6.2  Off-Leakage Current
    3. 6.3  On-Leakage Current
    4. 6.4  tON and tOFF Time
    5. 6.5  Break-Before-Make
    6. 6.6  Charge Injection
    7. 6.7  Off Isolation
    8. 6.8  Channel-to-Channel Crosstalk
    9. 6.9  Bandwidth
    10. 6.10 THD + Noise
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Bidirectional Operation
      2. 7.3.2 Rail-to-Rail Operation
      3. 7.3.3 1.8V Logic Compatible Inputs
      4. 7.3.4 Flat On-Resistance
      5. 7.3.5 Power-Up Sequence Free
    4. 7.4 SPI Operation
      1. 7.4.1 Address Mode
      2. 7.4.2 Burst Mode
      3. 7.4.3 Daisy Chain Mode
      4. 7.4.4 Error Detection
        1. 7.4.4.1 Address R/W Error Flag
        2. 7.4.4.2 SCLK Count Error Flag
        3. 7.4.4.3 CRC (Cyclic Redundancy Check) Enable and Error Flag
        4. 7.4.4.4 Clearing Error Flags
      5. 7.4.5 Software Reset
    5. 7.5 Device Functional Modes
    6. 7.6 Register Map
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Thermal Considerations
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

6.6 Charge Injection

The TMUXS7614D devices have a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted by the symbol QC. Figure 6-6 shows the setup used to measure charge injection from source (Sx) to drain (Dx).

TMUXS7614D Charge-Injection Measurement Setup Figure 6-6 Charge-Injection Measurement Setup