JAJSED7B
January 2018 – August 2018
TPA3220
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
概略回路図
4
改訂履歴
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Audio Characteristics (BTL)
7.7
Audio Characteristics (PBTL)
7.8
Typical Characteristics, BTL Configuration, AD-mode
7.9
Typical Characteristics, PBTL Configuration, AD-mode
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagrams
9.3
Feature Description
9.3.1
Internal LDO
9.3.1.1
Input Configuration, Gain Setting And Master / Slave Operation
9.3.2
Gain Setting And Master / Slave Operation
9.3.3
AD-Mode and HEAD-Mode PWM Modulation
9.3.4
Oscillator
9.3.5
Input Impedance
9.3.6
Error Reporting
9.4
Device Functional Modes
9.4.1
Powering Up
9.4.1.1
Startup Ramp Time
9.4.2
Powering Down
9.4.2.1
Power Down Ramp Time
9.4.3
Device Reset
9.4.4
Device Soft Mute
9.4.5
Device Protection System
9.4.5.1
Overload and Short Circuit Current Protection
9.4.5.2
Signal Clipping and Pulse Injector
9.4.5.3
DC Speaker Protection
9.4.5.4
Pin-to-Pin Short Circuit Protection (PPSC)
9.4.5.5
Overtemperature Protection OTW and OTE
9.4.5.6
Undervoltage Protection (UVP) and Power-on Reset (POR)
9.4.5.7
Fault Handling
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications
10.2.1
Stereo BTL Application
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedures
10.2.1.2.1
Decoupling Capacitor Recommendations
10.2.1.2.2
PVDD Capacitor Recommendation
10.2.1.2.3
BST capacitors
10.2.1.2.4
PCB Material Recommendation
10.2.2
Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)
10.2.2.1
Design Requirements
10.2.3
Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
10.2.3.1
Design Requirements
11
Power Supply Recommendations
11.1
Power Supplies
11.1.1
VDD Supply
11.1.2
AVDD and GVDD Supplies
11.1.3
PVDD Supply
11.1.4
BST Supply
12
Layout
12.1
Layout Guidelines
12.2
Layout Examples
12.2.1
BTL Application Printed Circuit Board Layout Example
12.2.2
PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
12.2.3
PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
13
デバイスおよびドキュメントのサポート
13.1
ドキュメントのサポート
13.2
ドキュメントの更新通知を受け取る方法
13.3
コミュニティ・リソース
13.4
商標
13.5
静電気放電に関する注意事項
13.6
Glossary
14
メカニカル、パッケージ、および注文情報
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
DDW|44
サーマルパッド・メカニカル・データ
発注情報
jajsed7b_oa
jajsed7b_pm
10.2.1
Stereo BTL Application
Figure 50.
Typical Differential (2N) AD-Mode BTL Application