JAJSE46B September   2017  – December 2017 TPA3221

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Audio Characteristics (BTL)
    7. 7.7 Audio Characteristics (PBTL)
    8. 7.8 Typical Characteristics, BTL Configuration, AD-mode
    9. 7.9 Typical Characteristics, PBTL Configuration, AD-mode
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagrams
    3. 9.3 Feature Description
      1. 9.3.1 Internal LDO
        1. 9.3.1.1 Input Configuration, Gain Setting And Master / Slave Operation
      2. 9.3.2 Gain Setting And Master / Slave Operation
      3. 9.3.3 AD-Mode and HEAD-Mode PWM Modulation
      4. 9.3.4 Oscillator
      5. 9.3.5 Input Impedance
      6. 9.3.6 Error Reporting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Powering Up
        1. 9.4.1.1 Startup Ramp Time
      2. 9.4.2 Powering Down
        1. 9.4.2.1 Power Down Ramp Time
      3. 9.4.3 Device Reset
      4. 9.4.4 Device Soft Mute
      5. 9.4.5 Device Protection System
        1. 9.4.5.1 Overload and Short Circuit Current Protection
        2. 9.4.5.2 Signal Clipping and Pulse Injector
        3. 9.4.5.3 DC Speaker Protection
        4. 9.4.5.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 9.4.5.5 Overtemperature Protection OTW and OTE
        6. 9.4.5.6 Undervoltage Protection (UVP), Overvoltage Protection (OVP) and Power-on Reset (POR)
        7. 9.4.5.7 Fault Handling
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo BTL Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedures
          1. 10.2.1.2.1 Decoupling Capacitor Recommendations
          2. 10.2.1.2.2 PVDD Capacitor Recommendation
          3. 10.2.1.2.3 BST capacitors
          4. 10.2.1.2.4 PCB Material Recommendation
      2. 10.2.2 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled before LC filter)
        1. 10.2.2.1 Design Requirements
      3. 10.2.3 Typical Application, Differential (2N), AD-Mode PBTL (Outputs Paralleled after LC filter)
        1. 10.2.3.1 Design Requirements
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
      1. 11.1.1 VDD Supply
      2. 11.1.2 AVDD and GVDD Supplies
      3. 11.1.3 PVDD Supply
      4. 11.1.4 BST Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
      1. 12.2.1 BTL Application Printed Circuit Board Layout Example
      2. 12.2.2 PBTL (Outputs Paralleled before LC filter) Application Printed Circuit Board Layout Example
      3. 12.2.3 PBTL (Outputs Paralleled after LC filter) Application Printed Circuit Board Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

The TPA3221 is available in a thermally enhanced TSSOP package.

The package type contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heat sink.

DDV Package
HTSSOP 44-Pin
(Top View)
TPA3221 DDV-44.gif

Pin Functions

NAME NO. I/O DESCRIPTION
HEAD 11 I 0 = AD, 1 = HEAD. Refer to: AD-Mode and HEAD-Mode PWM Modulation
AVDD 21 P AVDD voltage supply. Refer to: Internal LDO, AVDD and GVDD Supplies
BST1_M 43 P OUT1_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_M required.
Refer to: BST capacitors
BST1_P 44 P OUT1_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT1_P required.
Refer to: BST capacitors
BST2_M 23 P OUT2_M HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_M required.
Refer to: BST capacitors
BST2_P 24 P OUT2_P HS bootstrap supply (BST), 0.033 μF capacitor to OUT2_P required.
Refer to: BST capacitors
CMUTE 17 P Mute and Startup Timing Capacitor. Connect a 33 nF capacitor to GND. Refer to: Device Reset
FAULT 4 O Shutdown signal, open drain; active low. Refer to: Error Reporting
FREQ_ADJ 14 O Oscillator frequency programming pin. Refer to: Oscillator
GAIN/SLV 2 I Closed loop gain and master/slave programming pin.
Refer to: Input Configuration, Gain Setting And Master / Slave Operation
GND 5, 6, 7, 18, 19, 20, 25, 26, 33, 34, 41, 42 P Ground
GVDD 22 P Gate drive supply. Refer to: Internal LDO, AVDD and GVDD Supplies
IN1_M 9 I Negative audio input for channel 1
IN1_P 8 I Positive audio input for channel 1
IN2_M 16 I Negative audio input for channel 2
IN2_P 15 I Positive audio input for channel 2
OSCM 12 I/O Oscillator synchronization interface.
Refer to: Input Configuration, Gain Setting And Master / Slave Operation
OSCP 13 I/O Oscillator synchronization interface.
Refer to: Input Configuration, Gain Setting And Master / Slave Operation
OTW_CLIP 3 O Clipping warning and Over-temperature warning; open drain; active low.
Refer to: Error Reporting
OUT1_M 35 O Negative output for channel 1
OUT1_P 39, 40 O Positive output for channel 1
OUT2_M 27, 28 O Negative output for channel 2
OUT2_P 32 O Positive output for channel 2
PVDD 29, 30, 31, 36, 37, 38 P PVDD supply. Refer to: PVDD Capacitor Recommendation, PVDD Supply
RESET 10 I Device reset Input; active low. Refer to: Fault Handling, Powering Up, Powering Down
VDD 1 P Input power supply. Refer to: Internal LDO, VDD Supply
PowerPad™ P Ground, connect to grounded heatsink. Placed on top side of device.

Table 1. Mode Selection Pins

MODE PINS(2) INPUT MODE(1) OUTPUT CONFIGURATION DESCRIPTION
IN2_M IN2_P HEAD
X X 0 1N/2N + 1 2 × BTL Stereo, BTL output configuration, AD mode modulation
X X 1 1N/2N + 1 2 × BTL Stereo, BTL output configuration, HEAD mode modulation
0 0 0 1N/2N + 1 1 x PBTL Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, AD mode modulation
0 0 1 1N/2N + 1 1 x PBTL Mono, Parallelled BTL configuration. Connect OUT1_P to OUT2_P and OUT1_M to OUT2_M, HEAD mode modulation
1 1 0 1N/2N + 1 1 x BTL Mono, BTL configuration. OUT1_M and OUT1_P active, AD mode modulation
1 1 1 1N/2N + 1 1 x BTL Mono, BTL configuration. OUT1_M and OUT1_P active, HEAD mode modulation
(1) 2N refers to differential input signal, 1N refers to single ended input signal. +1 refers to number of logic control (RESET) input pins.
(2) X refers to inputs connected through AC coupling capacitor, 0 refers to logic low (GND), 1 refers to logic high (AVDD).