JAJSGU0A January 2019 – March 2019 TPA3255-Q1
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
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INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION |
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DVDD | Voltage regulator, only used as reference node | VDD = 10.6 V | 3 | 3.3 | 3.6 | V |
AVDD | Voltage regulator, only used as reference node | VDD = 10.6 V | 7.75 | V | ||
IVDD | VDD supply current | Operating, 50% duty cycle | 30 | mA | ||
Idle, reset mode | 14 | |||||
IGVDD_X | Gate-supply current per full-bridge | 50% duty cycle | 44 | mA | ||
Reset mode | 5 | |||||
IPVDD_X | PVDD idle current per full bridge | 50% duty cycle with recommended output filter | 24 | mA | ||
Reset mode, No switching | 5 | mA | ||||
VDD = 0V, GVDD_X = 0V | 1.25 | mA | ||||
ANALOG INPUTS | ||||||
RIN | Input resistance | 20 | kΩ | |||
VIN | Maximum input voltage swing, peak - peak | 7 | V | |||
IIN | Maximum input current | 1 | mA | |||
G | Inverting voltage Gain | VOUT/VIN | 21.5 | dB | ||
OSCILLATOR | ||||||
FPWM | PWM Output Frequency | Nominal, Master Mode, 1% Resistor | 450 | kHz | ||
AM1, Master Mode, 1% Resistor | 500 | |||||
AM2, Master Mode, 1% Resistor | 600 | |||||
ΔFPWM | PWM Output Frequency Variation | 1% Resistor | 5 | % | ||
fOSC(IO+) | Oscillator Frequency | Nominal, Master Mode, FPWM × 6 | 2.7 | MHz | ||
AM1, Master Mode, FPWM × 6 | 3 | |||||
AM2, Master Mode, FPWM × 6 | 3.45 | 3.6 | 3.75 | |||
ΔfOSC(IO+) | Oscillator Frequency Variation | 5 | % | |||
VIH | High level input voltage | 1.86 | V | |||
VIL | Low level input voltage | 1.45 | V | |||
OUTPUT-STAGE MOSFETs | ||||||
RDS(on) | Drain-to-source resistance, low side (LS) | TJ = 25°C, Includes metallization resistance,
GVDD = 10.6 V |
85 | mΩ | ||
Drain-to-source resistance, high side (HS) | 85 | mΩ | ||||
I/O
PROTECTION |
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Vuvp,VDD,GVDD | Undervoltage protection limit, GVDD_x and VDD | 8.7 | V | |||
Vuvp,VDD, GVDD,hyst(1) | 0.6 | V | ||||
Vuvp,PVDD | Undervoltage protection limit, PVDD_x | 14.5 | V | |||
Vuvp,PVDD,hyst(1) | 1.4 | V | ||||
OTW | Overtemperature warning, CLIP_OTW(1) | 110 | 120 | 130 | °C | |
OTWhyst(1) | Temperature drop needed below OTW temperature for CLIP_OTW to be inactive after OTW event. | 20 | °C | |||
OTE(1) | Overtemperature error | 140 | 150 | 160 | °C | |
OTEhyst(1) | A reset needs to occur for FAULT to be released following an OTE event | 15 | °C | |||
OTE-OTW(differential)(1) | OTE-OTW differential | 30 | °C | |||
OLPC | Overload protection counter | fPWM = 450 kHz (1024 PWM cycles) | 2.3 | ms | ||
IOC | Overcurrent limit protection | Resistor – programmable, nominal peak current in 1Ω load, ROCP = 22 kΩ | 17 | A | ||
Resistor – programmable, nominal peak current in 1Ω load, ROCP = 30 kΩ | 13 | |||||
IOC(LATCHED) | Overcurrent limit protection | Resistor – programmable, peak current in 1Ω load, ROCP = 47kΩ | 17 | A | ||
Resistor – programmable, peak current in 1Ω load, ROCP = 64kΩ | 13 | |||||
IDCspkr | DC Speaker Protection Current Threshold | BTL current imbalance threshold | 1.5 | A | ||
IOCT | Overcurrent response time | Time from switching transition to flip-state induced by overcurrent. | 150 | ns | ||
IPD | Output pulldown current of each half | Connected when RESET is active to provide bootstrap charge. Not used in SE mode. | 3 | mA | ||
STATIC DIGITAL SPECIFICATIONS | ||||||
VIH | High level input voltage | M1, M2, OSC_IOP, OSC_IOM, RESET | 1.9 | V | ||
VIL | Low level input voltage | 0.8 | V | |||
Ilkg | Input leakage current | 100 | μA | |||
OTW/SHUTDOWN (FAULT) | ||||||
RINT_PU | Internal pullup resistance, CLIP_OTW to DVDD, FAULT to DVDD | 26 | kΩ | |||
ΔRINT_PU | Internal pullup resistance variation, CLIP_OTW to DVDD, FAULT to DVDD | 25 | % | |||
VOH | High level output voltage | Internal pullup resistor | 3 | 3.3 | 3.6 | V |
VOL | Low level output voltage | IO = 4 mA | 10 | 500 | mV | |
Device fanout | CLIP_OTW, FAULT | No external pullup | 30 | devices |