JAJSGU0A January   2019  – March 2019 TPA3255-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      全高調波歪み
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Audio Characteristics (BTL)
    7. 6.7  Audio Characteristics (SE)
    8. 6.8  Audio Characteristics (PBTL)
    9. 6.9  Typical Characteristics, BTL Configuration
    10. 6.10 Typical Characteristics, SE Configuration
    11. 6.11 Typical Characteristics, PBTL Configuration
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Error Reporting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Protection System
        1. 8.4.1.1 Overload and Short Circuit Current Protection
        2. 8.4.1.2 Signal Clipping and Pulse Injector
        3. 8.4.1.3 DC Speaker Protection
        4. 8.4.1.4 Pin-to-Pin Short Circuit Protection (PPSC)
        5. 8.4.1.5 Overtemperature Protection OTW and OTE
        6. 8.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)
        7. 8.4.1.7 Fault Handling
        8. 8.4.1.8 Device Reset
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Stereo BTL Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedures
          1. 9.2.1.2.1 Decoupling Capacitor Recommendations
          2. 9.2.1.2.2 PVDD Capacitor Recommendation
          3. 9.2.1.2.3 PCB Material Recommendation
          4. 9.2.1.2.4 Oscillator
      2. 9.2.2 Application Curves
      3. 9.2.3 Typical Application, Single Ended (1N) SE
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedures
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Typical Application, Differential (2N) PBTL
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedures
        3. 9.2.4.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
      1. 10.1.1 VDD Supply
      2. 10.1.2 GVDD_X Supply
      3. 10.1.3 PVDD Supply
    2. 10.2 Powering Up
    3. 10.3 Powering Down
    4. 10.4 Thermal Design
      1. 10.4.1 Thermal Performance
      2. 10.4.2 Thermal Performance with Continuous Output Power
      3. 10.4.3 Thermal Performance with Non-Continuous Output Power
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
      1. 11.2.1 BTL Application Printed Circuit Board Layout Example
      2. 11.2.2 SE Application Printed Circuit Board Layout Example
      3. 11.2.3 PBTL Application Printed Circuit Board Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.1.6 Undervoltage Protection (UVP) and Power-on Reset (POR)

The UVP and POR circuits of the TPA3255-Q1 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach values stated in the Electrical Characteristics table. Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold.