SLAS997B March   2014  – January 2015 TPA6166A2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics, Audio Amplifiers
    7. 6.7 Electrical Characteristics, Mic Preamplifier and Bias
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 I2C Interface
        1. 7.3.1.1 Single and Multiple Byte Transfers
        2. 7.3.1.2 Single-Byte Write
        3. 7.3.1.3 Multiple-Byte Write and Incremental Multiple-Byte Write
        4. 7.3.1.4 Single-Byte Read
        5. 7.3.1.5 Multiple-Byte Read
      2. 7.3.2 Accessory Detection
      3. 7.3.3 Audio Playback Channel
        1. 7.3.3.1 Class-G Headphone Amplifier
          1. 7.3.3.1.1 Headphone Charge Pump
        2. 7.3.3.2 Out-of-Band and Input RF Noise Rejection
      4. 7.3.4 Mic Channel
      5. 7.3.5 Button Press Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 I2C Options
      2. 7.4.2 System in Shutdown Mode
      3. 7.4.3 System in Sleep Mode
        1. 7.4.3.1 Accessory Not Inserted
        2. 7.4.3.2 Accessory Inserted
        3. 7.4.3.3 Button Detection During Sleep Mode
      4. 7.4.4 System in Wake-Up Mode
        1. 7.4.4.1 Accessory Not Inserted
        2. 7.4.4.2 Accessory Inserted
        3. 7.4.4.3 Audio Not Playing or Not in Voice Call
        4. 7.4.4.4 High Impedance Line Out Load
        5. 7.4.4.5 Button Detection
    5. 7.5 Register Maps
      1. 7.5.1 Register Functional Overview
      2. 7.5.2 Initialization
        1. 7.5.2.1 Reserved Registers
        2. 7.5.2.2 Fixed Registers
        3. 7.5.2.3 Other Registers
      3. 7.5.3 Typical Use Case Modes
      4. 7.5.4 Recommended Software Flow Chart
      5. 7.5.5 Register Map Summary
      6. 7.5.6 Detailed Register Descriptions
        1. 7.5.6.1  Register 0x00: Config and Device Status Register 1
        2. 7.5.6.2  Register 0x01: Config and Device Status Register 2
        3. 7.5.6.3  Register 0x02: Config and Device Status Register 2
        4. 7.5.6.4  Register 0x03: Reserved Register
        5. 7.5.6.5  Register 0x04: Interrupt Mask Register 1
        6. 7.5.6.6  Register 0x05: Interrupt Mask Register 2
        7. 7.5.6.7  Register 0x06: Reserved Register
        8. 7.5.6.8  Register 0x07: Headphone Volume Register 1
        9. 7.5.6.9  Register 0x08: Headphone Volume Control Register 2
        10. 7.5.6.10 Register 0x09: Microphone Bias Control Register
        11. 7.5.6.11 Register 0x0a: Reserved
        12. 7.5.6.12 Register 0x0b: Revision ID Register
        13. 7.5.6.13 Register 0x0c: Reserved Register
        14. 7.5.6.14 Registers 0x0d to 0x10: Reserved Registers
        15. 7.5.6.15 Register 0x11: Reserved
        16. 7.5.6.16 Register 0x12: Reserved
        17. 7.5.6.17 Register 0x13: Reserved
        18. 7.5.6.18 Register 0x14: Reserved Register
        19. 7.5.6.19 Register 0x15: Keyscan Debounce Register
        20. 7.5.6.20 Register 0x16: Keyscan Delay Register
        21. 7.5.6.21 Register 0x17: Passive Multi Button Keyscan Data Register
        22. 7.5.6.22 Register 0x18: Jack Detect Test Hardware Settings
        23. 7.5.6.23 Register 0x19:State Register
        24. 7.5.6.24 Register 0x1a: Jack Detect Test Hardware Settings
        25. 7.5.6.25 Registers 0x1b: Reserved
        26. 7.5.6.26 Register 0x1c: Clock Control
        27. 7.5.6.27 Register 0x1d: Enable Register 1
        28. 7.5.6.28 Register 0x1e: Enable Register 2
        29. 7.5.6.29 Register 0x1F: Reserved
        30. 7.5.6.30 Register 0x66: Clock Flex Register
        31. 7.5.6.31 Register 0x6F: Clock Set Register
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Charge Pump Capacitors
        2. 8.2.2.2 Audio Input ac Coupling Capacitors
        3. 8.2.2.3 Suggested Output EMI Filter
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Decoupling Capacitors
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Pad Sizing
  11. 11Device and Documentation Support
    1. 11.1 Development Support
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

The ground terminal must be connected to the ground plane as close as possible to the TPA6166A2, to minimize any inductance in the path. Place the decoupling capacitor as close as possible to the supply terminal, minimizing trace length (and thus the inductance) on the decoupling capacitor connection to ground.

Because INL and INR are single-ended inputs, take care to minimize noise on INL and INR with respect to TPA6166A2 ground. This is best achieved by using then same ground plane for the signal source and the TPA6166A2 with a minimum inductance between them.

The accessory-detection algorithm requires trace capacitance to be minimized between TPA6166A2 and the jack. Depending upon headphone impedance, trace resistance between TPA6166A2 and the jack impacts power delivered to load. If trace resistance is much smaller than headphone impedance, power loss is given by Equation 4. Trace resistance should be minimized based on acceptable power loss.

Equation 4. Eq_Pwrloss_los714_.gif

To minimize crosstalk, trace resistance on RING2 (terminal 3) and SLEEVE (terminal 4) should be minimized. This can be achieved by placing TPA6166A2 close to the jack. For cases where trace resistance is not small, crosstalk is given by Equation 5. In such scenarios, best balance can be achieved by increasing trace width of SLEEVE. RING2 has no constraint on maximum capacitance, and its trace width can be maximized to achieve desired crosstalk performance.

Equation 5. Eq_Crosstalk_los714_.gif

10.2 Layout Example

10.2.1 Pad Sizing

When determining the pad size for the WCSP terminals, use nonsolder mask defined (NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the opening size is defined by the copper pad width. Figure 35 and Table 8 show the appropriate diameters for a WCSP layout.

M0200-01_LOS675.gifFigure 35. Land Pattern Dimensions

Table 8. Land Pattern Dimensions (1)(2)(3)(4)

SOLDER PAD DEFINITION COPPER PAD SOLDER MASK(5) OPENING COPPER THICKNESS STENCIL(6)(7)
OPENING		 STENCIL THICKNESS
Nonsolder mask defined (NSMD) 230 μm 310 μm 1 oz. max. (32 μm) 275 μm × 275 μm sq. (rounded corners) 100 μm thick
(1) Circuit traces from NSMD-defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside the solder mask opening. Wider trace widths reduce device standoff and impact reliability.
(2) Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating range of the intended application.
(3) Recommended solder paste is type 3 or type 4.
(4) For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in thermal fatigue performance.
(5) Solder mask thickness should be less than 20 µm on top of the copper circuit pattern.
(6) Best solder stencil performance is achieved using laser-cut stencils with electro polishing. Use of chemically etched stencils results in inferior solder paste volume control.
(7) Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional component movement due to solder wetting forces.

Table 9. Package Dimensions

D E
Max. = 2470 µm Max. = 2470 µm
Typ. = 2440 µm Typ. = 2440 µm
Min. = 2410 µm Min. = 2410 µm