SLOS490C July   2006  – November 2015

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Operating Characteristics
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Differential Amplifiers
        1. 9.3.1.1 Advantages of Fully Differential Amplifiers
      2. 9.3.2 Fully Differential Amplifier Efficiency and Thermal Information
      3. 9.3.3 Differential Output Versus Single-Ended Output
    4. 9.4 Device Functional Modes
      1. 9.4.1 Summing Input Signals With The TPA6205A1
        1. 9.4.1.1 Summing Two Differential Input Signals
        2. 9.4.1.2 Summing a Differential Input Signal and a Single-Ended Input Signal
        3. 9.4.1.3 Summing Two Single-Ended Input Signals
      2. 9.4.2 Shutdown Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA6205A1 With Differential Input
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Selecting Components
            1. 10.2.1.2.1.1 Resistors (RF and RI)
            2. 10.2.1.2.1.2 Bypass Capacitor (CBYPASS) and Start-Up Time
            3. 10.2.1.2.1.3 Input Capacitor (CI)
            4. 10.2.1.2.1.4 Decoupling Capacitor (CS)
          2. 10.2.1.2.2 Using Low-ESR Capacitors
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPA6205A1 With Differential Input and Input Capacitors
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 TPA6205A1 With Single-Ended Input
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Layout

12.1 Layout Guidelines

Placing the decoupling capacitors as close as possible to the device is important for the efficiency of the class-D amplifier. Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency.

For the DRB (QFN/SON) and DGN (MSOP) to presence of voids within the exposed thermal pad interconnection. Total elimination is difficult, but the design of the exposed pad stencil is key. The stencil design proposed in the Texas Instruments application note QFN/SON PCB Attachment (SLUA271) enables out-gassing of the solder paste during reflow as well as regulating the finished solder thickness. Typically the solder paste coverage is approximately 50% of the pad area.

In making the pad size for the BGA balls, it is recommended that the layout use soldermask-defined (SMD) land. With this method, the copper pad is made larger than the desired land area, and the opening size is defined by the opening in the solder mask material. The advantages normally associated with this technique include more closely controlled size and better copper adhesion to the laminate. Increased copper also increases the thermal performance of the IC. Better size control is the result of photo imaging the stencils for masks. Small plated vias should be placed near the center ball connecting ball B2 to the ground plane. Added plated vias and ground plane act as a heatsink and increase the thermal performance of the device. Figure 38 shows the appropriate diameters for a 2 mm × 2 mm MicroStar Junior™ BGA layout.

It is very important to keep the TPA6205A1 external components very close to the TPA6205A1 to limit noise pickup. The TPA6205A1 layout is shown in the next section as a layout example.

SLOS490TPA6205A1 layout_ex_slos490.gif Figure 38. MicroStar Junior™ BGA Recommended Layout

12.2 Layout Example

SLOS490TPA6205A1 TPA6205A1_BGA_Layout.gif Figure 39. TPA6205A1 BGA Layout
SLOS490TPA6205A1 TPA6205A1_HVSSOP_Layout.gif Figure 40. TPA6205A1 HVSSOP Layout
SLOS490TPA6205A1 TPA6205A1_VSON_Layout.gif Figure 41. TPA6205A1 VSON Layout