SLVS639F October 2007 – February 2016 TPD12S521
PRODUCTION DATA.
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
PIN | TYPE | ESD | DESCRIPTION | |
---|---|---|---|---|
NAME | NO. | |||
5V_SUPPLY | 1 | PWR | 2 kV(1) | Current source for 5V_OUT. |
LV_SUPPLY | 2 | Bias for CE/DDC/HOTPLUG level shifters. | ||
GND, TMDS_GND | 3, 5, 8, 11,14, 25, 28, 31, 34, 36 | GND | NA | TMDS ESD and parasitic GND return. |
TMDS_D2+ | 4, 35 | ESD clamp | 8 kV(2) | TMDS 0.8-pF ESD protection.(3) |
TMDS_D2– | 6, 33 | |||
TMDS_D1+ | 7, 32 | |||
TMDS_D1– | 9, 30 | |||
TMDS_D0+ | 10, 29 | |||
TMDS_D0– | 12, 27 | |||
TMDS_CK+ | 13, 26 | |||
TMDS_CK– | 15, 24 | |||
CE_REMOTE_IN | 16 | IO | 2 kV(1) | LV_SUPPLY referenced logic level into ASIC. |
DDC_CLK_IN | 17 | |||
DDC_DAT_IN | 18 | |||
HOTPLUG_DET_IN | 19 | |||
HOTPLUG_DET_OUT | 20 | IO, ESD clamp | 8 kV(2) | 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD(4) to connector. |
DDC_DAT_OUT | 21 | 5 V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector. | ||
DDC_CLK_OUT | 22 | |||
CE_REMOTE_OUT | 23 | IO, ESD clamp | 8 kV(2) | 3.3-V_SUPPLY referenced logic level out, plus 3.5-pF ESD to connector. |
ESD_BYP | 37 | ESD Bypass | 2 kV(1) | ESD bypass. This pin must be connected to a 0.1-µF ceramic capacitor. |
5V_OUT | 38 | PWR | 2 kV(1) | 5-V regulator output |