JAJSL01A
May 2021 – December 2021
TPD1E01B04-Q1
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings—AEC Specification
6.3
ESD Ratings—IEC Specification
6.4
ESD Ratings—ISO Specification
6.5
Recommended Operating Conditions
6.6
Thermal Information
6.7
Electrical Characteristics
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
IEC 61000-4-2 ESD Protection
7.3.2
IEC 61000-4-4 EFT Protection
7.3.3
IEC 61000-4-5 Surge Protection
7.3.4
IO Capacitance
7.3.5
DC Breakdown Voltage
7.3.6
Ultra Low Leakage Current
7.3.7
Low ESD Clamping Voltage
7.3.8
Supports High Speed Interfaces
7.3.9
Industrial Temperature Range
7.3.10
Easy Flow-Through Routing Package
7.4
Device Functional Modes
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Signal Range
8.2.2.2
Operating Frequency
8.2.3
Application Curves
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Documentation Support
11.1.1
Related Documentation
11.2
Receiving Notification of Documentation Updates
11.3
サポート・リソース
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
メカニカル・データ(パッケージ|ピン)
DPY|2
サーマルパッド・メカニカル・データ
発注情報
jajsl01a_oa
6.8
Typical Characteristics
Figure 6-1
Positive TLP Curve
Figure 6-3
8-kV IEC Waveform
Figure 6-5
Surge Curve (t
p
= 8/20µs), IO pin to GND
Figure 6-7
Capacitance vs. Bias Voltage (DPY Package)
Figure 6-9
DC Voltage Sweep I-V Curve
Figure 6-11
Insertion Loss
Figure 6-2
Negative TLP Curve
Figure 6-4
–8-kV IEC Waveform
Figure 6-6
Capacitance vs. Bias Voltage
Figure 6-8
Leakage Current vs. Temperature
Figure 6-10
Capacitance vs. Frequency