JAJSL01A May   2021  – December 2021 TPD1E01B04-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  IEC 61000-4-2 ESD Protection
      2. 7.3.2  IEC 61000-4-4 EFT Protection
      3. 7.3.3  IEC 61000-4-5 Surge Protection
      4. 7.3.4  IO Capacitance
      5. 7.3.5  DC Breakdown Voltage
      6. 7.3.6  Ultra Low Leakage Current
      7. 7.3.7  Low ESD Clamping Voltage
      8. 7.3.8  Supports High Speed Interfaces
      9. 7.3.9  Industrial Temperature Range
      10. 7.3.10 Easy Flow-Through Routing Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range
        2. 8.2.2.2 Operating Frequency
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DPY|2
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO < 10 nA –3.6 3.6 V
VBRF Breakdown voltage, IO pin to GND Measured as the maximum voltage before device snaps back into VHOLD voltage 6.4 V
VBRR Breakdown voltage, GND to IO pin –6.4 V
VHOLD Holding voltage IIO = 1 mA, TA = 25°C 5 5.9 6.5 V
VCLAMP Clamping voltage IPP = 1 A, TLP, from IO to GND 7 V
IPP = 5 A, TLP, from IO to GND 9.2
IPP = 16 A, TLP, from IO to GND 15
IPP = 1 A, TLP, from GND to IO 7
IPP = 5 A, TLP, from GND to IO 9.2
IPP = 16 A, TLP, from GND to IO 15
ILEAK Leakage current, IO to GND VIO = ±2.5 V 10 nA
RDYN Dynamic resistance IO to GND 0.57 Ω
GND to IO 0.57
CL Line capacitance VIO = 0 V, f = 1 MHz, IO to GND, TA = 25°C 0.2 0.23 pF